CHAPTER 4 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS
User’s Manual U16290EJ1V0UM
37
Figure 4-1. Equivalent Circuit of Emulation Circuit 1
100
Ω
100
Ω
100
Ω
1 M
Ω
100 k
Ω
LV
CC
Port 0
(KR00 to KR07)
Port 1
Port 2
Port 3
V
LC0
to V
LC4
CAP0 to CAP3
Port 6
Port 8
LCD0 to LCD87
Port 0
(KR00 to KR07)
Port 1
Port 2
Port 3
Port 6
Port 8
LCD0 to LCD87
Emulation circuit
ICE side
USR side
SW2 to SW6
RD7.5SB2
(V
LC0
only)
V
LC0
to V
LC4
CAP0 to CAP3
HC4066
Check point block
(Through hole)
Probe side
(Target system)
IE system side
(2) Signals input from the target system via a gate
Since the following signals are input via a gate, their signals show a delay compared to the
µ
PD789835
Subseries. Refer to
Figure 4-2 Equivalent Circuit of Emulation Circuit 2
.
•
RESET signal
•
Signals related to clock input
The X2 (CL2) and XT2 pins are not used in the IE-789835-NS-EM1.
•
SEL pin
The SEL pin is not used in the IE-789835-NS-EM1. The IE system is fixed to ceramic/crystal oscillation.
•
V
ROUT
pin
The V
ROUT
pin is not used in the IE-789835-NS-EM1. This pin is connected to GND via a capacitor of 47
µ
F in
the IE system.
