CHAPTER 4 CAUTIONS
User’s Manual U14700EJ2V0UM
35
4.5
Bus Control Pins
There are the following differences between the emulator and the target device in the operation of the pins for bus
control.
Table 4-2. Bus Control Pin Operation List (1/2)
(a) During break
Internal Memory
External Memory
Internal
ROM
Internal RAM
On-Chip
Peripheral I/O
Emulation RAM
Target System
Pin Name
Waiting for Emulator
Command
R
R
W
R
W
R
W
R
W
AD0 to AD15
Hi-Z
Hi-Z
Note
Note
A16 to A23
Address accessed last is
held
Address accessed last is held
Note
Note
CS0 to CS7
H
H
H
Note
RD
H
H
H
Note
ASTB
H
H
Note
Note
LWR, UWR
H
H
H
Note
WAIT
Invalid
Invalid
Maskable
Maskable
HLDRQ
Maskable
Maskable
Maskable
Maskable
HLDAK
Note
Note
Note
Note
Note
Performs the same operation as the cycle that is generated by the target device program execution.
Remarks 1.
R:
Read
W:
Write
2.
H:
High-level output
Hi-Z: High-impedance