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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

User’s Manual U18172EJ2V0UD

Figure 6-16. External Event Counter Configuration Diagram

16-bit timer capture/compare

16-bit timer counter 00 (TM00)

Internal bus

Match

Clear

OVF00

Note

INTTM000

Noise eliminator

Valid edge of TI000

Note

OVF00 is 1 only when 16-bit timer capture/compare register 000 is set to FFFFH.

Figure 6-17. External Event Counter Operation Timing (with Rising Edge Specified)

(1) INTTM000 generation timing immediately after operation starts

Counting is started after a valid edge is detected twice.

CR000

INTTM000

0000H 0001H 0002H 0003H

N–2

N–1

0000H 0001H 0002H

Count starts

TI000 pin input

TM00 count value

Timer operation starts

(2) INTTM000 generation timing after INTTM000 has been generated twice

CR000

INTTM000

0000H 0001H 0002H 0003H 0004H

N–1

0000H 0001H 0002H 0003H

TI000 pin input

TM00 count value

Caution When reading the external event counter count value, TM00 should be read.

Summary of Contents for 78K0S/KU1+

Page 1: ...User s Manual µPD78F9200 µPD78F9201 µPD78F9202 78K0S KU1 8 Bit Single Chip Microcontrollers Printed in Japan Document No U18172EJ2V0UD00 2nd edition Date Published January 2008 NS 2006 ...

Page 2: ...User s Manual U18172EJ2V0UD 2 MEMO ...

Page 3: ... including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON d...

Page 4: ...lity for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to ...

Page 5: ...scription How to Use This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers To understand the overall functions of 78K0S KU1 Read this manual in the order of the CONTENTS The mark R shows major revised points The revised points can be easily searched by copying an R in the PDF file and specifying it in the Find...

Page 6: ...Name Document No 78K0S KU1 User s Manual This manual 78K 0S Series Instructions User s Manual U11047E Documents Related to Development Software Tools User s Manuals Document Name Document No Operation U16656E Language U14877E RA78K0S Assembler Package Structured Assembly Language U11623E Operation U16654E CC78K0S C Compiler Language U14872E ID78K0S QB Ver 2 81 Integrated Debugger Operation U17287E...

Page 7: ...ages X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Note See the Semiconductor Device Mount Manual website http www necel com pkg en mount index html Caution The related documents listed abov...

Page 8: ...R 3 CPU ARCHITECTURE 26 3 1 Memory Space 26 3 1 1 Internal program memory space 29 3 1 2 Internal data memory space 30 3 1 3 Special function register SFR area 30 3 1 4 Data memory addressing 30 3 2 Processor Registers 33 3 2 1 Control registers 33 3 2 2 General purpose registers 36 3 2 3 Special function registers SFRs 37 3 3 Instruction Address Addressing 41 3 3 1 Relative addressing 41 3 3 2 Im...

Page 9: ... 4 1 High speed internal oscillator 70 5 4 2 Crystal ceramic oscillator 70 5 4 3 External clock input circuit 72 5 4 4 Prescaler 72 5 5 Operation of CPU Clock Generator 73 5 6 Operation of Clock Generator Supplying Clock to Peripheral Hardware 79 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 81 6 1 Functions of 16 Bit Timer Event Counter 00 81 6 2 Configuration of 16 Bit Timer Event Counter 00 82 6 3 Re...

Page 10: ...4 4 Watchdog timer operation in HALT mode when low speed internal oscillator can be stopped by software is selected by option byte 147 CHAPTER 9 A D CONVERTER 148 9 1 Functions of A D Converter 148 9 2 Configuration of A D Converter 150 9 3 Registers Used by A D Converter 152 9 4 A D Converter Operations 157 9 4 1 Basic operations of A D converter 157 9 4 2 Input voltage and conversion results 159...

Page 11: ...tage Detector 206 CHAPTER 15 OPTION BYTE 209 15 1 Functions of Option Byte 209 15 2 Format of Option Byte 210 15 3 Caution When the RESET Pin Is Used as an Input Only Port Pin P34 211 CHAPTER 16 FLASH MEMORY 212 16 1 Features 212 16 2 Memory Configuration 213 16 3 Functional Outline 213 16 4 Writing with Flash Memory Programmer 214 16 5 Programming Environment 215 16 6 Processing of Pins on Board ...

Page 12: ... Connecting QB MINI2 to 78K0S KU1 268 17 1 1 Connection of INTP1 pin 269 17 1 2 Connection of X1 and X2 pins 270 17 2 Securing of user resources 271 CHAPTER 18 INSTRUCTION SET OVERVIEW 272 18 1 Operation 272 18 1 1 Operand identifiers and description methods 272 18 1 2 Description of Operation column 273 18 1 3 Description of Flag column 273 18 2 Operation List 274 18 3 Instructions Listed by Addr...

Page 13: ...18172EJ2V0UD 13 APPENDIX C REGISTER INDEX 304 C 1 Register Index Register Name 304 C 2 Register Index Symbol 306 APPENDIX D LIST OF CAUTIONS 308 APPENDIX E REVISION HISTORY 323 E 1 Major Revisions in This Edition 323 ...

Page 14: ...ower on clear POC circuit A reset is automatically generated when the voltage drops to 2 1 V 0 1 V or below O On chip low voltage detector LVI circuit An interrupt reset selectable is generated when the detection voltage is reached Detection voltage Selectable from ten levels between 2 35 and 4 3 V O Single power supply flash memory Flash self programming enabled Software protection function Prote...

Page 15: ...his product in a voltage range of 2 2 to 5 5 V because the detection voltage VPOC of the power on clear POC circuit is 2 1 V 0 1 V O Operating temperature range TA 40 to 85 C 1 2 Ordering Information Part Number µPD78F9 A Semiconductor component Blank Conventional A Lead free Quality Grades ...

Page 16: ...External interrupt input TO00 TOH1 Timer output P20 to P23 Port 2 VDD Note2 Power supply P30 P34 Port 3 VSS Note1 Ground P40 P43 Port 4 X1 X2 Crystal oscillator X1 input clock RESET Reset Notes 1 In the 78K0S KU1 VSS functions alternately as the ground potential of the A D converter Be sure to connect VSS to a stabilized GND 0 V 2 In the 78K0S KU1 VDD functions alternately as the A D converter ref...

Page 17: ...1 ch Note 3 8 bit TMH 1 ch 8 bit TM8 1 ch Timer WDT 1 ch Serial interface LIN Bus supporting UART 1 ch A D converter Note 4 10 bits 4 ch 2 7 to 5 5V Note 4 Multiplier 8 bits 8 bits Provided Internal 5 Note 5 9 Interrupts External 2 4 RESET pin Provided POC 2 1 V TYP LVI Provided selectable by software Reset WDT Provided Operating temperature range Standard products TA 40 to 85 C Standard products ...

Page 18: ...ER 00 TO00 TI010 P21 TI000 P20 TOH1 P20 8 bit TIMER H1 INTP0 P21 INTP1 P32 ANI0 P20 ANI3 P23 4 A D CONVERTER INTERRUPT CONTROL PORT 3 P32 P34 PORT 4 P40 P43 2 LOW SPEED INTERNAL OSCILLATOR WATCHDOG TIMER Notes 1 In the 78K0S KU1 VDD functions alternately as the A D converter reference voltage input When using the A D converter stabilize VDD at the supply voltage used 2 7 to 5 5 V 2 In the 78K0S KU...

Page 19: ...ime 0 2 µs 0 4 µs 0 8 µs 1 6 µs 3 2 µs X1 input clock fX 10 MHz I O port Total 8 pins CMOS I O 7 pins CMOS input 1 pin Timer 16 bit timer event counter 1 channel 8 bit timer timer H1 1 channel Watchdog timer 1 channel Timer output 2 pins PWM 1 pin A D converter 10 bit resolution 4 channels External 2 Vectored interrupt sources Internal 5 Reset Reset by RESET pin Internal reset by watchdog timer In...

Page 20: ...1 ANI3 Note 1 P32 I O Can be set to input or output mode in 1 bit units An on chip pull up resistor can be connected by setting software Input INTP1 P34 Note 1 Input Port 3 Input only Input RESET Note 1 P40 P43 Note 2 I O Port 4 2 bit I O port Can be set to input or output mode in 1 bit units An on chip pull up resistor can be connected by setting software Input Notes 1 For the setting method for ...

Page 21: ... counter 00 Input P21 ANI1 TO00 INTP0 TO00 Output 16 bit timer event counter 00 output Input P21 ANI1 TI010 INTP0 TOH1 Output 8 bit timer H1 output Input P20 ANI0 TI000 ANI0 P20 TI000 TOH1 ANI1 P21 TI010 TO00 INTP0 ANI2 Note P22 X2 Note ANI3 Note Input Analog input of A D converter Input P23 X1 Note RESET Note Input System reset input Input P34 Note X1 Note Input Connection of crystal ceramic osci...

Page 22: ...egister 2 PU2 2 Control mode P20 to P23 function to input an analog signal to the A D converter input output a timer signal and input an external interrupt request signal a ANI0 to ANI3 These are the analog input pins of the A D converter When using these pins as analog input pins refer to 9 6 Cautions for A D converter 5 ANI0 P20 to ANI3 P23 b TI000 This pin inputs an external count clock to 16 b...

Page 23: ...pecified 2 2 3 P40 and P43 Port 4 P40 and P43 constitute a 2 bit I O port Each bit of this port can be set to the input or output mode by using port mode register 4 PM4 Note In addition an on chip pull up resistor can be connected to the port by using pull up resistor option register 4 PU4 Note At program initialization set PM41 PM42 and PM44 to PM47 to 0 2 2 4 RESET This pin inputs an active low ...

Page 24: ...used Pins Pin Name I O Circuit Type I O Recommended Connection of Unused Pin P20 ANI0 TI000 TOH1 P21 ANI1 TI010 TO00 INTP0 11 Input Individually connect to VDD or VSS via resistor Output Leave open P22 ANI2 X2 P23 ANI3 X1 36 Input Individually connect to VSS via resistor Output Leave open P32 INTP1 8 A I O Input Individually connect to VDD or VSS via resistor Output Leave open P34 RESET 2 Input Co...

Page 25: ...P ch VDD P ch IN OUT N ch Data Output disable Pull up enable VDD P ch N ch IN OUT Comparison voltage VSS P ch N ch Input enable VDD P ch Comparator P ch feedback cut off X1 IN OUT X2 IN OUT OSC enable data output disable VDD P ch N ch VSS P ch N ch pullup enable VDD P ch data output disable VDD P ch N ch VSS P ch N ch pullup enable VDD P ch Comparator Comparator VSS VSS VSS Comparison voltage Comp...

Page 26: ...nternal high speed RAM 128 8 bits Flash memory 1 024 8 bits Use prohibited Program memory space Data memory space F F F F H F F 0 0 H F E F F H F E 8 0 H F E 7 F H 0 4 0 0 H 0 3 F F H 0 0 0 0 H Program area Option byte area Program area CALLT table area Vector table area 0 3 F F H 0 0 4 0 H 0 0 3 F H 0 0 1 4 H 0 0 1 3 H 0 0 0 0 H Protect byte area 0 0 8 2 H 0 0 8 1 H 0 0 8 0 H 0 0 7 F H Remark The...

Page 27: ...bits Program memory space Data memory space Use prohibited F F F F H F F 0 0 H F E F F H F E 8 0 H F E 7 F H 0 8 0 0 H 0 7 F F H 0 0 0 0 H Program area Option byte area Program area CALLT table area Vector table area 0 7 F F H 0 0 4 0 H 0 0 3 F H 0 0 1 4 H 0 0 1 3 H 0 0 0 0 H Protect byte area 0 0 8 2 H 0 0 8 1 H 0 0 8 0 H 0 0 7 F H Remark The option byte and protect byte are 1 byte each ...

Page 28: ...bits Program memory space Data memory space Use prohibited F F F F H F F 0 0 H F E F F H F E 8 0 H F D 7 F H 1 0 0 0 H 0 F F F H 0 0 0 0 H Program area Option byte area Program area CALLT table area Vector table area 0 F F F H 0 0 4 0 H 0 0 3 F H 0 0 1 4 H 0 0 1 3 H 0 0 0 0 H Protect byte area 0 0 8 2 H 0 0 8 1 H 0 0 8 0 H 0 0 7 F H Remark The option byte and protect byte are 1 byte each ...

Page 29: ...table area This area stores program start addresses to be used when branching by RESET or interrupt request generation Of a 16 bit address the lower 8 bits are stored in an even address and the higher 8 bits are stored in an odd address Table 3 2 Vector Table Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H Reset 000CH INTTMH1 0006H INTLVI 000EH INTTM000 0008H IN...

Page 30: ...ssing modes to make memory manipulation as efficient as possible The area FE80H to FEFFH which contains a data memory and the special function register SFR area can be accessed using a unique addressing mode in accordance with each function Figures 3 4 to 3 6 illustrate the data memory addressing Figure 3 4 Data Memory Addressing µPD78F9200 Special function registers SFR 256 8 bits Internal high s...

Page 31: ... function registers SFR 256 8 bits Internal high speed RAM 128 8 bits Flash memory 2 048 8 bits Use prohibted Direct addressing Register indirect addressing Based addressing SFR addressing Short direct addressing F F F F H F F 0 0 H F E F F H F F 2 0 H F E 1 F H F E 8 0 H F E 7 F H 0 8 0 0 H 0 7 F F H 0 0 0 0 H ...

Page 32: ... function registers SFR 256 8 bits Internal high speed RAM 128 8 bits Flash memory 4 096 8 bits Use prohibted Direct addressing Register indirect addressing Based addressing SFR addressing Short direct addressing F F F F H F F 0 0 H F E F F H F F 2 0 H F E 1 F H F E 8 0 H F E 7 F H 1 0 0 0 H 0 F F F H 0 0 0 0 H ...

Page 33: ...of the instruction to be fetched When a branch instruction is executed immediate data or register contents are set Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 7 Program Counter Configuration 0 15 PC14 PC15 PC PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 2 Program status word PSW The program status word is an...

Page 34: ...0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI instruction execution b Zero flag Z When the operation result is zero this flag is set to 1 It is reset to 0 in all other cases c Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set to 1 It is reset to 0 in all other cases d Carry flag CY This flag stores ove...

Page 35: ...ly to the high speed RAM area and only the lower 10 bits can be actually set 0FF00H is in the SFR area not the high speed RAM area so it was converted to 0FB00H that is in the high speed RAM area When the value is actually pushed onto the stack 1 is subtracted from 0FB00H to become 0FAFFH but that value is not in the high speed RAM area so it is converted to 0FEFFH which is the same value as when ...

Page 36: ...t registers in pairs can be used as a 16 bit register AX BC DE and HL Registers can be described in terms of function names X A C B E D L H AX BC DE and HL and absolute names R0 to R7 and RP0 to RP3 Figure 3 12 General Purpose Register Configuration a Function names X 15 0 7 0 16 bit processing 8 bit processing HL DE BC AX A C B E D L H b Absolute names R0 15 0 7 0 16 bit processing 8 bit processi...

Page 37: ...bit manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describes a symbol reserved by the assembler for the 16 bit manipulation instruction operand When specifying an address describe an even address Table 3 3 lists the special function registers The meanings of the symbols in this table are as follows Symbol Indicates the addresses of ...

Page 38: ...21H FF22H PM2 1 1 1 1 PM23 PM22 PM21 PM20 FFH 59 FF23H PM3 1 1 1 1 1 PM32 1 1 FFH 59 FF24H PM4 1 1 1 1 PM43 1 1 PM40 R W FFH 59 FF25H to FF31H FF32H PU2 0 0 0 0 PU23 PU22 PU21 PU20 00H 62 FF33H PU3 0 0 0 0 0 PU32 0 0 00H 62 FF34H PU4 0 0 0 0 PU43 0 0 PU40 R W 00H 62 FF35H to FF47H FF48H WDTM 0 1 1 WDCS 4 WDCS 3 WDCS 2 WDCS 1 WDCS 0 67H 140 FF49H WDTE 9AH 141 FF50H LVIM LVI ON 0 0 0 0 0 LVI MD LVI ...

Page 39: ...1 CKS10 TMMD 11 TMMD 10 TOLE V1 TOEN 1 R W 00H 125 FF71H to FF7FH FF80H ADM ADCS 0 FR2 FR1 FR0 0 0 ADCE 00H 152 FF81H ADS 0 0 0 0 0 0 ADS1 ADS0 R W 00H 155 FF82H FF83H FF84H PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20 R W 00H 60 FF85H to FF9FH FFA0H PFCMD REG7 REG6 REG5 REG4 REG3 REG2 REG1 REG0 W Undefined 227 FFA1H PFS 0 0 0 0 0 WEPR ERR VCE RR FPR ERR 00H 227 FFA2H FLPMC 0 PRSEL F4 PRSEL F3 PRSEL F2 PR...

Page 40: ...0 LVIIF 0 R W 00H 170 FFE1H to FFE3H FFE4H MK0 ADM K TMM K010 TMM K000 TMM KH1 PMK 1 PMK 0 LVI MK 1 R W FFH 171 FFE5H to FFEBH FFECH INTM0 0 0 ES11 ES10 ES01 ES00 0 0 R W 00H 171 FFEDH to FFF2H FFF3H PPCC 0 0 0 0 0 0 PPCC1 PPCC0 02H 67 FFF4H OSTS 0 0 0 0 0 0 OSTS1 OSTS0 R W Undefined Note 69 FFF5H to FFFAH FFFBH PCC 0 0 0 0 0 0 PCC1 0 R W 02H 67 Note The oscillation stabilization time that elapses...

Page 41: ...Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC to branch The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes the sign bit In other words the range of branch in relative addressing is be...

Page 42: ...r High addr PC PC 1 PC 2 3 3 3 Table indirect addressing Function The table contents branch destination address of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter PC to branch Table indirect addressing is carried out when the CALLT addr5 instruction is executed This instruction can be used to branch to ...

Page 43: ... 4 Register addressing Function The register pair AX contents to be specified with an instruction word are transferred to the program counter PC to branch This function is carried out when the BR AX instruction is executed Illustration 7 0 rp 0 7 A X 15 0 PC 8 7 ...

Page 44: ...ruction execution 3 4 1 Direct addressing Function The memory indicated by immediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A FE80H When setting addr16 to FE80H Instruction code 0 0 1 0 1 0 0 1 OP Code 1 0 0 0 0 0 0 0 80H 1 1 1 1 1 1 1 0 FEH Illustration 7 0 OP code addr16 low addr16 high...

Page 45: ... mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 80H to FFH bit 8 of an effective address is cleared to 0 When it is at 00H to 1FH bit 8 is set to 1 See Illustration below Identifier Description saddr Label or FE80H to FF1FH immediate data saddrp Label or FE80H to FF1FH immediate data even address only Description example EQU DATA1 0...

Page 46: ...ction word This addressing is applied to the 256 byte space FF00H to FFFFH However SFRs mapped at FF00H to FF1FH are accessed with short direct addressing Operand format Identifier Description sfr Special function register name Description example MOV PM0 A When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 Illustration 15 0 SFR Effective address 1 1 1 1 1 1 1 8 7 0 7 OP c...

Page 47: ...at is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described with absolute names R0 to R7 and RP0 to RP3 as well as function names X A C B E D L H AX BC DE and HL Description example MOV A C When selecting the C register for r Instructio...

Page 48: ... accessed is specified with the register pair specify code in the instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE When selecting register pair DE Instruction code 0 0 1 0 1 0 1 1 Illustration 15 0 8 D 7 E 0 7 7 0 A DE The contents of addressed memory are transferred Memory address specified by re...

Page 49: ...ddition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL byte Description example MOV A HL 10H When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 Illustration 16 0 8 H 7 L 0 7 7 0 A HL The contents of addressed me...

Page 50: ...hod is automatically employed when the PUSH POP subroutine call and return instructions are executed or the register is saved restored upon interrupt request generation Stack addressing can be used to access the internal high speed RAM area only Description example In the case of PUSH DE Instruction code 1 0 1 0 1 0 1 0 Illustration FEE0H FEE0H FEDFH FEDEH D E FEDEH SP SP 7 0 Memory ...

Page 51: ...n 1 bit units On chip pull up resistor can be connected by setting software Input X1 ANI3 Note 1 P32 I O Can be set to input or output mode in 1 bit units On chip pull up resistor can be connected by setting software Input INTP1 P34 Note 1 Input Port 3 Input only Input RESET Note 1 P40 and P43 Note 2 I O Port 4 2 bit I O port Can be set to input or output mode in 1 bit units On chip pull up resist...

Page 52: ... P22 and P23 pins are also used as the X2 and X1 pins of the system clock oscillator The functions of the P22 and P23 pins differ therefore depending on the selected system clock oscillator The following three system clock oscillators can be used 1 High speed internal oscillator The P22 and P23 pins can be used as I O port pins or analog input pins to the A D converter 2 Crystal ceramic oscillator...

Page 53: ...00 INTP0 RD WRPM PM20 PM21 PM2 WRPORT WRPU PU20 PU21 VDD P ch PU2 PMC2 PMC20 PMC21 A D converter Alternate function Alternate function Selector Output latch P20 P21 Internal bus P2 WRPMC P2 Port register 2 PU2 Pull up resistor option register 2 PM2 Port mode register 2 PMC2 Port mode control register 2 RD Read signal WR Write signal ...

Page 54: ... P22 P22 ANI2 X2 WRPU WRPMC RD PU22 WRPM PM22 VDD P ch PU2 PM2 WRPORT Output latch P22 A D converter PMC2 PMC22 Internal bus Selector P2 P2 Port register 2 PU2 Pull up resistor option register 2 PM2 Port mode register 2 PMC2 Port mode control register 2 RD Read signal WR Write signal ...

Page 55: ... P23 P23 ANI3 X1 WRPU WRPMC RD PU23 WRPM PM23 VDD P ch PU2 PMC2 PM2 WRPORT Output latch P23 PMC23 A D converter Internal bus Selector P2 P2 Port register 2 PU2 Pull up resistor option register 2 PM2 Port mode register 2 PMC2 Port mode control register 2 RD Read signal WR Write signal ...

Page 56: ...t signal generation sets port 3 to the input mode The P34 pin is a 1 bit input only port This pin is also used as a RESET pin and when the power is turned on this is the reset function For the setting method for pin functions see CHAPTER 15 OPTION BYTE When P34 is used as an input port pin connect the pull up resistor Figures 4 5 and 4 6 show the block diagrams of port 3 Figure 4 5 Block Diagram o...

Page 57: ...er the reset release if low level is input to the RESET pin before the referencing then the reset state is not released When it is used as an input port pin connect the pull up resistor 4 2 3 Port 4 Port 4 is a 2 bit I O port with an output latch Each bit of this port can be set to the input or output mode by using port mode register 4 PM4 Note When the P40 and P43 pins are used as an input port a...

Page 58: ... latch P40 P43 Selector P4 P4 Port register 4 PU4 Pull up resistor option register 4 PM4 Port mode register 4 RD Read signal WR Write signal 4 3 Registers Controlling Port Functions The ports are controlled by the following four types of registers Port mode registers PM2 to PM4 Port registers P2 to P4 Port mode control register 2 PMC2 Pull up resistor option registers PU2 to PU4 ...

Page 59: ...ding interrupt request flag is set if each of these pins is set to the output mode and its output level is changed To use the port pin in the output mode therefore set the corresponding interrupt mask flag to 1 in advance Figure 4 8 Format of Port Mode Register Address FF22H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 1 1 PM23 PM22 PM21 PM20 Address FF23H After reset FFH R W Symbol 7 6 5 4 ...

Page 60: ...2 1 0 P2 0 0 0 0 P23 P22 P21 P20 Address FF03H After reset 00H Note Output latch R W Note Symbol 7 6 5 4 3 2 1 0 P3 0 0 0 P34 0 P32 0 0 Address FF04H After reset 00H Output latch R W Symbol 7 6 5 4 3 2 1 0 P4 0 0 0 0 P43 0 0 P40 m 2 to 4 n 0 to 4 Pmn Controls of output data in output mode Input data read in input mode 0 Output 0 Input low level 1 Output 1 Input high level Note Because P34 is read ...

Page 61: ......

Page 62: ... a 1 bit or 8 bit memory manipulation instruction Reset signal generation set these registers to 00H Figure 4 11 Format of Pull up Resistor Option Register Address FF32H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU2 0 0 0 0 PU23 PU22 PU21 PU20 Address FF33H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU3 0 0 0 0 0 PU32 0 0 Address FF34H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU4 0 0 0 0 PU43 0...

Page 63: ...wever the pin status remains unchanged Once data is written to the output latch it is retained until new data is written to the output latch When a reset signal is generated cleans the data in the output latch 4 4 2 Reading from I O port 1 In output mode The contents of the output latch can be read by a transfer instruction The contents of the output latch remain unchanged 2 In input mode The pin ...

Page 64: ...and X2 pins It can oscillate a clock of 2 MHz to 10 MHz Oscillation of this circuit can be stopped by execution of the STOP instruction External clock input circuit This circuit supplies a clock from an external IC to the X1 pin A clock of 2 MHz to 10 MHz can be supplied Internal clock supply can be stopped by execution of the STOP instruction If the external clock input is selected as the system ...

Page 65: ...tion of Clock Generators Item Configuration Control registers Processor clock control register PCC Preprocessor clock control register PPCC Low speed internal oscillation mode register LSRCM Oscillation stabilization time select register OSTS Oscillators Crystal ceramic oscillator High speed internal oscillator External clock input circuit Low speed internal oscillator ...

Page 66: ... 22 fRL LSRSTOP CPU System clock oscillation stabilization time counter Selector Prescaler Clock to peripheral hardware fXP 8 bit timer H1 watchdog timer Option byte 1 Cannot be stopped 0 Can be stopped Low speed internal oscillation mode register LSRCM Low speed internal oscillator Prescaler System clock oscillatorNote External clock input Crystal ceramic oscillation High speed internal oscillati...

Page 67: ... set by using a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets PCC and PPCC to 02H Figure 5 2 Format of Processor Clock Control Register PCC Address FFFBH After reset 02H R W Symbol 7 6 5 4 3 2 1 0 PCC 0 0 0 0 0 0 PCC1 0 Figure 5 3 Format of Preprocessor Clock Control Register PPCC Address FFF3H After reset 02H R W Symbol 7 6 5 4 3 2 1 0 PPCC 0 0 0 0 0 0 PPCC1 PPCC0 PP...

Page 68: ...llation mode register LSRCM This register is used to select the operation mode of the low speed internal oscillator 240 kHz TYP This register is valid when it is specified by the option byte that the low speed internal oscillator can be stopped by software If it is specified by the option byte that the low speed internal oscillator cannot be stopped by software setting of this register is invalid ...

Page 69: ...TS Address FFF4H After reset Undefined R W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 0 OSTS1 OSTS0 OSTS1 OSTS0 Selection of oscillation stabilization time 0 0 2 10 fX 102 4 µs 0 1 2 12 fX 409 6 µs 1 0 2 15 fX 3 27 ms 1 1 2 17 fX 13 1 ms Cautions 1 To set and then release the STOP mode set the oscillation stabilization time as follows Expected oscillation stabilization time of resonator Oscillation sta...

Page 70: ...etween the X1 and X2 pins If the crystal ceramic oscillator is selected by the option byte as the system clock source the X1 and X2 pins are used as crystal or ceramic resonator connection pins For details of the option byte refer to CHAPTER 15 OPTION BYTE For details of I O ports refer to CHAPTER 4 PORT FUNCTIONS Figure 5 6 shows the external circuit of the crystal ceramic oscillator Figure 5 6 E...

Page 71: ...7 Examples of Incorrect Resonator Connection 1 2 a Too long wiring of connected circuit b Crossed signal lines VSS X1 X2 VSS X1 X2 PORT c Wiring near high fluctuating current d Current flowing through ground line of oscillator Potential at points A B and C fluctuates VSS X1 X2 High current VSS X1 X2 PORT VDD A B C High current ...

Page 72: ... option byte refer to CHAPTER 15 OPTION BYTE For details of I O ports refer to CHAPTER 4 PORT FUNCTIONS 5 4 4 Prescaler The prescaler divides the clock fX output by the system clock oscillator to generate a clock fXP to be supplied to the peripheral hardware It also divides the clock to peripheral hardware fXP to generate a clock to be supplied to the CPU Remark The clock output by the oscillator ...

Page 73: ... speed internal oscillator is selected as the oscillator the CPU can be started without having to wait for the oscillation stabilization time of the system clock Therefore the start time can be shortened Improvement of expandability If the high speed internal oscillator is selected as the oscillator the X1 and X2 pins can be used as I O port pins For details refer to CHAPTER 4 PORT FUNCTIONS Figur...

Page 74: ...high speed internal oscillation clock operates as the system clock Figure 5 9 Status Transition of Default Start by High Speed internal oscillation HALT instruction STOP instruction VDD 2 1 V 0 1 V Start with PCC 02H PPCC 02H HALT STOP Interrupt Reset signal Interrupt Power application Reset by power on clear Clock division ratio variable during CPU operation High speed internal oscillator selecte...

Page 75: ... 2 Notes 1 Operation stop time is 276 µs MIN 544 µs TYP and 1 074 ms MAX 2 The clock oscillation stabilization time for default start is selected by the option byte For details refer to CHAPTER 15 OPTION BYTE The oscillation stabilization time that elapses after the STOP mode is released is selected by the oscillation stabilization time select register OSTS a The internal reset signal is generated...

Page 76: ...STOP instruction Start with PCC 02H PPCC 02H Interrupt Reset signal Interrupt Power application Clock division ratio variable during CPU operation Wait for clock oscillation stabilization Crystal ceramic oscillation selected by option byte Reset by power on clear VDD 2 1 V 0 1 V Remark PCC Processor clock control register PPCC Preprocessor clock control register ...

Page 77: ...s an I O port pin For details refer to CHAPTER 4 PORT FUNCTIONS Figures 5 12 and 5 13 show the timing chart and status transition diagram of default start by external clock input Figure 5 12 Timing of Default Start by External Clock Input VDD a b External clock input PCC 02H PPCC 02H H RESET System clock Internal reset CPU clock Option byte is read System clock is selected Operation stopsNote Note...

Page 78: ...TOP HALT instruction STOP instruction VDD 2 1 V 0 1 V Start with PCC 02H PPCC 02H Interrupt Reset signal Interrupt Power application Reset by power on clear External clock input selected by option byte Clock division ratio variable during CPU operation Remark PCC Processor clock control register PPCC Preprocessor clock control register ...

Page 79: ...cannot be stopped by software If it is specified that the low speed internal oscillator can be stopped by software oscillation can be started or stopped by using the low speed internal oscillation mode register LSRCM If it is specified that it cannot be stopped by software the clock source of WDT is fixed to the low speed internal oscillation clock fRL The low speed internal oscillator is independ...

Page 80: ...xed to fRL LSRSTOP 1 VDD 2 1 V 0 1 V Reset signal Power application Reset by power on clear Low speed internal oscillator can be stopped Low speed internal oscillator cannot be stopped Low speed internal oscillator stops Select by option byte if low speed internal oscillator can be stopped or not Note The clock source of the watchdog timer WDT is selected from fX or fRL or it may be stopped For de...

Page 81: ...th or more of a signal input externally Valid level pulse width 2 fXP or more 3 Pulse width measurement 16 bit timer event counter 00 can measure the pulse width of an externally input signal Valid level pulse width 2 fXP or more 4 Square wave output 16 bit timer event counter 00 can output a square wave with any selected frequency Cycle 2 to 65536 2 count clock cycle 5 PPG output 16 bit timer eve...

Page 82: ...ister 2 P2 Port mode control register 2 PMC2 Figures 6 1 shows a block diagram of these counters Figure 6 1 Block Diagram of 16 Bit Timer Event Counter 00 Internal bus Capture compare control register 00 CRC00 TI010 TO00 ANI1 INTP0 P21 fXP fXP 22 fXP 28 fX TI000 ANI0 TOH1 P20 Prescaler mode register 00 PRM00 2 PRM001 PRM000 CRC002 16 bit timer capture compare register 010 CR010 Match Match 16 bit ...

Page 83: ...se output mode Cautions 1 Even if TM00 is read the value is not captured by CR010 2 When TM00 is read count misses do not occur since the input of the count clock is temporarily stopped and then resumed after the read 2 16 bit timer capture compare register 000 CR000 CR000 is a 16 bit register which has the functions of both a capture register and a compare register Whether it is used as a capture...

Page 84: ...ion cannot be performed when this register is used as an external event counter However in the free running mode and in the clear start mode using the valid edge of TI000 if CR000 is set to 0000H an interrupt request INTTM000 is generated when CR000 changes from 0000H to 0001H following overflow FFFFH 2 If the new value of CR000 is less than the value of 16 bit timer counter 0 TM00 TM00 continues ...

Page 85: ... Valid Edge ES010 ES000 Falling edge Falling edge 0 0 Rising edge Rising edge 0 1 Both rising and falling edges Both rising and falling edges 1 1 Remarks 1 Setting ES010 ES000 1 0 is prohibited 2 ES010 ES000 Bits 5 and 4 of prescaler mode register 00 PRM00 CRC002 Bit 2 of capture compare control register 00 CRC00 Cautions 1 In the free running mode and in the clear start mode using the valid edge ...

Page 86: ...are control register 00 CRC00 16 bit timer output control register 00 TOC00 Prescaler mode register 00 PRM00 Port mode register 2 PM2 Port register 2 P2 Port mode control register 2 PMC2 1 16 bit timer mode control register 00 TMC00 This register sets the 16 bit timer operating mode the 16 bit timer counter 00 TM00 clear mode and output timing and detects an overflow TMC00 is set by a 1 bit or 8 b...

Page 87: ... of CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H the OVF00 flag is set to 1 6 Even if the OVF00 flag is cleared before the next count clock is counted before TM00 becomes 0001H after the occurrence of a TM00 overflow the OVF00 flag is re set newly and clear is disabled 7 The capture operation is performed at the fall of the count clock An interrupt request input INTTM0n0 however o...

Page 88: ... register 1 Operate as capture register CRC001 CR000 capture trigger selection 0 Capture on valid edge of TI010 pin 1 Capture on valid edge of TI000 pin by reverse phase Note CRC000 CR000 operating mode selection 0 Operate as compare register 1 Operate as capture register Note When the CRC001 bit value is 1 capture is not performed if both the rising and falling edges have been selected as the val...

Page 89: ...C004 Timer output F F control using match of CR010 and TM00 0 Disables inversion operation 1 Enables inversion operation LVS00 LVR00 Timer output F F status setting 0 0 No change 0 1 Timer output F F reset 0 1 0 Timer output F F set 1 1 1 Setting prohibited TOC001 Timer output F F control using match of CR000 and TM00 0 Disables inversion operation 1 Enables inversion operation TOE00 Timer output ...

Page 90: ... 3 2 1 0 PRM00 ES110 ES100 ES010 ES000 0 0 PRM001 PRM000 ES110 ES100 TI010 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES010 ES000 TI000 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges PRM001 PRM000 Count clock fsam selection 0 0 fXP 10 MHz 0 1 fXP 2 2 2 5 MHz 1...

Page 91: ... when a TI000 valid edge is used as the count clock and when it is used as a capture trigger In the former case the count clock is fXP and in the latter case the count clock is selected by prescaler mode register 00 PRM00 The capture operation is not performed until the valid edge is sampled and the valid level is detected twice thus eliminating noise with a short pulse width 5 When using P21 as t...

Page 92: ... CR000 register 3 Set the count clock by using the PRM00 register 4 Set the TMC00 register to start the operation see Figure 6 11 for the set value Caution Changing the CR000 setting during TM00 operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 17 Changing compare register during timer operation Remark For how to enable the INTTM...

Page 93: ...tting 10 is prohibited c 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 1 TMC002 1 TMC001 0 1 OVF00 0 TMC00 Clears and starts on match between TM00 and CR000 Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with the interval timer See the description of the respective control registers for details Figure 6 12 Interval Timer Configuration Diagram 16 bi...

Page 94: ... value M after the CR000 change is smaller than that N before the change it is necessary to restart the timer after changing CR000 Figure 6 14 Timing After Change of Compare Register During Timer Count Operation N M N M CR000 N M Count clock TM00 count value X 1 X FFFFH 0000H 0001H 0002H Remark N X M 6 4 2 External event counter operation Setting The basic operation setting procedure is as follows...

Page 95: ...rried out only when the valid edge of the TI000 pin is detected twice after sampling with the internal clock fXP noise with a short pulse width can be removed Figure 6 15 Control Register Settings in External Event Counter Mode with Rising Edge Specified a Capture compare control register 00 CRC00 7 0 6 0 5 0 4 0 3 0 CRC002 0 1 CRC001 0 1 CRC000 0 CRC00 CR000 used as compare register b Prescaler m...

Page 96: ...ternal Event Counter Operation Timing with Rising Edge Specified 1 INTTM000 generation timing immediately after operation starts Counting is started after a valid edge is detected twice CR000 INTTM000 0000H 0001H 0002H 0003H N 2 N 1 N 0000H 0001H 0002H N 1 2 3 Count starts TI000 pin input TM00 count value Timer operation starts 2 INTTM000 generation timing after INTTM000 has been generated twice C...

Page 97: ...er see Figures 6 19 6 22 6 24 and 6 26 for the set value 2 Set the count clock by using the PRM00 register 3 Set the TMC00 register to start the operation see Figures 6 19 6 22 6 24 and 6 26 for the set value Caution To use two capture registers set the TI000 and TI010 pins Remarks 1 For the setting of the TI000 or TI010 pin see 6 3 5 Port mode register 2 PM2 and port mode control register 2 PMC2 ...

Page 98: ...000 0 1 PRM00 Selects count clock setting 11 is prohibited Specifies both edges for pulse width detection Setting invalid setting 10 is prohibited c 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 0 TMC002 1 TMC001 0 1 OVF00 0 TMC00 Free running mode Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement See the description of th...

Page 99: ... TI000 and TI010 pins by using bits 4 and 5 ES000 and ES010 and bits 6 and 7 ES100 and ES110 of PRM00 When the valid edge specified by bits 4 and 5 ES000 and ES010 of prescaler mode register 00 PRM00 is input to the TI000 pin the value of TM00 is taken into 16 bit timer capture compare register 010 CR010 and an interrupt request signal INTTM010 is set Also when the valid edge specified by bits 6 a...

Page 100: ...s capture register b Prescaler mode register 00 PRM00 ES110 1 ES100 1 ES010 1 ES000 1 3 0 2 0 PRM001 0 1 PRM000 0 1 PRM00 Selects count clock setting 11 is prohibited Specifies both edges for pulse width detection Specifies both edges for pulse width detection c 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 0 TMC002 1 TMC001 0 1 OVF00 0 TMC00 Free running mode Remark 0 1 Setti...

Page 101: ......

Page 102: ...ising edge for pulse width detection Setting invalid setting 10 is prohibited c 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 0 TMC002 1 TMC001 0 1 OVF00 0 TMC00 Free running mode Note If the valid edge of TI000 is specified to be both the rising and falling edges 16 bit timer capture compare register 000 CR000 cannot perform the capture operation When the CRC001 bit value is ...

Page 103: ...re compare register 010 CR010 and then the pulse width of the signal input to the TI000 pin is measured by clearing TM00 and restarting the count The edge specification can be selected from two types rising or falling edges by bits 4 and 5 ES000 and ES010 of prescaler mode register 00 PRM00 Sampling is performed at the interval selected by prescaler mode register 00 PRM00 and a capture operation i...

Page 104: ...tting 10 is prohibited c 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 1 TMC002 0 TMC001 0 1 OVF00 0 TMC00 Clears and starts at valid edge of TI000 pin Note If the valid edge of TI000 is specified to be both the rising and falling edges 16 bit timer capture compare register 000 CR000 cannot perform the capture operation Figure 6 27 Timing of Pulse Width Measurement Operation b...

Page 105: ...ister 2 PM2 and port mode control register 2 PMC2 2 For how to enable the INTTM000 interrupt see CHAPTER 10 INTERRUPT FUNCTIONS A square wave with any selected frequency can be output at intervals determined by the count value preset to 16 bit timer capture compare register 000 CR000 The TO00 pin output status is reversed at intervals determined by the count value preset to CR000 1 by setting bit ...

Page 106: ... is prohibited Does not invert output on match between TM00 and CR010 Disables one shot pulse output d 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 1 TMC002 1 TMC001 0 OVF00 0 TMC00 Clears and starts on match between TM00 and CR000 Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with square wave output See the description of the respective control ...

Page 107: ......

Page 108: ...F F setting 11 is prohibited Inverts output on match between TM00 and CR010 Disables one shot pulse output c Prescaler mode register 00 PRM00 ES110 0 1 ES100 0 1 ES010 0 1 ES000 0 1 3 0 2 0 PRM001 0 1 PRM000 0 1 PRM00 Selects count clock Setting invalid setting 10 is prohibited Setting invalid setting 10 is prohibited d 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 1 TMC002 1 ...

Page 109: ...Clear circuit Noise eliminator fXP fXP fXP 22 fXP 28 16 bit timer capture compare register 010 CR010 TO00 TI010 ANI1 INTP0 P21 Selector Output controller TI000 ANI0 TOH1 P20 Figure 6 32 PPG Output Operation Timing t 0000H 0000H 0001H 0001H M 1 Count clock TM00 count value TO00 Pulse width M 1 t 1 cycle N 1 t N CR000 capture value CR010 capture value M M N 1 N N Clear Clear Remark 0000H M N FFFFH ...

Page 110: ... in Figure 6 33 and by setting bit 6 OSPT00 of the TOC00 register to 1 by software By setting the OSPT00 bit to 1 16 bit timer event counter 00 is cleared and started and its output becomes active at the count value N set in advance to 16 bit timer capture compare register 010 CR010 After that the output becomes inactive at the count value M set in advance to 16 bit timer capture compare register ...

Page 111: ...5 4 3 CRC00 CRC002 CRC001 CRC000 CR000 as compare register CR010 as compare register 0 0 1 0 c 16 bit timer output control register 00 TOC00 0 7 0 1 1 0 1 TOC00 LVR00 LVS00 TOC004 OSPE00 OSPT00 TOC001 TOE00 Enables TO00 output Inverts output upon match between TM00 and CR000 Specifies initial value of TO00 output F F setting 11 is prohibited Inverts output upon match between TM00 and CR010 Sets on...

Page 112: ...n Figure 6 35 and by using the valid edge of the TI000 pin as an external trigger The valid edge of the TI000 pin is specified by bits 4 and 5 ES000 ES010 of prescaler mode register 00 PRM00 The rising falling or both the rising and falling edges can be specified When the valid edge of the TI000 pin is detected the 16 bit timer event counter is cleared and started and the output becomes active at ...

Page 113: ... CRC00 0 0 0 0 0 7 6 5 4 3 CRC00 CRC002 CRC001 CRC000 CR000 used as compare register CR010 used as compare register 0 0 1 0 c 16 bit timer output control register 00 TOC00 0 7 0 1 1 0 1 TOC00 LVR00 TOC001 TOE00 OSPE00 OSPT00 TOC004 LVS00 Enables TO00 output Inverts output upon match between TM00 and CR000 Specifies initial value of TO00 output F F setting 11 is prohibited Inverts output upon match...

Page 114: ...fied 0000H N N N N N M M M M M N 1 N 2 M 1 M 2 M 2 M 1 0001H 0000H Count clock TM00 count value CR010 set value CR000 set value TI000 pin input INTTM010 INTTM000 TO00 pin output When TMC00 is set to 08H TM00 count starts t Caution 16 bit timer counter 00 starts operating as soon as a value other than 00 operation stop mode is set to the TMC002 and TMC003 bits Remark N M ...

Page 115: ...stopped and then resumed after the read 4 If the timer is stopped timer counts and timer interrupts do not occur even if a signal is input to the TI000 TI010 pins 3 Setting of 16 bit timer capture compare registers 000 010 CR000 CR010 1 Set 16 bit timer capture compare register 000 CR000 to other than 0000H in the clear start mode entered on match between TM00 and CR000 This means a 1 pulse count ...

Page 116: ... 8 Setting of prescaler mode register 00 PRM00 Always set data to PRM00 after stopping the timer operation 9 Valid edge setting Set the valid edge of the TI000 pin with bits 4 and 5 ES000 and ES010 of prescaler mode register 00 PRM00 after stopping the timer operation 10 One shot pulse output One shot pulse output normally operates only in the free running mode or in the clear start mode at the va...

Page 117: ...h between TM00 and CR000 clear start at the valid edge of the TI000 pin or free running mode is selected CR000 is set to FFFFH When TM00 is counted up from FFFFH to 0000H Figure 6 38 Operation Timing of OVF00 Flag Count clock CR000 TM00 OVF00 INTTM000 FFFFH FFFEH FFFFH 0000H 0001H 2 Even if the OVF00 flag is cleared before the next count clock is counted before TM00 becomes 0001H after the occurre...

Page 118: ...es of the TI000 pin 3 When the CRC001 bit value is 1 the TM00 count value is not captured in the CR000 register when a valid edge of the TI010 pin is detected but the input from the TI010 pin can be used as an external interrupt source because INTTM000 is generated at that timing 4 To ensure the reliability of the capture operation the capture trigger requires a pulse longer than two cycles of the...

Page 119: ...between TM00 and CR000 TOC001 1 6 Clear the interrupt request flag of INTTM000 TMIF000 0 7 Enable the INTTM000 interrupt TMMK000 0 Changing duty CR010 1 Disable the timer output inversion operation at the match between TM00 and CR010 TOC004 0 2 Disable the INTTM000 interrupt TMMK000 1 3 Rewrite CR010 4 Wait for 1 cycle of the TM00 count clock 5 Enable the timer output inversion operation at the ma...

Page 120: ...enabled Remark n 0 1 2 The sampling clock used to remove noise differs when a TI000 valid edge is used as the count clock and when it is used as a capture trigger In the former case the count clock is fXP and in the latter case the count clock is selected by prescaler mode register 00 PRM00 The capture operation is not performed until the valid edge is sampled and the valid level is detected twice...

Page 121: ... the AC characteristics refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS 2 When an external waveform is input to 16 bit timer event counter 00 it is sampled by the noise limiter circuit and thus an error occurs on the timing to become valid inside the device Count clock fsam TI000 Input pulse through noise limiter circuit Sampling time on filter Remark The count clock fsam can be selected using bits ...

Page 122: ... bit timer H1 consists of the following hardware Table 7 1 Configuration of 8 Bit Timer H1 Item Configuration Timer register 8 bit timer counter H1 Registers 8 bit timer H compare register 01 CMP01 8 bit timer H compare register 11 CMP11 Timer output TOH1 Control registers 8 bit timer H mode register 1 TMHMD1 Port mode register 2 PM2 Port register 2 P2 Port mode control register 2 PMC2 Figure 7 1 ...

Page 123: ...LEV1 TOEN1 8 bit timer H mode register 1 TMHMD1 8 bit timer H compare register 11 CMP11 Decoder TOH1 TI000 ANI1 P20 INTTMH1 Selector fXP fXP 22 fXP 24 fXP 26 fXP 212 fRL 27 Interrupt generator Output controller Level inversion 1 0 F F R 8 bit timer counter H1 PWM mode signal Timer H enable signal Clear 3 2 8 bit timer H compare register 01 CMP01 Output latch P20 PM20 ...

Page 124: ...it Timer H Compare Register 11 CMP11 Symbol CMP11 Address FF0FH After reset 00H R W 7 6 5 4 3 2 1 0 CMP11 can be rewritten during timer count operation If the CMP11 value is rewritten during timer operation the compare value after the rewrite takes effect at the timing at which the count value and the compare value before the rewrite match If the timing at which the count value and compare value m...

Page 125: ...rol 8 Bit Timer H1 8 bit timer H mode register 1 TMHMD1 Port mode register 2 PM2 Port register 2 P2 Port mode control register 2 PMC2 1 8 bit timer H mode register 1 TMHMD1 This register controls the mode of timer H This register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to 00H ...

Page 126: ...r mode PWM output mode Setting prohibited TMMD11 0 1 TMMD10 0 0 Timer operation mode Low level High level TOLEV1 0 1 Timer output level control in default mode Disable output Enable output TOEN1 0 1 Timer output control Other than above 7 6 5 4 3 2 1 0 Cautions 1 When TMHE1 1 setting the other bits of the TMHMD1 register is prohibited 2 In the PWM output mode be sure to set 8 bit timer H compare r...

Page 127: ...mat of Port Mode Control Register 2 PMC2 Address FF84H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20 PMC2n Specification of operation mode n 0 to 3 0 Port Alternate function except A D converter mode 1 A D converter mode 7 4 Operation of 8 Bit Timer H1 7 4 1 Operation as interval timer square wave output When 8 bit timer counter H1 and compare register 01 CMP01 ma...

Page 128: ...Timer output level inversion setting Interval timer mode setting Count clock fCNT selection Count operation stopped ii CMP01 register setting Compare value N 2 Count operation starts when TMHE1 1 3 When the values of 8 bit timer counter H1 and the CMP01 register match the INTTMH1 signal is generated and 8 bit timer counter H1 is cleared to 00H Interval time N 1 fCNT 4 Subsequently the INTTMH1 sign...

Page 129: ...n match interrupt occurrence 8 bit timer counter H1 clear 3 1 1 The count operation is enabled by setting the TMHE1 bit to 1 The count clock starts counting no more than 1 clock after the operation is enabled 2 When the values of 8 bit timer counter H1 and the CMP01 register match the value of 8 bit timer counter H1 is cleared the TOH1 output level is inverted and the INTTMH1 signal is output 3 Th...

Page 130: ...e Output Operation 2 2 b Operation when CMP01 FFH 00H Count clock Count start 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 01H FEH Clear Clear FFH 00H FEH FFH 00H FFH Interval time c Operation when CMP01 00H Count clock Count start 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 00H 00H Interval time ...

Page 131: ... an arbitrary duty and arbitrary cycle can be set is output 1 Set each register Figure 7 9 Register Setting in PWM Output Mode i Setting timer H mode register 1 TMHMD1 0 0 1 0 1 0 1 1 0 0 1 1 TMMD10 TOLEV1 TOEN1 CKS11 CKS12 TMHE1 TMHMD1 CKS10 TMMD11 Timer output enabled Timer output level inversion setting PWM output mode selection Count clock fCNT selection Count operation stopped ii Setting CMP0...

Page 132: ...put cycle and duty are as follows PWM pulse output cycle N 1 fCNT Duty Active width Total width of PWM M 1 N 1 Cautions 1 In PWM output mode the setting value for the CMP11 register can be changed during timer count operation However three operation clocks signal selected using the CKS12 to CKS10 bits of the TMHMD1 register or more are required to transfer the register value after rewriting the CM...

Page 133: ...y masking one count clock to count up At this time TOH1 output remains inactive when TOLEV1 0 2 When the values of 8 bit timer counter H1 and the CMP01 register match the TOH1 output level is inverted the value of 8 bit timer counter H1 is cleared and the INTTMH1 signal is output 3 When the values of 8 bit timer counter H1 and the CMP11 register match the level of the TOH1 output is returned At th...

Page 134: ...en CMP01 FFH CMP11 00H Count clock 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 TOLEV1 0 00H 01H FFH 00H 01H 02H FFH 00H FFH 00H 01H 02H CMP11 FFH 00H c Operation when CMP01 FFH CMP11 FEH Count clock 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 TOLEV1 0 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H CMP11 FFH FEH ...

Page 135: ... Manual U18172EJ2V0UD 135 Figure 7 10 Operation Timing in PWM Output Mode 3 4 d Operation when CMP01 01H CMP11 00H Count clock 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 TOLEV1 0 01H 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP11 00H ...

Page 136: ... timer counter H1 is cleared the TOH1 output becomes active and the INTTMH1 signal is output 4 If the CMP11 register value is changed the value is latched and not transferred to the register When the values of 8 bit timer counter H1 and the CMP11 register before the change match the value is transferred to the CMP11 register and the CMP11 register value is changed 2 However three count clocks or m...

Page 137: ...illation Clock Operation During System Clock Operation 2 11 fRL 4 27 ms 2 13 fX 819 2 µs 2 12 fRL 8 53 ms 2 14 fX 1 64 ms 2 13 fRL 17 07 ms 2 15 fX 3 28 ms 2 14 fRL 34 13 ms 2 16 fX 6 55 ms 2 15 fRL 68 27 ms 2 17 fX 13 11 ms 2 16 fRL 136 53 ms 2 18 fX 26 21 ms 2 17 fRL 273 07 ms 2 19 fX 52 43 ms 2 18 fRL 546 13 ms 2 20 fX 104 86 ms Remarks 1 fRL Low speed internal oscillation clock oscillation fre...

Page 138: ......

Page 139: ...f Watchdog Timer Clock input controller Output controller Internal reset signal WDCS2 Internal bus WDCS1 WDCS0 WDCS3 WDCS4 0 1 1 Selector 16 bit counter or 213 fX to 220 fX Watchdog timer enable register WDTE Watchdog timer mode register WDTM 3 2 Clear Option byte to set low speed internal oscillator cannot be stopped or low speed internal oscillator can be stopped by software fRL 22 fX 24 211 fRL...

Page 140: ...ion clock selection 0 0 Low speed internal oscillation clock fRL 0 1 System Clock fX 1 Watchdog timer operation stopped Overflow time setting WDCS2 Note 2 WDCS1 Note 2 WDCS0 Note 2 During low speed internal oscillation clock operation During system clock operation 0 0 0 2 11 fRL 4 27 ms 2 13 fX 819 2 µs 0 0 1 2 12 fRL 8 53 ms 2 14 fX 1 64 ms 0 1 0 2 13 fRL 17 07 ms 2 15 fX 3 28 ms 0 1 1 2 14 fRL 3...

Page 141: ...at enough overflow time is secured Example 1 byte writing 200 µs MIN 1 block deletion 10 ms MIN Remarks 1 fRL Low speed internal oscillation clock oscillation frequency 2 fX System clock oscillation frequency 3 Don t care 4 Figures in parentheses apply to operation at fRL 480 kHz MAX fX 10 MHz 2 Watchdog timer enable register WDTE Writing ACH to WDTE clears the watchdog timer counter and starts co...

Page 142: ...gister WDTM by an 8 bit memory manipulation instructionNotes 1 2 Cycle Set using bits 2 to 0 WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 The operation clock low speed internal oscillation clock cannot be changed If any value is written to bits 3 and 4 WDCS3 WDCS4 of WDTM it is ignored 2 As soon as WDTM is written th...

Page 143: ...d Is Selected by Option Byte Reset WDT clock fRL Overflow time 546 13 ms MAX STOP WDT count continues HALT WDT count continues STOP instruction HALT instruction WDT clock is fixed to fRL Select overflow time settable only once WDT clock fRL Overflow time 4 27 ms to 546 13 ms MAX WDT count continues Interrupt Interrupt WDTE ACH Clear WDT counter ...

Page 144: ...clock fX Watchdog timer operation stopped Cycle Set using bits 2 to 0 WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 As soon as WDTM is written the counter of the watchdog timer is cleared 2 Set bits 7 6 and 5 to 0 1 1 respectively Do not set the other values 3 At the first write If the watchdog timer is stopped by set...

Page 145: ...DT count continues STOP WDT count stops HALT WDT count stops STOP instruction HALT instruction Interrupt Interrupt WDTE ACH Clear WDT counter WDT operation stops WDCS4 1 WDT clock fX Overflow time 213 fX to 220 fX WDT count continues WDT clock fX Select overflow time settable only once WDT clock fRL WDT count stops WDTE ACH Clear WDT counter LSRSTOP 1 LSRSTOP 0 STOP WDT count stops HALT WDT count ...

Page 146: ...egister OSTS after operation stops in the case of crystal ceramic oscillation and then counting is started again using the operation clock before the operation was stopped At this time the counter is not cleared to 0 but holds its value Figure 8 6 Operation in STOP Mode WDT Operation Clock Clock to Peripheral Hardware 1 CPU clock Crystal ceramic oscillation clock Operation stopped Operating Oscill...

Page 147: ...on STOP Oscillation stopped Operation stoppedNote 2 CPU clock High speed internal oscillation clock or external clock input Operating Normal operation Watchdog timer Operation stopped Operating fRL fCPU CPU operation Normal operation STOP Oscillation stopped Operation stoppedNote Note The operation stop time is 17 µs MIN 34 µs TYP and 67 µs MAX 8 4 4 Watchdog timer operation in HALT mode when low ...

Page 148: ...ersion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI3 Each time an A D conversion operation ends an interrupt request INTAD is generated Figure 9 1 shows the timing of sampling and A D conversion and Table 9 1 shows the sampling time and A D conversion time Figure 9 1 Timing of A D Converter Sampling and A D Conversion ADCS Conversion time Conversion time Sampli...

Page 149: ...e When VDD 2 7 V fXP 8 MHz The sampling time is 11 0 µs or more and the A D conversion time is 14 0 µs or more and 100 µs or less Set FR2 FR1 and FR0 0 1 1 or 1 1 1 2 Set the sampling time as follows VDD 4 5 V 1 0 µs or more VDD 4 0 V 2 4 µs or more VDD 2 85 V 3 0 µs or more VDD 2 7 V 11 0 µs or more 3 Set the A D conversion time as follows VDD 4 5 V 3 0 µs or more and less than 100 µs VDD 4 0 V 4...

Page 150: ... input When using the A D converter stabilize VDD at the supply voltage used 2 7 to 5 5 V 9 2 Configuration of A D Converter The A D converter consists of the following hardware 1 ANI0 to ANI3 pins These are the analog input pins of the 4 channel A D converter They input analog signals to be converted into digital signals Pins other than the one selected as the analog input pin by the analog input...

Page 151: ... A D conversion is completed and the ADCRH register holds the result of A D conversion in its higher 8 bits 8 Controller When A D conversion has been completed INTAD is generated 9 VDD pin This is the positive power supply pin In the 78K0S KU1 VDD functions alternately as the A D converter reference voltage input When using the A D converter stabilize VDD at the supply voltage used 2 7 to 5 5 V 10...

Page 152: ...egister ADS 10 bit A D conversion result register ADCR 8 bit A D conversion result register ADCRH Port mode register 2 PM2 Port mode control register 2 PMC2 1 A D converter mode register ADM This register sets the conversion time for analog input to be A D converted and starts stops conversion ADM can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this re...

Page 153: ... µs 9 6 µs 14 4 µs 1 0 1 48 fXP 96 fXP 6 0 µs 12 0 µs 4 8 µs 9 6 µs 0 1 0 48 fXP 72 fXP 6 0 µs 9 0 µs 4 8 µs 7 2 µs 0 0 1 VDD 2 85 V 24 fXP 48 fXP 3 0 µs 6 0 µs Setting prohibited Note 5 2 4 µs Setting prohibited Note 5 4 8 µs 1 1 1 176 fXP 224 fXP 22 0 µs 28 0 µs 17 6 µs 22 4 µs 0 1 1 VDD 2 7 V 88 fXP 112 fXP 11 0 µs 14 0 µs Setting prohibited Note 5 8 8 µs Setting prohibited Note 5 11 2 µs ADCE ...

Page 154: ... and ADCE ADCS ADCE A D Conversion Operation 0 0 Stop status DC power consumption path does not exist 0 1 Conversion waiting mode only comparator consumes power 1 Conversion mode Figure 9 4 Timing Chart When Comparator Is Used ADCE Comparator ADCS Conversion operation Conversion operation Conversion stopped Conversion waiting Comparator operating Note Note The time from the rising of the ADCE bit ...

Page 155: ... Address FF81H After reset 00H R W Symbol Caution Be sure to clear bits 2 to 7 of ADS to 0 3 10 bit A D conversion result register ADCR This register is a 16 bit register that stores the A D conversion result The higher six bits are fixed to 0 Each time A D conversion ends the conversion result is loaded from the successive approximation register and is stored in ADCR in order starting from bit 1 ...

Page 156: ...23 may be 0 or 1 PM2 and PMC2 are set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets PM2 to 00H and clears PMC2 to FFH Figure 9 8 Format of Port Mode Register 2 PM2 Address FF22H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 1 1 PM23 PM22 PM21 PM20 PM2n Pmn pin I O mode selection n 0 to 3 0 Output mode output buffer on 1 Input mode output buffer off Figure 9 ...

Page 157: ...DD the MSB is reset to 0 9 Next bit 8 of SAR is automatically set to 1 and the operation proceeds to the next comparison The D A converter voltage tap is selected according to the preset value of bit 9 as described below Bit 9 1 3 4 VDD Bit 9 0 1 4 VDD The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows Analog input voltage Voltage tap Bit 8 1 Analog in...

Page 158: ...nversion operations are performed continuously until bit 7 ADCS of the A D converter mode register ADM is reset 0 by software If a write operation is performed to ADM or the analog input channel specification register ADS during an A D conversion operation the conversion operation is initialized and if the ADCS bit is set 1 conversion starts again from the beginning Reset signal generation makes t...

Page 159: ...e INT Function which returns integer part of value in parentheses VAIN Analog input voltage VDD VDD pin voltage ADCR 10 bit A D conversion result register ADCR value Figure 9 11 shows the relationship between the analog input voltage and the A D conversion result Figure 9 11 Relationship Between Analog Input Voltage and A D Conversion Result 1023 1022 1021 3 2 1 0 03FFH 03FEH 03FDH 0003H 0002H 000...

Page 160: ...d in the A D conversion result register ADCR ADCRH and an interrupt request signal INTAD is generated Once the A D conversion has started and when one A D conversion has been completed the next A D conversion operation is immediately started The A D conversion operations are repeated until new data is written to ADS If ADM or ADS is written during A D conversion the A D conversion operation under ...

Page 161: ...n data to the A D conversion result register ADCR ADCRH Change the channel 7 Change the channel using bits 1 and 0 ADS1 ADS0 of ADS to start A D conversion 8 An interrupt request signal INTAD is generated 9 Transfer the A D conversion data to the A D conversion result register ADCR ADCRH Complete A D conversion 10 Clear ADCS to 0 11 Clear ADCE to 0 Cautions 1 Make sure the period of 1 to 4 is 1 µs...

Page 162: ... overall error in the characteristics table 3 Quantization error When analog values are converted to digital values a 1 2LSB error naturally occurs In an A D converter an analog input voltage in a range of 1 2LSB is converted to the same digital code so a quantization error cannot be avoided Note that the quantization error is not included in the overall error zero scale error full scale error int...

Page 163: ...nt value and the ideal value Figure 9 15 Zero Scale Error Figure 9 16 Full Scale Error 111 011 010 001 Zero scale error Ideal line 000 0 1 2 3 VDD Digital output Lower 3 bits Analog input LSB 111 110 101 000 0 VDD 3 Full scale error Ideal line Analog input LSB Digital output Lower 3 bits VDD 2 VDD 1 VDD Figure 9 17 Integral Linearity Error Figure 9 18 Differential Linearity Error 0 VDD Digital out...

Page 164: ...erter mode register ADM write or analog input channel specification register ADS write upon the end of conversion ADM or ADS write has priority ADCR ADCRH write is not performed nor is the conversion end interrupt signal INTAD generated 4 Noise countermeasures To maintain the 10 bit resolution attention must be paid to noise input to the VDD pin and ANI0 to ANI3 pins 1 Connect a capacitor with a l...

Page 165: ...dance of the analog input source 1 kΩ or lower or attach a capacitor of around 0 01 µF to 0 1 µF to the ANI0 to ANI3 pins see Figure 9 19 When writing the flash memory on board supply a stabilized analog voltage to the ANI2 and ANI3 pins without attaching a capacitor Because the communication pulse may change and the communication may fail if a capacitor is attached to remove noise 7 Interrupt req...

Page 166: ... Using a timing other than the above may cause an incorrect conversion result to be read 10 The operating current at the conversion waiting mode The DC characteristic of the operating current at the STOP mode is not satisfied at the conversion waiting mode when A D converter mode register ADM is set up with bit 7 ADCS 0 and bit 0 ADCE 1 only comparator consumes power 11 Internal equivalent circuit...

Page 167: ...interrupt requests are generated at the same time processing takes place in the priority order of the vector interrupt servicing For details on the priority order see Table 10 1 There are five internal sources and two external sources of maskable interrupts Reset The CPU and SFR are returned to their initial states by the reset signal The causes for reset signal occurrences are shown in Table 10 1...

Page 168: ...er is specified 000EH 6 INTTM010 Match between TM00 and CR010 when compare register is specified TI000 pin valid edge detection when capture register is specified 0010H Maskable 7 INTAD End of A D conversion Internal 0012H A RESET Reset input POC Power on clear LVI Low voltage detection Note 4 Reset WDT WDT overflow 0000H Notes 1 Priority is the vector interrupt servicing priority order when sever...

Page 169: ...IF IE Vector table address generator Standby release signal Edge detector Interrupt request IF Interrupt request flag IE Interrupt enable flag MK Interrupt mask flag 10 3 Interrupt Function Control Registers The interrupt functions are controlled by the following four types of registers Interrupt request flag register 0 IF0 Interrupt mask flag register 0 MK0 External interrupt mode register 0 INTM...

Page 170: ...pt request is acknowledged or when a reset signal is input IF0 is set with a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears IF0 to 00H Figure 10 2 Format of Interrupt Request Flag Register 0 IF0 Address FFE0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0 ADIF TMIF010 TMIF000 TMIFH1 PIF1 PIF0 LVIIF 0 IF Interrupt request flag 0 No interrupt request signal has been is...

Page 171: ...ut level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore the interrupt mask flag should be set to 1 before using the output mode 3 External interrupt mode register 0 INTM0 This register is used to set the valid edge of INTP0 and INTP1 INTM0 is set with an 8 bit memory manipulation instruction Reset signal generation clears INTM0 to 00H Figur...

Page 172: ...e disable interrupt acknowledgment Used in the execution of ordinary instructions 10 4 Interrupt Servicing Operation 10 4 1 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0 If the interrupt enabled status is in effect when the IE flag is set to 1...

Page 173: ... request pending IF Interrupt request flag MK Interrupt mask flag IE Flag to control maskable interrupt request acknowledgment 1 enable 0 disable Figure 10 7 Interrupt Request Acknowledgment Timing Example of MOV A r Clock CPU Interrupt MOV A r Saving PSW and PC jump to interrupt servicing 8 clocks Interrupt servicing program If an interrupt request flag IF is set before an instruction clock n n 4...

Page 174: ...ample of the interrupt request acknowledgment timing for an interrupt request flag that is set at the second clock of NOP 2 clock instruction In this case the MOV A r instruction after the NOP instruction is executed and then the interrupt acknowledgment processing is performed Caution Interrupt requests will be held pending while the interrupt request flag register 0 IF0 or interrupt mask flag re...

Page 175: ...eased and the interrupt request acknowledgement enable state is set Caution Multiple interrupts can be acknowledged even for low priority interrupts Example 2 Multiple interrupts are not generated because interrupts are not enabled INTyy EI Main processing RETI INTyy servicing INTxx servicing IE 0 INTxx RETI INTyy is held pending IE 0 Because interrupts are not enabled in interrupt INTxx servicing...

Page 176: ......

Page 177: ... LSRSTOP setting is valid only when Can be stopped by software is set for the low speed internal oscillator by the option byte Remark LSRSTOP Bit 0 of the low speed internal oscillation mode register LSRCM The standby function is designed to reduce the operating current of the system The following two modes are available 1 HALT mode HALT instruction execution sets the HALT mode In the HALT mode th...

Page 178: ...7 µs MAX In either of these two modes all the contents of registers flags and data memory just before the standby mode is set are held The I O port output latches and output buffer statuses are also held Cautions 1 When shifting to the STOP mode be sure to stop the peripheral hardware operation before executing STOP instruction except the peripheral hardware that operates on the low speed internal...

Page 179: ...BYTE OSTS is set by using the 8 bit memory manipulation instruction Figure 11 1 Format of Oscillation Stabilization Time Select Register OSTS Address FFF4H After reset Undefined R W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 0 OSTS1 OSTS0 OSTS1 OSTS0 Selection of oscillation stabilization time 0 0 2 10 fX 102 4 µs 0 1 2 12 fX 409 6 µs 1 0 2 15 fX 3 27 ms 1 1 2 17 fX 13 1 ms Cautions 1 To set and then r...

Page 180: ...e interrupt request flag set and the interrupt mask flag clear the standby mode is immediately cleared if set Table 11 2 Operating Statuses in HALT Mode Low Speed Internal Oscillator can be stopped Note Setting of HALT Mode Item Low Speed Internal Oscillator cannot be stopped Note When Low Speed Internal Oscillation Continues When Low Speed Internal Oscillation Stops System clock Clock supply to C...

Page 181: ...ent is disabled the next address instruction is executed Figure 11 2 HALT Mode Release by Interrupt Request Generation HALT instruction Wait Wait Operating mode HALT mode Operating mode Oscillation System clock oscillation Status of CPU Standby release signal Interrupt request Remarks 1 The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledge...

Page 182: ...is stopped 277 µs MIN 544 µs TYP 1 075 ms MAX because the option byte is referenced 2 When CPU clock is crystal ceramic oscillation clock HALT instruction Reset signal System clock oscillation Operation mode HALT mode Reset period Operation stopsNote Oscillation stabilization waits Oscillates Oscillation stops Oscillates CPU status Oscillation stabilization time 210 fX to 217 fX Operation mode Not...

Page 183: ...Operating Statuses in STOP Mode Low Speed Internal Oscillator can be stopped Note Setting of STOP Mode Item Low Speed Internal Oscillator cannot be stopped Note When Low Speed Internal Oscillation Continues When Low Speed Internal Oscillation Stops System clock Oscillation stops CPU Operation stops Port latch Holds status before STOP mode was set 16 bit timer event counter 00 Operation stops Sets ...

Page 184: ...de is released STOP mode High speed internal oscillation clock or external clock input Operation stopsNote 2 If crystal ceramic oscillation clock is selected as system clock to be supplied System clock oscillation CPU clock STOP mode is released STOP mode HALT status oscillation stabilization time set by OSTS Crystal ceramic oscillation clock Operation stopsNote Note The operation stop time is 17 ...

Page 185: ...s high speed internal oscillation clock or external input clock Operation mode Operation mode Oscillation STOP instruction STOP mode Standby release signal System clock oscillation CPU status Oscillation Oscillation stops Operation stopsNote Interrupt request 2 If CPU clock is crystal ceramic oscillation clock Waiting for stabilization of oscillation Oscillation stabilization time set by OSTS HALT...

Page 186: ... MIN 544 µs TYP 1 075 ms MAX because the option byte is referenced 2 If CPU clock is crystal ceramic oscillation clock STOP instruction Reset signal System clock oscillation Operation mode STOP mode Reset period Operation stopsNote Operation mode Oscillation Oscillation stops Oscillation CPU status Oscillation stabilization time 210 fX to 217 fX Oscillation stabilization waits Note Operation is st...

Page 187: ... option byte after the option byte is referenced and the clock oscillation stabilization time elapses if crystal ceramic oscillation is selected A reset generated by the watchdog timer source is automatically released after the reset and the CPU starts program execution after referencing the option byte after the option byte is referenced and the clock oscillation stabilization time elapses if cry...

Page 188: ...egister RESF Internal bus Reset signal of WDT Reset signal of POC Reset signal of LVI Internal reset signal Reset signal to LVIM LVIS register Clear Set Clear Set Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit Remarks 1 LVIM Low voltage detect register 2 LVIS Low voltage detection level select register ...

Page 189: ... stops because option byte is referencedNote 100 ns TYP 100 ns TYP Note The operation stop time is 277 µs MIN 544 µs TYP and 1 075 ms MAX 2 With crystal ceramic oscillation clock Hi Z RESET Port pin Delay Normal operation in progress Reset period oscillation stops Oscillation stabilization time 210 fX to 217 fX Normal operation reset processing CPU clock Internal reset signal Crystal ceramic oscil...

Page 190: ...me is 277 µs MIN 544 µs TYP and 1 075 ms MAX Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer 2 With crystal ceramic oscillation clock Hi Z Port pin Normal operation in progress Reset period oscillation stops Oscillation stabilization time 210 fX to 217 fX Normal operation reset processing CPU clock Internal reset signal Crystal ceramic oscillation cl...

Page 191: ...ation stop time is 277 µs MIN 544 µs TYP and 1 075 ms MAX 2 With crystal ceramic oscillation clock Hi Z RESET Port pin Delay Normal operation in progress CPU clock Normal operation reset processing CPU clock Internal reset signal Crystal ceramic oscillation clock Delay Operation stops because option byte is referencedNote Reset period oscillation stops Stop status oscillation stops STOP instructio...

Page 192: ...LSRCM 00H Oscillation stabilization time select register OSTS Undefined Timer counter 00 TM00 0000H Capture compare registers 000 010 CR000 CR010 0000H Mode control register 00 TMC00 00H Prescaler mode register 00 PRM00 00H Capture compare control register 00 CRC00 00H 16 bit timer 00 Timer output control register 00 TOC00 00H Compare registers CMP01 CMP11 00H 8 bit timer H1 Mode register 1 TMHMD1...

Page 193: ...h protect command register PFCMD Undefined Flash status register PFS 00H Flash programming mode control register FLPMC Undefined Flash programming command register FLCMD 00H Flash address pointer L FLAPL Flash address pointer H FLAPH Undefined Flash address pointer H compare register FLAPHC 00H Flash address pointer L compare register FLAPLC 00H Flash memory Flash write buffer register FLW 00H Not...

Page 194: ...4 3 2 1 0 RESF 0 0 0 WDTRF 0 0 0 LVIRF WDTRF Internal reset request by watchdog timer WDT 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated LVIRF Internal reset request by low voltage detector LVI 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated Note The value after reset varies depending on the rese...

Page 195: ...ignal is generated in the POC circuit the reset control flag register RESF is cleared to 00H 2 Because the detection voltage VPOC of the POC circuit is in a range of 2 1 V 0 1 V use a voltage in the range of 2 2 to 5 5 V Remark This product incorporates multiple hardware functions that generate an internal reset signal A flag that indicates the reset cause is located in the reset control flag regi...

Page 196: ... source Internal reset signal VDD VDD 13 3 Operation of Power on Clear Circuit In the power on clear circuit the supply voltage VDD and detection voltage VPOC 2 1 V 0 1 V are compared and an internal reset signal is generated when VDD VPOC and an internal reset is released when VDD VPOC Figure 13 2 Timing of Internal Reset Signal Generation in Power on Clear Circuit Time Supply voltage VDD POC det...

Page 197: ...imer and then initialize the ports Figure 13 3 Example of Software Processing After Release of Reset 1 2 If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage Check reset source Note 2 Initialization of ports Setting WDT Source fRL 2 1 MHz MAX 212 51 ms when the compare value is 25 Timer starts TMHE1 1 Note 1 Setting 8 bit timer H1 50 ms is measured Specify the divisi...

Page 198: ... Example of Software Processing After Release of Reset 2 2 Checking reset cause Yes No Check reset source Power on clear external reset generated Reset processing by watchdog timer Reset processing by low voltage detector No WDTRF of RESF register 1 LVIRF of RESF register 1 Yes ...

Page 199: ...re Operable in STOP mode When the low voltage detector is used to reset bit 0 LVIRF of the reset control flag register RESF is set to 1 if reset occurs For details of RESF refer to CHAPTER 12 RESET FUNCTION 14 2 Configuration of Low Voltage Detector The block diagram of the low voltage detector is shown in Figure 14 1 Figure 14 1 Block Diagram of Low Voltage Detector LVION Reference voltage source...

Page 200: ...age detection operation mode selection 0 Generate interrupt signal when supply voltage VDD detection voltage VLVI 1 Generate internal reset signal when supply voltage VDD detection voltage VLVI LVIF Note 4 Low voltage detection flag 0 Supply voltage VDD detection voltage VLVI or when operation is disabled 1 Supply voltage VDD detection voltage VLVI Notes 1 For a reset by LVI the value of LVIM is n...

Page 201: ...S1 LVIS0 LVIS3 LVIS2 LVIS1 LVIS0 Detection level 0 0 0 0 VLVI0 4 3 V 0 2 V 0 0 0 1 VLVI1 4 1 V 0 2 V 0 0 1 0 VLVI2 3 9 V 0 2 V 0 0 1 1 VLVI3 3 7 V 0 2 V 0 1 0 0 VLVI4 3 5 V 0 2 V 0 1 0 1 VLVI5 3 3 V 0 15 V 0 1 1 0 VLVI6 3 1 V 0 15 V 0 1 1 1 VLVI7 2 85 V 0 15 V 1 0 0 0 VLVI8 2 6 V 0 1 V 1 0 0 1 VLVI9 2 35 V 0 1 V Other than above Setting prohibited Note For a reset by LVI the value of LVIS is not i...

Page 202: ...VION of LVIM to 1 enables LVI operation 4 Use software to instigate a wait of at least 0 2 ms 5 Wait until supply voltage VDD detection voltage VLVI at bit 0 LVIF of LVIM is confirmed 6 Set bit 1 LVIMD of LVIM to 1 generates internal reset signal when supply voltage VDD detection voltage VLVI Figure 14 4 shows the timing of generating the internal reset signal of the low voltage detector Numbers 1...

Page 203: ... set by software LVION flag set by software LVIMD flag set by software Cleared by software Not cleared Not cleared Not cleared Not cleared Cleared by software Time Clear Clear Clear 4 0 2 ms or longer Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The LVIF flag may be set 1 3 LVIRF is bit 0 of the reset control flag register RESF For details of RESF refer to CHAPTER 12 RESET FUNCT...

Page 204: ...y voltage VDD detection voltage VLVI at bit 0 LVIF of LVIM is confirmed 6 Clear the interrupt request flag of LVI LVIIF to 0 7 Release the interrupt mask flag of LVI LVIMK 8 Execute the EI instruction when vector interrupts are used Figure 14 5 shows the timing of generating the interrupt signal of the low voltage detector Numbers 1 to 7 in this figure correspond to 1 to 7 above When stopping oper...

Page 205: ...VIIF flag Internal reset signal LVIMK flag set by software LVION flag set by software Time 6 Cleared by software 7 Cleared by software 4 0 2 ms or longer Note 2 Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 An interrupt request signal INTLVI may be generated and the LVIF and LVIIF flags may be set to 1 Remark 1 to 7 in Figure 14 5 above correspond to 1 to 7 in the description of ...

Page 206: ...n used as reset After releasing the reset signal wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer and then initialize the ports see Figure 14 6 2 When used as interrupt a Perform the processingNote for low voltage detection Check that supply voltage VDD detection voltage VLVI in the servicing routine of the LVI interrupt by using bit 0 ...

Page 207: ...tion flag Clear timaer counter and timer starts LVI reset Check reset source Note Initialization of ports Setting WDT Reset Initialization processing 1 Setting 8 bit timer H1 50 ms is measured Source fRL 2 1 MHz MAX 212 51 ms when the compare value is 25 Timer starts TMHE1 1 fXP High speed internal oscillation clock 8 4 MHz MAX 22 default value Clears WDT 50 ms has passed TMIFH1 1 Initialization p...

Page 208: ...Example of Software Processing After Release of Reset 2 2 Checking reset source Yes No Yes No Check reset source Power on clear external reset generated Reset processing by watchdog timer Reset processing by low voltage detector WDTRF of RESF register 1 LVIRF of RESF register 1 ...

Page 209: ... source High speed internal oscillation clock Crystal ceramic oscillation clock External clock input 2 Low speed internal oscillation clock oscillation Cannot be stopped Can be stopped by software 3 Control of RESET pin Used as RESET pin RESET pin is used as an input port pin P34 refer to 15 3 Caution When the RESET Pin Is Used as an Input Only Port Pin P34 4 Oscillation stabilization time on powe...

Page 210: ...f a low level is input to the RESET pin before the option byte is referenced then the reset state is not released Also when setting 0 to RMCE connect the pull up resistor OSCSEL1 OSCSEL0 Selection of system clock source 0 0 Crystal ceramic oscillation clock 0 1 External clock input 1 High speed internal oscillation clock Caution Because the X1 and X2 pins are also used as the P23 ANI3 and P22 ANI2...

Page 211: ...to the 8 bit timer H1 even in the STOP mode Remarks 1 fX 10 MHz 2 For the oscillation stabilization time of the resonator refer to the characteristics of the resonator to be used 3 An example of software coding for setting the option bytes is shown below OPB CSEG AT 0080H DB 10010001B Set to option byte Low speed internal oscillator cannot be stopped The system clock is a crystal or ceramic resona...

Page 212: ...tes Write unit 1 block at onboard offboard programming time 1 byte at self programming time Rewriting method Rewriting by communication with dedicated flash memory programmer on board off board programming Rewriting flash memory by user program self programming Supports rewriting of the flash memory at onboard offboard programming time through security functions Supports security functions in bloc...

Page 213: ...ed into 4 8 16 blocks and can be programmed erased in block units All the blocks can also be erased at once by using a dedicated flash memory programmer Figure 16 1 Flash Memory Mapping Special function resister 256 byte Internal high speed RAM 128 byte Flash memory 1 2 4 KB FFFFH FF00H FEFFH 0000H Use prohibited FE80H FE7FH 1 KB ...

Page 214: ...rd and Off Board Flash Memory Programming 16 8 Flash Memory Programming by Self Programming 16 4 Writing with Flash Memory Programmer The following two types of dedicated flash memory programmers can be used for writing data to the internal flash memory of the 78K0S KU1 FlashPro4 PG FP4 FL PR4 FlashPro5 PG FP5 FL PR5 Data can be written to the flash memory on board or off board by using a dedicate...

Page 215: ...n using FlashPro5 and QB MINI2 the signals do not have to be connected A host machine that controls the dedicated flash memory programmer is necessary When using the PG FP4 FL PR4 PG FP5 or FL PR5 data can be written with just the dedicated flash memory programmer after downloading the program from the host machine UART is used for manipulation such as writing and erasing when interfacing between ...

Page 216: ...ANI2 6 RESET Output Reset signal RESET P34 7 VDD VDD voltage generation voltage monitor VDD 4 GND Ground VSS 3 Notes 1 In the 78K0S KU1 the CLK and FLMD0 signals are connected to the X1 pin and the SI RxD and SO TxD signals to the X2 signal therefore these signals need to be directly connected 2 When using FlashPro5 and QB MINI2 the signals do not have to be connected Figure 16 3 Wiring diagram wi...

Page 217: ...anged Therefore there is a possibility that cannot communicate depending on capacitor capacitance When perform flash memory programming isolate connection with a condenser Perform the following processing 1 and 2 when on board programming is performed with the resonator mounted when it is difficult to isolate the resonator while a crystal or ceramic resonator is selected as the system clock 1 Moun...

Page 218: ...environment these values may change so set them after having performed sufficient evaluations 16 6 2 RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board signal collision takes place To prevent this collision isolate the connection with the reset signal generator If the reset signal is inpu...

Page 219: ...he reset signal generator 78K0S KU1 16 6 3 Port pins When the flash memory programming mode is set all the pins not used for flash memory programming enter the same status as that immediately after reset If external devices connected to the ports do not recognize the port status immediately after reset the port pin must be connected to VDD or VSS via a resistor The state of the pins in the self pr...

Page 220: ...xxx Axxxx XXX YYY XXXXX XXXXXX XXXX XXXX YYYY STATVE FlashPro4 Dedicated flash memory programmer FlashPro5 QB MINI2 Communication commands are listed in the table below All these communication commands are issued from the programmer and the 78K0S KU1 perform processing corresponding to the respective communication commands Table 16 5 Communication Commands Classification Communication Command Name...

Page 221: ...he batch erase chip erase command Write is prohibited Execution of the write and block erase commands for entire blocks in the flash memory is prohibited This prohibition setting can be cancelled using the batch erase chip erase command Remark The security setting is valid when the programming mode is set next time The batch erase chip erase block erase and write commands are enabled by the defaul...

Page 222: ...4 2 To use the internal flash memory of the 78K0S KU1 as the external EEPROM for storing data refer to 78K0S Kx1 EEPROM Emulation Application Note U17379E 16 8 1 Outline of self programming To execute self programming shift the mode from the normal operation of the user program normal mode to the self programming mode Write erase processing for the flash memory which has been set to the register i...

Page 223: ...cuit Erase circuit WEPRERR VCERR FPRERR HALT release signal FLCMD2 FLCMD1 FLCMD0 Internal bus Flash programming command register FLCMD Increment circuit Flash memory Protect byte PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 5 Flash address pointer H FLAPH Flash address pointer L FLAPL Flash address pointer H compare register FLAPHC Match Match Flash address pointer L compare register FLAPLC Flash write...

Page 224: ... ms Internal verify 2 This command is used to check if data has been correctly written to the flash memory It is used to check whether data has been written in the same block Internal verify for 1 byte 27 µs Block erasure Note This command is used to erase a specified block Specify the block number before execution 8 5 ms Block blank check This command is used to check if data in a specified block...

Page 225: ...it memory manipulation instruction The state of the pins in self programming mode is the same as that in HALT mode Since the security function set via on board off board programming is disabled in self programming mode the self programming command can be executed regardless of the security function setting To disable write or erase processing during self programming set the protect byte Be sure to...

Page 226: ...t byte is read to these bits Notes 1 Bit 0 FLSPM is cleared to 0 when reset is released The set value of the protect byte is read to bits 2 to 6 PRSELF0 to PRSELF4 after reset is released 2 Bits 2 to 6 PRSELF0 to PRSELF4 are read only Cautions 1 Cautions in the case of setting the self programming mode refer to 16 8 2 Cautions on self programming function 2 Set the CPU clock so that it is 1 MHz or...

Page 227: ... of the register so that the register cannot be written illegally Occurrence of an illegal store operation can be checked by bit 0 FPRERR of the flash status register PFS Check FPRERR using a 1 bit memory manipulation instruction A5H must be written to PFCMD each time the value of FLPMC is changed PFCMD can be set by an 8 bit memory manipulation instruction Reset signal generation makes PFCMD unde...

Page 228: ...2 is written by the first store instruction after 3 Remark The numbers in angle brackets above correspond to the those in 2 Flash protect command register PFCMD Reset conditions If 0 is written to the FPRERR flag If the reset signal is generation 2 Operating conditions of VCERR flag Setting conditions Erasure verification error Internal writing verification error If VCERR is set it means that the ...

Page 229: ...Internal verify 2 This command is used to check if data has been correctly written to the flash memory It is used to check whether data has been written in the same block If an error occurs bit 1 VCERR or bit 2 WEPRERR of the flash status register PFS is set to 1 0 1 1 Block erase This command is used to erase specified block It is used both in the on board mode and self programming mode 1 0 0 Blo...

Page 230: ...ice may malfunction 6 Flash address pointer H compare register and flash address pointer L compare register FLAPHC and FLAPLC These registers are used to specify the address range in which the internal sequencer operates when the flash memory is verified in the self programming mode Set FLAPHC to the same value as that of FLAPH Set the last address of the range in which verification is to be execu...

Page 231: ... area is invalid the data written to the protected area is guaranteed Figure 16 17 Format of Protect Byte 1 2 Address 0081H 7 6 5 4 3 2 1 0 1 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 1 1 µ PD78F9200 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 Status 0 1 1 1 0 Blocks 3 to 0 are protected 0 1 1 1 1 Blocks 1 and 0 are protected Blocks 2 and 3 can be written or erased 1 1 1 1 1 All blocks can be written or...

Page 232: ... to self programming mode The operating mode must be shifted from normal mode to self programming mode before performing self programming An example of shifting to self programming mode is explained below 1 Disable interrupts if the interrupt function is used by setting the interrupt mask flag registers MK0 to FFH and executing the DI instruction 2 Clear FLCMD FLCMD 00H 3 Clear the flash status re...

Page 233: ...PMC 01H set value FLPMC 0FEH inverted set value FLPMC 01H set value Set value is invalid Set value is valid 4 instruction 2 Clear FLCMD FLCMD 00H 6 Check execution result FPRERR flag Abnormal Normal 7 Termination NOP instruction HALT instruction 5 Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased or written Remark 1 to...

Page 234: ...onfigure settings so that the CPU clock 1 MHz MOV PFS 00H Clears flash status register MOV PFCMD 0A5H PFCMD register control MOV FLPMC 01H FLPMC register control sets value MOV FLPMC 0FEH FLPMC register control inverts set value MOV FLPMC 01H Sets self programming mode with FLPMC register control sets value NOP HALT BT PFS 0 ModeOnLoop Checks completion of write to specific registers Repeats the s...

Page 235: ...C writing in this step is invalid Write 0FFH inverted value of 00H to FLPMC writing in this step is invalid Write 00H to FLPMC writing in this step is valid 4 Check the execution result of the specific sequence using bit 0 FPRERR of PFS Abnormal 2 normal 5 5 Enable interrupt servicing by executing the EI instruction and changing MK0 to restore the original state 6 Mode shift is completed Note Afte...

Page 236: ... FLPMC 00H set value Set value is invalid Set value is valid 5 Enable interrupts by executing EI instruction and changing MK0 When interrupt function is used 3 1 Clear FLCMD FLCMD 00H Restore the CPU clock to its setting before the self programming Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased or written Remark 1 t...

Page 237: ...0A5H PFCMD register control MOV FLPMC 00H FLPMC register control sets value MOV FLPMC 0FFH FLPMC register control inverts set value MOV FLPMC 00H Sets normal mode via FLPMC register control sets value BT PFS 0 ModeOffLoop Checks completion of write to specific registers Repeats the same processing when an error occurs Restore the CPU clock to its setting before the self programming MOV MK0 INT_MK0...

Page 238: ...ter FLAPHC 5 Set the flash address pointer L compare register FLAPLC to 00H 6 Clear the flash status register PFS 7 Write ACH to the watchdog timer enable register WDTE clear and restart the watchdog timer counter Note 8 Execute the HALT instruction then start self programming Execute an instruction immediately after the HALT instruction if self programming has been executed 9 Check if a self prog...

Page 239: ...CERR and WEPRERR flags 8 Execute HALT instruction Normal 6 Clear PFS 1 Set erase command FLCMD 03H 2 Set no of block to be erased to FLAPH Block erasure 4 Set the same value as that of FLAPH to FLAPHC 10 Abnormal termination Abnormal 3 Set FLAPL to 00H 5 Set FLAPLC to 00H Note This setting is not required when the watchdog timer is not used Remark 1 to 11 in Figure 16 20 correspond to 1 to 11 in 1...

Page 240: ...s number of block to be erased block 7 is specified here MOV FLAPL 00H Fixes FLAPL to 00H MOV FLAPHC 07H Sets erase block compare number same value as that of FLAPH MOV FLAPLC 00H Fixes FLAPLC to 00H MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS MOV CmdStatus A Execution result is stored in variable CmdStatus 0 normal terminat...

Page 241: ...ess pointer H compare register FLAPHC 5 Set the flash address pointer L compare register FLAPLC to FFH 6 Clear the flash status register PFS 7 Write ACH to the watchdog timer enable register WDTE clear and restart the watchdog timer counter Note 8 Execute the HALT instruction then start self programming Execute an instruction immediately after the HALT instruction if self programming has been exec...

Page 242: ...d WEPRERR flags 8 Execute HALT instruction Normal Abnormal 6 Clear PFS 1 Set block blank check command FLCMD 04H 2 Set no of block for blank check to FLAPH Block blank check 10 Abnormal termination 5 Set FLAPLC to 00H 4 Set the same value as that of FLAPH to FLAPHC 3 Set FLAPL to 00H Note This setting is not required when the watchdog timer is not used Remark 1 to 11 in Figure 16 21 correspond to ...

Page 243: ... Sets number of block for blank check block 7 is specified here MOV FLAPL 00H Fixes FLAPL to 00H MOV FLAPHC 07H Sets blank check block compare number same value as that of FLAPH MOV FLAPLC 0FFH Fixes FLAPLC to FFH MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS MOV CmdStatus A Execution result is stored in variable CmdStatus 0 n...

Page 244: ...ite buffer register FLW 5 Clear the flash status register PFS 6 Write ACH to the watchdog timer enable register WDTE clear and restart the watchdog timer counter Note 7 Execute the HALT instruction then start self programming Execute an instruction immediately after the HALT instruction if self programming has been executed 8 Check if a self programming error has occurred using bit 1 VCERR and bit...

Page 245: ...ERR and WEPRERR flags 7 Execute HALT instruction Normal Abnormal 5 Clear PFS 1 Set byte write command FLCMD 05H Byte write 9 Abnormal termination 4 Set data to be written to FLW 2 Set no of block to be written to FLAPH 3 Set address at which data is to be written to FLAPL Note This setting is not required when the watchdog timer is not used Remark 1 to 10 in Figure 16 22 correspond to 1 to 10 in 1...

Page 246: ...ta is to be written with FLAPH block 7 is specified here MOV FLAPL 20H Sets address to which data is to be written with FLAPL address 20H is specified here MOV FLW 10H Sets data to be written 10H is specified here MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS MOV CmdStatus A Execution result is stored in variable CmdStatus 0 n...

Page 247: ... 1 VCERR and bit 2 WEPRERR of PFS Abnormal 10 Normal 11 10 Internal verify processing is abnormally terminated 11 Internal verify processing is normally terminated Internal verify 2 1 Set 02H internal verify 2 to the flash program command register FLCMD 2 Set the number of block for which internal verify is performed to flash address pointer H FLAPH 3 Sets flash address pointer L FLAPL to the star...

Page 248: ...gs 8 Execute HALT instruction Normal Abnormal 6 Clear PFS 1 Set internal verify 1 command FLCMD 01H Internal verify 1 10 Abnormal termination 2 Set No of block for internal verify to FLAPH 4 Set the same value as that of FLAPH to FLAPHC 5 Sets FLAPLC to FFH 3 Sets FLAPL to 00H Note This setting is not required when the watchdog timer is not used Remark 1 to 11 in Figure 16 23 correspond to Interna...

Page 249: ...T instruction Normal Abnormal 6 Clear PFS 1 Set internal verify 2 command FLCMD 02H Internal verify 2 10 Abnormal termination 2 Set No of block for internal verify to FLAPH 4 Set the same value as that of FLAPH to FLAPHC 5 Sets FLAPLC to the end address 3 Sets FLAPL to the start address Note This setting is not required when the watchdog timer is not used Remark 1 to 11 in Figure 16 24 correspond ...

Page 250: ...tatus A Execution result is stored in variable CmdStatus 0 normal termination other than 0 abnormal termination END Internal verify 2 START FlashVerify MOV FLCMD 02H Sets flash control command internal verify 2 MOV FLAPH 07H Set the number of block for which internal verify is performed to FLAPH Example Block 7 is specified here MOV FLAPL 00H Sets FLAPL to the start address for verify Example Addr...

Page 251: ...ted from self programming mode to normal mode 1 to 6 in 16 8 5 Figure 16 25 Example of Operation When Command Execution Time Should Be Minimized from Erasure to Blank Check 4 Shift to normal mode Abnormal 1 Shift to self programming mode Erasure to blank check Abnormal terminationNote 2 Execute block erase 3 Execute block blank check 2 Check execution result VCERR and WEPRERR flags 3 Check executi...

Page 252: ... Checks completion of write to specific registers Repeats the same processing when an error occurs FlashBlockErase MOV FLCMD 03H Sets flash control command block erase MOV FLAPH 07H Sets number of block to be erased block 7 is specified here MOV FLAPL 00H Fixes FLAPL to 00H MOV FLAPHC 07H Sets erase block compare number same value as that of FLAPH MOV FLAPLC 00H Fixes FLAPLC to 00H MOV WDTE 0ACH C...

Page 253: ... register control sets value MOV FLPMC 0FFH FLPMC register control inverts set value MOV FLPMC 00H Sets normal mode via FLPMC register control sets value BT PFS 0 ModeOffLoop Checks completion of write to specific registers Repeats the same processing when an error occurs After the specific sequence is correctly executed restore the CPU clock to its setting before the self programming MOV MK0 INT_...

Page 254: ...mand Execution Time Should Be Minimized from Write to Internal Verify 6 Shift to normal mode Abnormal 1 Shift to self programming mode Write to internal verify 3 Execute byte write command 5 Execute internal verify command 3 Check execution result VCERR and WEPRERR flags 5 Check execution result VCERR and WEPRERR flags Normal termination Normal Abnormal Normal Figure 16 22 1 to 10 Figure 16 23 1 t...

Page 255: ... Checks completion of write to specific registers Repeats the same processing when an error occurs FlashWrite MOVW HL DataAdrTop Sets address at which data to be written is located MOVW DE WriteAdr Sets address at which data is to be written FlashWriteLoop MOV FLCMD 05H Sets flash control command byte write MOV A D MOV FLAPH A Sets address at which data is to be written MOV A E MOV FLAPL A Sets ad...

Page 256: ...ination processing when an error occurs MOV FLCMD 00H Clears FLCMD register ModeOffLoop MOV PFS 00H Clears flash status register MOV PFCMD 0A5H PFCMD register control MOV FLPMC 00H FLPMC register control sets value MOV FLPMC 0FFH FLPMC register control inverts set value MOV FLPMC 00H Sets normal mode via FLPMC register control sets value BT PFS 0 ModeOffLoop Checks completion of write to specific ...

Page 257: ...ould be minimized in self programming mode are explained below 1 Erasure to blank check 1 Specification of block erase command 1 to 5 in 16 8 6 2 Mode is shifted from normal mode to self programming mode 1 to 7 in 16 8 4 3 Execution of block erase command Error check 6 to 11 in 16 8 6 4 Mode is shifted from self programming mode to normal mode 1 to 6 in 16 8 5 5 Specification of block blank check ...

Page 258: ...o self programming mode Figure 16 18 1 to 7 3 Execute block erase command Figure 16 20 6 to 11 4 Shift to normal mode Figure 16 19 1 to 6 5 Specify block blank check command 7 Check execution result VCERR and WEPRERR flags Figure 16 21 1 to 5 6 Shift to self programming mode Figure 16 18 1 to 7 7 Execute block blank check command Figure 16 21 6 to 11 8 Shift to normal mode Figure 16 19 1 to 6 Norm...

Page 259: ...WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS CMP A 00H BNZ StatusError Checks erase error Performs abnormal termination processing when an error occurs CALL ModeOff Shift to normal mode Sets blank check command MOV FLCMD 04H Sets flash control command block blank check MOV FLAPH 07H Sets block number for blank check block 7 is specified here MOV FLAPL 00H Fixes FLAPL to...

Page 260: ...I ModeOnLoop Configure settings so that the CPU clock 1 MHz MOV PFS 00H Clears flash status register MOV PFCMD 0A5H PFCMD register control MOV FLPMC 01H FLPMC register control sets value MOV FLPMC 0FEH FLPMC register control inverts set value MOV FLPMC 01H Sets self programming mode via FLPMC register control sets value NOP HALT BT PFS 0 ModeOnLoop Checks completion of write to specific registers ...

Page 261: ...lue MOV FLPMC 00H Sets normal mode via FLPMC register control sets value BT PFS 0 ModeOffLoop Checks completion of write to specific registers Repeats the same processing when an error occurs After the specific sequence is correctly executed restore the CPU clock to its setting before the self programming MOV MK0 INT_MK0 Restores interrupt mask flag EI RET ...

Page 262: ...tion of byte write command Error check 5 to 10 in 16 8 8 5 Mode is shifted from self programming mode to normal mode 1 to 6 in 16 8 5 6 2 to 5 is repeated until all data are written 7 The internal verify command is specified 1 to 5 in 16 8 9 8 Mode is shifted from normal mode to self programming mode 1 to 7 in 16 8 4 9 Execution of internal verify command Error check 6 to 11 in 16 8 9 10 Mode is s...

Page 263: ...on Normal Abnormal Figure 16 22 1 to 4 3 Shift to self programming mode Figure 16 18 1 to 7 4 Execute byte write command Figure 16 22 5 to 10 5 Shift to normal mode Figure 16 19 1 to 6 7 Specify internal verify command 9 Check execution result VCERR and WEPRERR flags Figure 16 23 1 to 5 8 Shift to self programming mode Figure 16 18 1 to 7 9 Execute internal verify command Figure 16 23 6 to 11 10 S...

Page 264: ...h data is to be written MOV A HL MOV FLW A Sets data to be written CALL ModeOn Shift to self programming mode Execution of write command MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS CMP A 00H BNZ StatusError Checks write error Performs abnormal termination processing when an error occurs CALL ModeOff Shift to normal mode MOV ...

Page 265: ...nal verify command MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS CMP A 00H BNZ StatusError Checks internal verify error Performs abnormal termination processing when an error occurs CALL ModeOff Shift to normal mode BR StatusNormal END abnormal termination processing Perform processing to shift to normal mode in order to retur...

Page 266: ...an error occurs RET Processing to shift to normal mode ModeOffLoop MOV FLCMD 00H Clears FLCMD register MOV PFS 00H Clears flash status register MOV PFCMD 0A5H PFCMD register control MOV FLPMC 00H FLPMC register control sets value MOV FLPMC 0FFH FLPMC register control inverts set value MOV FLPMC 00H Sets normal mode via FLPMC register control sets value BT PFS 0 ModeOffLoop Checks completion of wri...

Page 267: ...CHAPTER 16 FLASH MEMORY User s Manual U18172EJ2V0UD 267 DB XXH DB XXH DataAdrBtm Remark Internal verify 2 is used in the above program example Use internal verify 1 to verify s whole block ...

Page 268: ...3 CLK R F U R F U INTP R F U CLK RESET_IN R F U 1 kΩ 1 kΩ 10 kΩ VDD VDD 3 to 10 kΩ VDD VDD VDD VDD 1 to 10 kΩ VDD Caution The constants described in the circuit connection example are reference values If you perform flash programming aiming at mass production thoroughly evaluate whether the specifications of the target device are satisfied Notes 1 The RESET pin is used to download the monitor prog...

Page 269: ...onitor program X1 X2 RESET INTP1 VDD VSS RESET INTP1 VDD VSS 17 1 1 Connection of INTP1 pin The INTP1 pin is used only for communication between QB MINI2 and the target device during debugging Design circuits appropriately according to the relevant case among the cases shown below 1 INTP1 pin is not used in target system as is illustrated in Figure 17 1 Recommended Circuit Connection See Figure 17...

Page 270: ...er Programs downloaded by the debugger include the monitor program and such a program malfunctions if it is not controlled via QB MINI2 17 1 2 Connection of X1 and X2 pins The X1 and X2 pins are used when the debugger is started for the first time when downloading the monitor program and when programming is performed with the QB Programmer Figure 17 5 Circuit Connection for the Case Where X1 and X...

Page 271: ...ved for placing the debug monitor program so user programs cannot be allocated in these spaces Figure 17 6 Memory Spaces Where Debug Monitor Programs Are Allocated INTP1 interrupt vector 2 bytes for software break 2 bytes 0x7EH Internal ROM end address 304 bytes Internal ROM space Internal RAM space Stack area for debugging 5 bytes 0x18H Internal RAM end address Securement of serial interface for ...

Page 272: ...irect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 18 1 Operand Identifiers and Description Methods Identifier...

Page 273: ...k pointer PSW Program status word CY Carry flag AC Auxiliary carry flag Z Zero flag IE Interrupt request enable flag Memory contents indicated by address or register contents in parentheses H L Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit data displacem...

Page 274: ...sfr sfr A 2 4 sfr A A addr16 3 8 A addr16 addr16 A 3 8 addr16 A PSW byte 3 6 PSW byte A PSW 2 4 A PSW PSW A 2 4 PSW A A DE 1 6 A DE DE A 1 6 DE A A HL 1 6 A HL HL A 1 6 HL A A HL byte 2 6 A HL byte MOV HL byte A 2 6 HL byte A A X 1 4 A X A r Note 2 2 6 A r A saddr 2 6 A saddr A sfr 2 6 A sfr A DE 1 8 A DE A HL 1 8 A HL XCH A HL byte 2 8 A HL byte Notes 1 Except r A 2 Except r A X Remark One instru...

Page 275: ...addr16 A HL 1 6 A CY A HL ADD A HL byte 2 6 A CY A HL byte A byte 2 4 A CY A byte CY saddr byte 3 6 saddr CY saddr byte CY A r 2 4 A CY A r CY A saddr 2 4 A CY A saddr CY A addr16 3 8 A CY A addr16 CY A HL 1 6 A CY A HL CY ADDC A HL byte 2 6 A CY A HL byte CY A byte 2 4 A CY A byte saddr byte 3 6 saddr CY saddr byte A r 2 4 A CY A r A saddr 2 4 A CY A saddr A addr16 3 8 A CY A addr16 A HL 1 6 A CY...

Page 276: ... 6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL 1 6 A A HL AND A HL byte 2 6 A A HL byte A byte 2 4 A A byte saddr byte 3 6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL 1 6 A A HL OR A HL byte 2 6 A A HL byte A byte 2 4 A A byte saddr byte 3 6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL ...

Page 277: ...Z AC CY A byte 2 4 A byte saddr byte 3 6 saddr byte A r 2 4 A r A saddr 2 4 A saddr A addr16 3 8 A addr16 A HL 1 6 A HL CMP A HL byte 2 6 A HL byte ADDW AX word 3 6 AX CY AX word SUBW AX word 3 6 AX CY AX word CMPW AX word 3 6 AX word r 2 4 r r 1 INC saddr 2 4 saddr saddr 1 r 2 4 r r 1 DEC saddr 2 4 saddr saddr 1 ...

Page 278: ... BZ saddr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ saddr16 2 6 PC PC 2 jdisp8 if Z 0 saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 1 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 1 A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 BT PSW bit addr16 4 10 PC PC 4 jdisp8 if PSW bit 1 saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 0 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 3 8 PC PC 3 jdisp...

Page 279: ...HL byte addr16 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOVNote XCHNote ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV MOV INC DEC B C DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV DBNZ INC D...

Page 280: ...rp Note saddrp SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW rp MOVW MOVW Note INCW DECW PUSH POP saddrp MOVW sp MOVW Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd Operand 1st Operand addr16 None A bit BT BF SET1 CLR1 sfr bit BT BF SET1 CLR1 saddr bit BT BF SET1 CLR1 PSW bit BT BF SET1 CLR1 HL bit SET1 CLR1 CY SET1 CLR1 NOT1 ...

Page 281: ...2V0UD 281 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand 1st Operand AX addr16 addr5 addr16 Basic instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound instructions DBNZ 5 Other instructions RET RETI NOP EI DI HALT STOP ...

Page 282: ...ormal operation mode Operating ambient temperature TA During flash memory programming 40 to 85 C Flash memory blank status 65 to 150 C Storage temperature Tstg Flash memory programming already performed 40 to 125 C Note Must be 6 5 V or lower Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rat...

Page 283: ...n clear POC circuit is 2 1 V 0 1 V 2 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Caution When using the X1 oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines ...

Page 284: ......

Page 285: ...clock mode P20 and P21 0 0 3VDD V Total of output pins IOH 15 mA 4 0 V VDD 5 5 V IOH 5 mA VDD 1 0 V Output voltage high VOH IOH 100 µA 2 0 V VDD 4 0 V VDD 0 5 V Total of output pins IOL 30 mA 4 0 V VDD 5 5 V IOL 10 mA 1 3 V Output voltage low VOL 2 0 V VDD 4 0 V IOL 400 µA 0 4 V Input leakage current high ILIH VI VDD Pins other than X1 1 µA Input leakage current low ILIL VI 0 V Pins other than X1 ...

Page 286: ...High speed internal oscillation operating mode Note7 fX 8 MHz VDD 5 0 V 10 Note 4 When A D converter is operating 6 5 13 0 mA When peripheral functions are stopped 1 4 3 2 IDD4 High speed internal oscillation HALT mode Note 7 fX 8 MHz VDD 5 0 V 10 Note 4 When peripheral functions are operating 5 9 mA When low speed internal oscillation is stopped 3 5 20 0 VDD 5 0 V 10 When low speed internal oscil...

Page 287: ...in a voltage range of 2 2 to 5 5 V because the detection voltage VPOC of the power on clear POC circuit is 2 1 V 0 1 V 2 Selection of fsam fXP fXP 4 or fXP 256 is possible using bits 0 and 1 PRM000 PRM001 of prescaler mode register 00 PRM00 Note that when selecting the TI000 valid edge as the count clock fsam fXP CPU Clock Frequency Peripheral Clock Frequency Parameter Conditions CPU Clock fCPU Pe...

Page 288: ...Clock External Clock Input 1 2 3 4 5 6 0 1 0 4 1 0 10 60 0 33 2 7 5 5 16 Guaranteed operation range Supply voltage VDD V Cycle time T CY s µ TCY vs VDD High speed internal oscillator Clock 1 2 3 4 5 6 0 1 1 0 10 60 2 7 5 5 0 23 4 22 0 47 0 95 Supply voltage VDD V Cycle time T CY s Guaranteed operation range µ ...

Page 289: ...Manual U18172EJ2V0UD 289 AC Timing Test Points Excluding X1 Input 0 8VDD 0 2VDD 0 8VDD 0 2VDD Test points Clock Timing 1 fX tXL tXH X1 input TI000 Timing tTIL tTIH TI000 Interrupt Input Timing INTP0 INTP1 tINTL tINTH RESET Input Timing RESET tRSL ...

Page 290: ...r Notes 3 4 AINL 2 7 V VDD 4 0 V 0 25 Note 5 0 35 to 0 55 FSR 4 0 V VDD 5 5 V 0 20 to 0 35 Note 5 0 35 to 0 65 FSR Zero scale error Notes 3 4 Ezs 2 7 V VDD 4 0 V 0 25 Note 5 0 35 to 0 55 FSR 4 0 V VDD 5 5 V 0 20 to 0 35 Note 5 0 35 to 0 55 FSR Full scale error Notes 3 4 Efs 2 7 V VDD 4 0 V 0 25 Note 5 0 35 to 0 50 FSR 4 0 V VDD 5 5 V 1 5 Note 5 3 0 LSB Integral non linearity error Note 3 ILE 2 7 V...

Page 291: ... time 1 Note 1 tPTHD When power supply rises after reaching detection voltage MAX 3 0 ms Response delay time 2 Note 2 tPD When power supply falls 1 0 ms Minimum pulse width tPW 0 2 ms Notes 1 Time required from voltage detection to internal reset release 2 Time required from voltage detection to internal reset signal generation POC Circuit Timing Supply voltage VDD Detection voltage MIN Detection ...

Page 292: ...ion stabilization wait time Note 2 tLWAIT 0 1 0 2 ms Notes 1 Time required from voltage detection to interrupt output or internal reset signal generation 2 Time required from setting LVION to 1 to operation stabilization Remarks 1 VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 VLVI7 VLVI8 VLVI9 2 VPOC VLVIm m 0 to 9 LVI Circuit Timing Supply voltage VDD Detection voltage MIN Detection voltage TYP Detec...

Page 293: ... 5 V 0 4 s 3 5 V VDD 4 5 V 0 5 s TA 10 to 85 C NERASE 100 2 7 V VDD 3 5 V 0 6 s 4 5 V VDD 5 5 V 2 6 s 3 5 V VDD 4 5 V 2 8 s TA 10 to 85 C NERASE 1000 2 7 V VDD 3 5 V 3 3 s 4 5 V VDD 5 5 V 0 9 s 3 5 V VDD 4 5 V 1 0 s TA 40 to 85 C NERASE 100 2 7 V VDD 3 5 V 1 1 s 4 5 V VDD 5 5 V 4 9 s 3 5 V VDD 4 5 V 5 4 s Block erase time TBERASE TA 40 to 85 C NERASE 1000 2 7 V VDD 3 5 V 6 6 s Byte write time TWRI...

Page 294: ...ion T P at maximum material condition ITEM DIMENSIONS A B C E F G H I J L M N D 0 50 0 65 T P 0 10 0 05 0 08 0 08 0 07 1 45 MAX 1 20 6 40 0 20 4 40 0 10 0 10 1 00 0 20 0 50 0 13 0 10 0 24 K 0 17 P 3 5 3 UNIT mm P10MA 65 CAC V W W A I F G E B K H J P U L 3 60 0 10 T U V 0 25 T P 0 60 0 15 0 25 MAX W 0 15 MAX 5 S C S N M D M T 10 PIN PLASTIC SSOP 5 72 mm 225 ...

Page 295: ...nting Type Soldering Conditions 10 pin plastic SSOP lead free products µPD78F9200MA CAC A 78F9201MA CAC A 78F9202MA CAC A Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 260 C Time 60 seconds max at 220 C or higher Count 3 times or less Exposure limit 7 days Note after that prebake at 125 C for 10 to 72 hours IR60 107 3 Wave soldering For...

Page 296: ...t of systems using the 78K0S KU1 Figure A 1 shows development tools Compatibility with PC98 NX series Unless stated otherwise products which are supported by IBM PC ATTM and compatibles can also be used with the PC98 NX series When using the PC98 NX series therefore refer to the explanations for IBM PC AT and compatibles ...

Page 297: ...e Software package Flash memory writing environment Assembler package C compiler package Device file C library source fileNote 1 Integrated debuggerNote 3 System simulator Software package Project Manager Windows version only Note 2 Notes 1 The C library source file is not included in the software package 2 The Project Manager PM is included in the assembler package PM is used only in the Windows ...

Page 298: ...ash memory writing environment Assembler package C compiler package Device file C library source fileNote 1 Integrated debuggerNote 4 System simulator Software package Project Manager Windows version only Note 2 Notes 1 The C library source file is not included in the software package 2 The Project Manager PM is included in the assembler package PM is used only in the Windows environment 3 The on ...

Page 299: ...aution when used in PC environment The assembler package is a DOS based application but may be used under the Windows environment by using PM of Windows included in the assembler package RA78K0S Assembler package Part number µS RA78K0S Program that converts program written in C language into object codes that can be executed by microcontroller Used in combination with assembler package RA78K0S and...

Page 300: ...his software a series of user program development operations including starting the editor build and starting the debugger can be executed on the PM Caution The PM is included in the assembler package RA78K0S It can be used only in the Windows environment A 4 Flash Memory Writing Tools FlashPro4 FL PR4 PG FP4 FlashPro5 FL PR5 PG FP5 Flash memory programmer Flash programmer dedicated to the microco...

Page 301: ...ash memory Specifications of pin header on target system 16 pin general purpose connector 2 54 mm pitch A 6 Debugging Tools Software This debugger supports the in circuit emulators for the 78K0S Kx1 Series ID78K0S QB is Windows based software Provided with the debug function supporting C language source programming disassemble display and memory display are possible This is used with the device fi...

Page 302: ...ckage 1pin Unit mm Exchange adapter tip area Components up to 3 5 mm high can be mounted Target connector area Exchange adapter mounted component area Components up to 2 0 mm high can be mounted Center point of Target connector Top view 9 0 7 5 6 4 4 5 5 9 4 1 1pin Unit mm Exchange adapter tip area Components up to 3 5 mm high can be mounted Target connector area Exchange adapter mounted component...

Page 303: ...able single track A interval pin header More than 2 54mm Unit mm A contact area of a pin header 0 635 0 635mm Height 6mm Top view 2 54 2 54 A interval pin header More than 2 54mm Unit mm A contact area of a pin header 0 635 0 635mm Height 6mm Top view 2 54 2 54 Overview Viewing direction Target cable Pin header IECUBE ...

Page 304: ...hannel specification register ADS 155 C Capture compare control register 00 CRC00 88 E External interrupt mode register 0 INTM0 171 F Flash address pointer H compare register FLAPHC 230 Flash address pointer L compare register FLAPLC 230 Flash address pointer H FLAPH 230 Flash address pointer L FLAPL 230 Flash programming command register FLCMD 229 Flash programming mode control register FLPMC 225...

Page 305: ... 2 P2 60 Port register 3 P3 60 Port register 4 P4 60 Preprocessor clock control register PPCC 67 Prescaler mode register 00 PRM00 90 Processor clock control register PCC 67 Pull up resistor option register 2 PU2 62 Pull up resistor option register 3 PU3 62 Pull up resistor option register 4 PU4 62 R Reset control flag register RESF 194 W Watchdog timer enable register WDTE 141 Watchdog timer mode ...

Page 306: ...e compare control register 00 88 F FLAPH Flash address pointer H 230 FLAPHC Flash address pointer H compare register 230 FLAPL Flash address pointer L 230 FLAPLC Flash address pointer L compare register 230 FLCMD Flash programming command register 229 FLPMC Flash programming mode control register 225 FLW Flash write buffer register 231 I IF0 Interrupt request flag register 0 170 INTM0 External int...

Page 307: ...Port mode control register 2 60 91 127 156 PPCC Preprocessor clock control register 67 PRM00 Prescaler mode register 00 90 PU2 Pull up resistor option register 2 62 PU3 Pull up resistor option register 3 62 PU4 Pull up resistor option register 4 62 R RESF Reset control flag register 194 T TM00 16 bit timer counter 00 83 TMC00 16 bit timer mode control register 00 86 TMHMD1 8 bit timer H mode regis...

Page 308: ...set p 51 P34 Because the P34 pin functions alternately as the RESET pin if it is used as an input port pin the function to input an external reset signal to the RESET pin cannot be used The function of the port is selected by the option byte For details refer to CHAPTER 15 OPTION BYTE Also since the option byte is referenced after the reset release if low level is input to the RESET pin before the...

Page 309: ... flows Do not fetch signals from the oscillator p 70 Even if TM00 is read the value is not captured by CR010 pp 83 115 Hard TM00 16 bit timer counter 00 When TM00 is read count misses do not occur since the input of the count clock is temporarily stopped and then resumed after the read pp 83 115 Set CR000 to other than 0000H in the clear start mode entered on match between TM00 and CR000 This mean...

Page 310: ...nt stop and the input of the capture trigger conflict the capture data is undefined pp 85 117 CR010 16 bit capture compare register 010 Changing the CR010 setting during TM00 operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 17 Changing compare register during timer operation p 86 16 bit timer counter 00 TM00 starts operation at ...

Page 311: ...e count clock do not set the clear start mode and the capture trigger at the valid edge of the TI000 pin pp 90 118 In the following cases note with caution that the valid edge of the TI0n0 pin is detected 1 Immediately after a system reset if a high level is input to the TI0n0 pin the operation of the 16 bit timer counter 00 TM00 is enabled If the rising edge or both rising and falling edges are s...

Page 312: ...not set the OSPT00 bit to 1 again while the one shot pulse is being output To output the one shot pulse again wait until the current one shot pulse output is completed pp 110 116 Hard When using the one shot pulse output of 16 bit timer event counter 00 with a software trigger do not change the level of the TI000 pin or its alternate function port pin Because the external trigger is valid even in ...

Page 313: ...racteristics refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS p 121 Chapter 6 Soft 16 bit timer event counters 00 External clock limitation When an external waveform is input to 16 bit timer event counter 00 it is sampled by the noise limiter circuit and thus an error occurs on the timing to become valid inside the device p 121 CMP01 8 bit timer H compare register 01 CMP01 cannot be rewritten during ...

Page 314: ...s not performed an internal reset signal is generated when the watchdog timer overflows after STOP instruction execution p 142 Chapter 8 Hard Watchdog timer when low speed internal oscillator can be stopped by software is selected by option byte In this mode watchdog timer operation is stopped during HALT STOP instruction execution After HALT STOP mode is released counting is started again using t...

Page 315: ...converter mode register ADM to 0 before executing the STOP instruction p 164 Hard Input range of ANI0 to ANI3 Observe the rated range of the ANI0 to ANI3 input voltage If a voltage of VDD or higher and VSS or lower even in the range of absolute maximum ratings is input to an analog input channel the converted value of that channel becomes undefined In addition the converted values of the other cha...

Page 316: ...ersion result and ADIF for the pre change analog input may be set just before the ADS rewrite Caution is therefore required since at this time when ADIF is read immediately after the ADS rewrite ADIF is set despite the fact A D conversion for the post change analog input has not ended When A D conversion is stopped and then resumed clear ADIF before the A D conversion operation is resumed p 165 Co...

Page 317: ...hen release the STOP mode set the oscillation stabilization time as follows Expected oscillation stabilization time of resonator Oscillation stabilization time set by OSTS p 179 Hard The wait time after the STOP mode is released does not include the time from the release of the STOP mode to the start of clock oscillation a in the figure below regardless of whether STOP mode was released by reset s...

Page 318: ...cinity of the POC detection voltage VPOC the system may be repeatedly reset and released from the reset status In this case the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action p 197 To stop LVI follow either of the procedures below When using 8 bit manipulation instruction Write 00H to LVIM When using 1 bit memor...

Page 319: ...dog timer WDT is fixed to low speed internal oscillation clock p 211 Low speed internal oscillates If it is selected that low speed internal oscillator can be stopped by software supply of the count clock to WDT is stopped in the HALT STOP mode regardless of the setting of bit 0 LSRSTOP of the low speed internal oscillation mode register LSRCM Similarly clock supply is also stopped when a clock ot...

Page 320: ...asing the HALT status and then execute self programming p 225 Check FPRERR using a 1 bit memory manipulation instruction p 225 The state of the pins in self programming mode is the same as that in HALT mode p 225 Since the security function set via on board off board programming is disabled in self programming mode the self programming command can be executed regardless of the security function se...

Page 321: ... erase is performed and FFH when a blank check is performed p 230 pp 232 Shifting to self programming mode Shifting to normal mode Be sure to perform the series of operations described above using the user program at an address where data is not erased or written 233 235 236 Chapter 16 Soft Flash memory Byte write If a write results in failure erase the block once and write to it again p 244 Do no...

Page 322: ...s short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as VSS Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator p 283 Chapter 19 Hard Electrica...

Page 323: ... Wiring Between 78K0S KU1 and FlashPro4 FlashPro5 QB MINI2 and Addition of Note 2 Modification of Figure 16 3 Wiring diagram with FlashPro4 FlashPro5 QB MINI2 Deletion of PG FPL2 from dedicated flash memory programmer p 218 Modification of Figure 16 5 PG FP5 GUI Software Setting Example p 220 Modification of Figure 16 7 Communication Commands p 224 Addition of Note in Table 16 10 Self Programming ...

Page 324: ...l 02 8175 9600 http www tw necel com NEC Electronics Singapore Pte Ltd 238A Thomson Road 12 08 Novena Square Singapore 307684 Tel 6253 8311 http www sg necel com NEC Electronics Korea Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 02 558 3737 http www kr necel com For further information please contact G0706 Europe NEC Electronics Europe GmbH Arcadiastrasse 10 4...

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