Refreshing
The DP8409A also provdes hidden refresh capability while
in one of the automatic access modes (
Figure 4 ). In this
mode, it will automatically perform a refresh without the sys-
tem being interrupted. To do this, the DP8409A requires two
clock signals, refresh clock (RFCK) which defines the re-
fresh period (usually 16
m
s), and RAS generator clock
(RGCK), which is typically the microprocessor clock.
Highest priority is given to hidden refreshing through use of
level sensing of RFCK. A refresh cycle begins when RFCK
transitions to a high level. If during the time RFCK is high the
DP8409A is deselected (CS in the high state) and the proc-
essor is accessing another portion of the system such as
another memory segment, or ROM, or a peripheral, then a
hidden refresh is performed. When a read or write cycle is
initiated by the processor, the RASIN input on the DP8409A
transitions low. With CS high, this causes the present state
of the internal refresh counter to be placed on the address
outputs, followed by the four RAS outputs transitioning low,
strobing the refresh address into the DRAM array. When the
cycle ends, RASIN will terminate, thus forcing the RAS out-
puts back to their inactive state and ending the hidden re-
fresh. The refresh counter is then incremented and another
microprocssor cycle can begin immediately. However, to
save power, the DP8409A will allow only one hidden refresh
to occur during a given RFCK cycle.
In the event that a hidden refresh does not occur, the
DP8409A must force a refresh before the RFCK’s next
positive-going transition. The system is notified after the nega-
tive-going RFCK transition that a hidden refresh has not oc-
curred, via the refresh request output (RF I/O pin). The sys-
tem acknowledges the request for a forced refresh by set-
ting M2 (refresh) low on the DP8409A and preventing fur-
ther access to the DP8409A. The DP8409A then uses
RGCK to generate an automatic forced refresh. The refresh
request pin then returns to the inactive state, and the
DP8409A allows the processor to take full system control
after the forced refresh has been completed.
OCTAL MEMORY DRIVERS
For those applications where the memory array is extremely
large or the controller design is unique to a particular appli-
cation requirement, specialized high capacitive load ad-
dress and control buffers are required. However, like any
other element in a DRAM system, selection of the improper
driver can have significant impact on system performance.
In the past, this function has been performed using Schottky
logic family circuits such as the DM74S240 octal inverter or
the DM74S244 octal buffer. The output stages of these de-
vices have good drive capability, but their performance with
heavy capacitive loads is not ideal for DRAM arrays. The
key disadvantage of these devices is their non-symmetrical
rise and fall time characteristics and their long propagation
delays with heavy load capacitance. The former is a result
of impedance mismatch in the upper and lower output
stages. The latter stems from process capability and circuit
design techniques not tailored to the DRAM application.
The combined result of all these factors is increased output
skew in address and control lines when these devices are
used as buffers.
TL/F/5012 – 4
FIGURE 4. Hidden and Forced Refresh Timing of the DP8409A
4
Summary of Contents for DP8400
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