MICROPROCESSOR INTERFACE CIRCUITS
The major 8-bit, 16-bit and 32-bit microprocessors have dif-
ferent control signal timing. There are also a number of
speed options. The DP8400 family was designed, not for a
specific microprocessor, but rather, significant control flexi-
bility has been provided on both the DP84XX DRAM control-
ler/drivers and the DP84XX error correction devices for
easy interface to any microprocessor. However, a certain
amount of ‘‘glue’’ is necessary to interface to these LSI cir-
cuits, usually in the form of a number of MSI/SSI logic cir-
cuits. Not only can this be costly in board space utilization,
but it is usually the one place where the most design related
problems occur in system development.
Figures 13 and 14 show the DP8400 family solution to this
problemÐthe DP84XX2 series of microprocessor interface
circuits.
Figure 13 shows how the DP84300 refresh timer
and the DP84XX2 microprocessor interface circuit connect
to the DP8409A and various microprocessors for a typical
application.
Figure 14 shows the DP8409A and the DP8400
together in a microprocessor-based memory system using
DRAMs, with double bit error detect and single bit error cor-
rect capability. In addition, it shows that with the simple ad-
dition of some standard data buffers, how the system can
implement byte writing to the DRAM array.
This system structure requires the insertion of few or no wait
states during a memory access cycle, thus maximizing
throughput. The DP84XX2 circuits have been designed to
work with all of National’s DRAM controller/drivers to con-
trol refreshing so that system throughput is affected only
when absolutely necessary. First, in any refresh clock peri-
od of 16
m
s, hidden refreshing is given maximum opportuni-
ty. This can be helped with the optional DP84300 refresh
interval generator which offers maximum high-to-low ratio-
ing of RFCK. Second, when a hidden refresh does not occur
in a particular RFCK cycle, a forced refresh may still not
affect a slow access cycle. The worst-case is when an ac-
cess is pending during a forced refresh, in which case a
three wait state delay is usually the maximum penalty.
Usually two DP84XX2 type chips would be required to inter-
face between any microprocessor and the DP8400/
DP8409A combined system. These chips would handle the
read/write control as well as error detection and correction
control. Table VII shows the individual DP84XX2 circuits
that would be used in systems with no error correction, thus
requiring only the DP84XX DRAM controller/driver function.
²
The select wait input to the
DP843X2 chip inserts a wait
state during accessing. This is
necessary for very fast micro-
processors.
TL/F/5012 – 17
FIGURE 13. Connecting the DP8409A between 16-Bit Microprocessor and Memory
11
Summary of Contents for DP8400
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