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The 

“Configure I/O” button opens the user port option

menu window. Clicking the left mouse button selects the
desired port (the default Windows address and IRQ is
assumed). Clicking the 

“OK” button sends an identifica-

tion command out the selected port and listens for the
Capture board to echo back the command. This function
requires that DC power and data clock is present. If the
hardware is functional and the proper PC port connected,
the Configure I/O window will then close and return back
to the user Control Panel. Capture Board LED#6 will be lit
if the data clock is present.

If the incorrect serial port is selected or if the hardware is
dysfunctional (i.e. missing power or clock) the program
will return an error-warning window.

Click the 

“OK” button to clear the warning and then try

the other PC serial port in the 

“I/O Configuration”

window or correct the hardware problem.

The 

“Change Data File” button enables a dialog window

where the user can direct the location of the captured
data file. The desired file name and path can be typed
into the box. Clicking the left mouse on the button on the
right side of the file name box opens a standard browser
window to search for an appropriate file name.   The
“Default” button restores the default directory and file
name. The attached Matlab script analysis routines (*.m
files) assume that the data is located at this location;
however, the user can edit the routines to load from the
appropriate location. Clicking the 

“OK” button updates

the Capture program’s *.ini file and returns to the Capture
Control Panel.

The 

“Configure Capture” button invokes the user dialog

window for the remainder of the configuration options.
After selecting the desired options, a left mouse click on
“OK” stores the configuration variables and returns to
the Control Panel. Positioning the mouse pointer over the
Progress Bar inside the Control Panel pops up a text bub-
ble which displays the configuration variables used when
the Capture Program is started. Next is a discussion of
the Mode functions and the related sub-functions:

MODES
There are four primary modes in which to run the data
capture system, each with its own associated options:

1.

Capture mode configures the Capture Board for
data reception from the DRCS evaluation board.
Both serial and the parallel output ports can be used
as the source data path. 

a) The 

24-Bits option captures serial DRCS data

FROM either of the two serial data ports. The
Capture 1st Bit option should be selected for this
mode of data capture. With CLC5902 DDC in
“packed” and “mux_mode”, the AOUT data
source contains both phases of both DDC channels.
The two 

Channel buttons select the desired DDC

channel to be stored in the SRAM. The four 

Phase

buttons select either I or Q phase or the ordering of
alternating I/Q phases. In this latter case, the 32K
RAM space is shared. Therefore, only 16K points of
each phase are collected. If the 

BOUT data source

is selected, the CLC5902 DDC must be instructed
accordingly (i.e. “packed” and “mux_mode” off). With
the DDC in its default output format, the 

BOUT

serial port is disabled. 

b) The 

Upper 16-Bits and Lower 16-Bits options

enable the CLC5902 DDC’s parallel outputs. In this
configuration the DDC parallel output mux is
controlled by the FPGA through the 64 pin Euro
connector (be sure that the DRCS board SW1
“POUT” switches are OFF/OPEN). The user
selects 

Channel 

and 

Phase and the FPGA instructs

the DDC which channel, phase, and which half of
the 32-bit output word to send out its parallel data
bus. This configuration uses the FIFO for temporary
data storage. 

2.

Histogram mode returns the Capture Board to the
24-bit serial data mode. As before, with the
CLC5902 DDC in “packed” and “mux_mode”, the
AOUT data source contains both phases of both
DDC channels. A DDC change is required to enable
the 

BOUT. The Capture 1st Bit option should be

selected as before. In the 

Histogram configuration,

the program 

Start button first sets every SRAM

location value to zero. The hardware then samples
the data, reads the value at that memory location,
increments the value, and writes back the updated
value. The process continues until one of the
memory values reach the target value set by SW1

Summary of Contents for Data Capture Board CLC-CAPT-PCASM

Page 1: ...Receiver Transmitter an oscillator and a level translator IC The captured data is stored in either three 32K x 8 static RAMs organized into 24 bit words or in a FIFO containing 32K 18 bit words LEDs...

Page 2: ...n board An amplitude of 10 to 16dBm is recommended Here again the HP 8644B is a good choice Software 1 National Semiconductor Software All of the required software is provided on a CD ROM To install t...

Page 3: ...on board pin 20B The third jumper block J2 is unused Data Capture Board Block Diagram DIP Switches Five of the eight DIP switches are used to configure several capture functions as follows DIP switch...

Page 4: ...e Data Capture Board is powered up and the FPGA is initialized it is on to indicate that the board is ready After all the SRAM data has been output it is off LED 2 This LED is on when captured data is...

Page 5: ...ou start with the default file name and location shown Click on Default and then on OK If you do not have a C temp directory please make one The reason for this is that the Matlab script files for dat...

Page 6: ...configuration menu Select Histogram Debug as shown above and click on OK When the data capture control panel returns you can verify your capture settings by positioning the mouse over the progress bar...

Page 7: ...and Capture Board combination require 5V at 1A 4 An IBM Compatible Personal Computer running Windows 95 Windows 98 or Windows NT with a serial port capable of 115 200 baud 5 Serial data cable to conne...

Page 8: ...on The SRAM is useful for displaying time records of data or collecting contiguous blocks of slower data that have been decimated by the CLC5902 DDC The SRAM is the memory element used for the board s...

Page 9: ...rted Next is a discussion of the Mode functions and the related sub functions MODES There are four primary modes in which to run the data capture system each with its own associated options 1 Capture...

Page 10: ...ta source The DRCS Debug data will be displayed at the 15 bit resolution limit this is also the case for the DRCS 24 bit Serial Out data and the histogram will be centered about 16 384 assuming there...

Page 11: ...ditions The main portion of the noise power is contained in the carrier s immediate sidebands 5KHz Another point of interest is that there are several spectral lines about 75dBFS and 25KHz on either s...

Page 12: ...variable to 0 Setting the Dither variable excludes a lower portion of the spectrum from the FFT analysis and is intended to be used in conjunction with a base band dither signal being present at the...

Page 13: ...13 http www national com CLC CAPT PCASM Evaluation Board Layer 1 CLC CAPT PCASM Evaluation Board Layer 2 CLC CAPT PCASM Evaluation Board Layer 3 CLC CAPT PCASM Evaluation Board Layer 4...

Page 14: ...1 1 1 1 6 287 287 287 1 9 9 1 1 1 1 1 1 1 6 6 287 9 9 9 9 5 9 9 9 9 1 4 5 2 2 5 1 57 4 4 9 4 3 3 1 1 5 5 1 2 9 1 4 1 4 602 9 4 1 4 4 4 4 4 4 9 4 4 1 4 4 1 4 56 1 1 1 1 1 865 21 B 21 6 7 7 7 7 7 7 7 7...

Page 15: ...o perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor National Semicondu...

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