background image

If your data capture results in something similar to what is

shown  here  in 

Figure  3

  or  in 

Figure  4

,  take  another

sample. It may take a few trials to get good data.

Figure  4    Marginal  data  capture  that  results  from  trying  to

capture  data  that  is  near  but  not  right  at  the  point  where  the

ADC outputs are in transition.

Figure 5. Normal data capture.

Coherent sampling of a periodic waveform occurs when a

prime  integer  number  of  cycles  exists  in  the  sample

window.  The  relationship  between  the  number  of  cycles

sampled  (CY),  the  number  of  samples  taken  (SS),  the

signal  input  frequency  (fin) and the sample rate (fs), for

coherent sampling, is

Figure 3.  Poor data capture resulting from trying to capture

data while the ADC outputs are in transition

6.2 Coherent Sampling

Artifacts  can  result  when  we  perform  an  FFT  on  a

digitized  waveform,  producing  inconsistent  results  when

testing repeatedly. The presence of these artifacts means

that  the  ADC  under  test  may  perform  better  than  the

measurements would indicate.

CY

SS

f

in

f

s

=

CY, the number of  cycles  in  the  data  record,  must  be  a

prime integer number and SS, the number of samples in

the data record, must be a factor of 2 integer.

We  can  eliminate  the  need  for  windowing  and  get  more

consistent results if we observe the proper ratios between

the input and sampling frequencies. We call this 

coherent

sampling

.  Coherent  sampling  greatly  increases  the

spectral  resolution  of  the  FFT,  allowing  us  to  more

accurately  evaluate  the  spectral  response  of  the  A/D

converter.  When  we  do  this,  however,  we  must  be  sure

that the input signal has high spectral purity and stability

and  that  the  sampling  clock  signal  is  extremely  stable

with minimal jitter.

Further, fin (signal input frequency) and fs (sampling rate)

should  be  locked  to  each  other  so  that  the  relationship

between  the  two  frequencies  is  exact.  Locking  the  two

signal  sources  to  each  other  also  causes

 

whatever

sample-to-sample clock edge timing  variation  (jitter)  that

is present in the two signals to cancel each other.
Windowing (an FFT Option under WaveVision) should be

turned off for coherent sampling.

7.0 Evaluation Board Specifications

Board Size:

6.5" x 3.5" (16.5 cm x 8.9 cm)

Power Requirements:

+5.0V, 100 mA (ADC12040 /

ADC12010 / ADC12020) or

+3.3V, 120 mA (ADC12L063)
+5V @ 30 mA / 1A (see Sect 4.6)

Clock Frequency Range:

1.0 MHz to 40 MHz or 60 MHz

Analog Input

Nominal Voltage:

1.4VP-P

Impedance:

50 Ohms

              

7

          

http://www.national.com

Summary of Contents for ADC12010

Page 1: ...040 12 Bit 40 Msps 5 Volt 380 mW A D Converter ADC12010 12 Bit 10 Msps 5 Volt 160 mW A D Converter ADC12020 12 Bit 20 Msps 5 Volt 185 mW A D Converter ADC12L063 12 Bit 62 Msps 3 3 Volt 354 mW A D Converter 2001 2002 2003 2004 National Semiconductor Corporation 1 http www national com ...

Page 2: ... circuit 5 4 5 Digital Data Output 6 4 5 Power Supply Connections 6 4 6 Power Requirements 6 5 0 Installing the ADC12040 Evaluation Board 6 6 0 Obtaining Best Results 6 6 1 Clock Jitter 6 6 2 Coherent Sampling 7 7 0 Evaluation Board Specifications 8 8 0 Hardware Schematic 9 9 0 Evaluation Board Bill of Materials 10 A1 0 Operating in the Computer Mode 12 A2 0 Summary Tables of Test Points and Conne...

Page 3: ...on a PC monitor as a dynamic waveform The digitized output is also available at Euro connector J2 Provision is made for adjustment of the Reference Voltage VREF with VR1 2 0 Board Assembly The ADC12040 Evaluation Board may come pre assembled or as a bare board that must be assembled Refer to the Bill of Materials for a description of components to Figure 1 for major component placement and to Figu...

Page 4: ...ics 4 To use the crystal oscillator located at Y1 to clock the ADC connect the jumper at JP2 to pins 2 and 3 This is the default position The ADC clock signal may be monitored at TP7 Because of clock isolation resistor R12 and the scope probe capacitance the clock signal at TP7 will appear integrated 5 Connect the jumper at JP3 between pins 1 and 2 and the jumper at JP4 to pins 1 and 2 to select i...

Page 5: ...e of 0 to 2 4 Volts for the ADC12040 ADC12010 and ADC12020 or 0 to 1 2 Volts for the ADC12L063 The ADC12040 ADC12010 and ADC12020 are specified to operate with VREF in the range of 1 0 to 2 4 V with a nominal value of 2 0V while the ADC12L063 is specified to operate with VREF in the range of 0 8 to 1 2 V with a nominal value of 1 0V The reference voltage can be monitored at test point TP1 and is s...

Page 6: ...rable plot of Figure 2b Note that all dynamic performance parameters shown to the right of the FFT are improved by eliminating clock jitter To develop the ADC clock WAVEVISON BRD 3 0 Digital Interface Board divides its on board clock to provide the ADC clock In doing so jitter is introduced to the ADC clock degrading the observed performance of the ADC The amount of jitter produced by this evaluat...

Page 7: ...umber of samples in the data record must be a factor of 2 integer We can eliminate the need for windowing and get more consistent results if we observe the proper ratios between the input and sampling frequencies We call this coherent sampling Coherent sampling greatly increases the spectral resolution of the FFT allowing us to more accurately evaluate the spectral response of the A D converter Wh...

Page 8: ...1 C21 A22 B22 C22 A23 B23 C23 A24 B24 C24 A25 B25 C25 A26 B26 C26 A27 B27 C27 A28 B28 C28 A29 B29 C29 A30 B30 C30 A31 B31 C31 A32 B32 C32 J2 96 PIN FEMALE EURO DIN CONNECTOR V V 5V R10 not used Q1 MMBT2222A R1 330 D6 1N5227 3 6V 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 ADC12010 ADC12020 ADC12040 or ADC12L063 V REF V IN V IN AGND V A V A AGND PD D8 D7 D6 DR V D DR GND D5 D4 D3 32 31 30 29 28 27 26 2...

Page 9: ...12L063 Type 1206 25 R2 R10 R19 R2 R19 no exist not used n a 26 1 R4 0 shorting strap n a 27 2 R5 R18 100 5 Type 1206 28 2 R6 R17 47 5 Type 1206 29 2 R7 R8 33 5 47Ω for ADC12010 12020 Type 1206 30 2 R9 R13 200 5 Type 1206 31 2 R11 R15 10k 5 Type 1206 32 1 R12 470 5 Type 1206 33 1 R16 not used on ADC12L063 1K 5 Type 1206 34 1 R20 100k 5 Type 1206 35 1 R21 1K 5 Type 1206 36 R22 R23 R24 R25 not popula...

Page 10: ...ly voltage TP 3 Positive input signal to the ADC Vin TP 4 Negative input signal to the ADC Vin TP 5 Signal Input test point TP 6 Power Down active high input TP 7 ADC clock frequency monitor TP 8 5V power supply for ADC12040 12010 12020 or 3 3V for ADC12L063 TP 9 5V power supply for the Digital Interface Board if used TP 10 Optional negative power supply for breadboard area TP 20 Output Enable inp...

Page 11: ...ADC output D2 B17 ADC output D3 C17 ADC output D4 B18 ADC output D5 C18 ADC output D6 B19 ADC output D7 C19 ADC output D8 B20 ADC output D9 C20 ADC output D10 B21 ADC output D11 C21 GND A1 thru A24 A28 B28 C28 A31 B31 C31 ADC Output Enable C12 not used External clock input B23 Reserved signal B22 C22 C23 Reserved power A25 A26 B25 B26 C25 C26 5V Logic Power Supply to Digital Interface Board Reserv...

Page 12: ...MICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any com...

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