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Chapter 2
User-Defined FPGA Signals
Reference Schematic Design Considerations
Table 2-6 lists design considerations for the schematic shown in Figure 2-4
RS-4
8
5 Layout Considerations
Pay close attention to how the ground planes are arranged under the isolated RS-485 transceiver.
Isolated and non-isolated ground planes overlap across layers to provide some capacitance
between the grounds and help with EMC. Refer to the datasheet for the RS-485 transceiver for
more information.
CAN (CAN0, CAN1)
You can use any FPGA pins to implement a CAN interface port.
The reference carrier board implements one CAN port (CAN0). You can implement an
additional CAN port (CAN1) in the same way that the CAN0 signal is implemented on the
reference carrier board.
Table 2-6.
Serial5 Reference Schematic Design Considerations
Consideration
Notes
Interface
The reference carrier board demonstrates how to use the Serial5 interface
to implement an isolated RS-485 serial port.
Serial
transceiver
U25 is the RS-485 serial transceiver that converts between RS-485 and
LVTTL signal levels. This transceiver provides functional isolation of
the RS-485 signals to prevent ground loops from affecting the RS-485
signals.
Series
termination
• R140 is the series termination for Serial5. Use series termination at the
serial transceiver on all signals being driven to the sbRIO-9651 SOM.
• FPGA DIO signals from DIO Bank 0 include series termination on the
sbRIO-9651 SOM. Use series termination at the SEARAY connector
on all signals outside of Bank 0 being driven from the sbRIO-9651
SOM to the serial transceiver.