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© National Instruments
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NI sbRIO-9651 System on Module Carrier Board Design Guide
Reference Schematic Design Considerations
Table 2-2 lists design considerations for the schematics shown in Figures 2-1 and 2-2.
Table 2-2.
GBE1 Reference Schematic Design Considerations
Consideration
Notes
Ethernet PHY
selection
• The only PHY supported for secondary Ethernet is the Micrel
Ethernet PHY, part number KSZ9031MNXIA. Refer to Table 1-4,
Gigabit Ethernet Connector Parts
, of Chapter 1,
, for information about the Gigabit Ethernet connector parts
used in the sbRIO-9651 SOM development kit.
• To meet GMII timing to the sbRIO-9651 SOM, the DIO bank for the
PHY (DVDDH) and VIO_BANK2 on the sbRIO-9651 SOM must be
powered at 1.8 V.
• All pull-up and pull-down resistors connected to the PHY must be
implemented in your carrier board design as shown in Figure 2-1.
These connections ensure that the PHY is set up properly for
sbRIO-9651 SOM software support.
• Refer to the datasheet for the Micrel Ethernet PHY for more
information about secondary Ethernet PHY requirements.
GMII TX signals
• Route the GMII TX signals directly to the Ethernet PHY.
• To meet timing requirements, the TX signals must be 1.8 V logic.
• You must place series termination resistors at the sbRIO-9651 SOM
connector on the TX signals driving to the Ethernet PHY, as shown in
Figure 2-2.
GMII RX signals
• Connect the GMII RX signals directly to the Ethernet PHY.
• The pull resistors on the RX signals set options in the PHY when
coming out of reset.
• The pull resistors must be implemented in your carrier board design
as shown in Figure 2-1 to ensure that secondary Ethernet works
properly. The resistors must be the same values shown in Figure 2-1.
• You must place series termination resistors near the Ethernet PHY on
all RX signals, as shown in Figure 2-1.
PHY crystal
selection
• NI recommends that you use a crystal with the Ethernet PHY.
• The crystal must be 25 MHz with 50 ppm or better accuracy.
• Ensure that you use suitable load capacitors for your crystal.