Digital I/O Single-Ended Channels
Number of channels
8
Signal type
Single-ended
Voltage families
3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V
Input impedance
100 kΩ, nominal
Output impedance
50 Ω, nominal
Direction control
Per channel
Minimum required direction change
latency
200 ns
Maximum output toggle rate
60 MHz with 100 μA load, nominal
Table 2. DIGITAL I/O Single-Ended DC Signal Characteristics
2
Voltage Family
V
IL
V
IH
V
OL
(100µA load)
V
OH
(100µA load)
Maximum DC Drive
Strength
3.3 V
0.8 V
2.0 V
0.2 V
3.0 V
24 mA
2.5 V
0.7 V
1.6 V
0.2 V
2.2 V
18 mA
1.8 V
0.62 V 1.29 V
0.2 V
1.5 V
16 mA
1.5 V
0.51 V 1.07 V
0.2 V
1.2 V
12 mA
1.2 V
0.42 V 0.87 V
0.2 V
0.9 V
6 mA
Digital I/O High-Speed Serial MGT
3
Note
MGTs are available on devices with KU040 and KU060 FPGAs only.
Data rate
500 Mbps to 16.375 Gbps, nominal
Number of Tx channels
4
Number of Rx channels
4
I/O AC coupling capacitor
100 nF
2
Voltage levels are guaranteed by design through the digital buffer specifications.
3
For detailed FPGA and High-Speed Serial Link specifications, refer to Xilinx documentation.
PXIe-5763 Specifications
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© National Instruments
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