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2-15
To make sure that your application can run and control a process at 2 kHz, and that the first
output is generated within the first sample period, make sure that the following conditions are
satisfied:
500 µs
≤
Transfer Time
+
Application Time
(2-1)
where:
Transfer Time
—the time it takes to transfer samples between the DAQ device and the PXIe
controller or computer.
Application Time
—the time it takes for the PXIe controller or computer to analyze the
acquired data and generate the AO stimulus.
Using Equation 2-1 and the Transfer Time from the sample system described in this section, you
can determine that an application time of 480
μ
s is required to close a 2 kHz control loop.
Application Time
≤
500 µs -
Transfer Time
Application Time
≤
500 µs - 20 µs
Application Time
≤
480 µs
Any application taking more than 480
μ
s will fail to close the 2 kHz control loop.
When analyzing the bandwidth of the system, you must consider the group delay of all the
components of the system. When using only the NI PXIe-4302/4303 internal 2 kHz filter, the
bandwidth of the control loop is as follows:
Control Bandwidth
= 1.613 kHz
Note
You can increase the bandwidth of the system by either reducing the
application time or by using another filter option with lower group delay.
Timing and Triggering
This section contains information about the timing and triggering theory of operation.
Sample Clock Timebase
The ADCs require an oversample clock to drive the conversion. The oversample clock
frequency is greater than the sample rate. On the NI PXIe-4302/4303 modules the oversample
clock is produced from a 106.25 MHz reference clock. This 106.25 MHz reference clock can be
phase locked with the PXIe backplane 100 MHz clock or be generated by an internal timebase
ControlBandwidth
1
TransferTime ApplicationTime FilterGroupDelay
+
+
-----------------------------------------------------------------------------------------------------------------------------------------------
=
ControlBandwidth
1
20
μ
s 480
μ
s 120
μ
s
+
+
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=