8-Slot NI PXIe-1082 Backplane Installation Guide
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PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 have the default timing
relationship described in Figure 6.
Figure 6.
System Reference Clock Default Behavior
To synchronize the system to an external clock, you can drive PXI_CLK10
from an external source through the PXI_CLK10_IN pin on the System
Timing Slot. Refer to Table 10,
XP4 Connector Pinout for the System
, for the pinout. When a 10 MHz clock is detected on this pin,
the backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100,
and PXIe_SYNC100 signals to this external clock and distributes these
signals to the slots. Refer to the
section for the
specification information for an external clock provided on the
PXI_CLK10_IN pin of the system timing slot.
You also can drive a 10 MHz clock on connector J36. Refer to Figure 11 for
the location of this connector. When a 10 MHz clock is detected on this
connector, the backplane automatically phase-locks the PXI_CLK10,
PXIe_CLK100, and PXIe_SYNC100 signals to this external clock and
distributes these signals to the slots. Refer to the
section for the specification information for an external clock provided
on J36.
If the 10 MHz clock is present on both the PXI_CLK10_IN pin of the
System Timing Slot and connector J36, the signal on the System Timing
Slot is selected. Refer to Table 1, which explains how the backplane selects
the 10 MHz clocks.
PXIe_CLK100
PXI_CLK10
PXIe_SYNC100
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
