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National Instruments Corporation

NI 5731/5732/5733/5734R User Guide and Specifications

Clocking

The NI 5731/5732/5733/5734 clocks control the sample rate and other timing functions on the device.
Table 4 contains information about the possible NI 5731/5732/5733/5734 clock resources.

Note

Specifications for the NI 5731/5732/5733/5734 adapter modules were characterized only at

the maximum sample rates.

Note

For more information about configuring clocks, refer to the respective CLIP Help section for

your device in the

NI FlexRIO Help

Table 4.

NI 5731/5732/5733/5734 Clock Sources

Clock

Configuration

Supported Sample

Rates

External

Clock

Type

External Clock

Frequency

Description

Internal Clock
PLL Off

NI 5731 = 40 MS/s
NI 5732 = 80 MS/s

NI 5733 = 120 MS/s
NI 5734 = 120 MS/s

—

The internal VCXO
acts as a free-running
clock.

Internal Clock
PLL On
(IoModSyncClk)

NI 5731 = 40 MS/s
NI 5732 = 80 MS/s

NI 5733 = 120 MS/s
NI 5734 = 120 MS/s

—

10 MHz

The internal VCXO
locks to
IoModSyncClk (Sync
Clock), which is
provided only through
the backplane of
supported devices.

Internal Clock
PLL On
(CLK IN)

NI 5731 = 40 MS/s
NI 5732 = 80 MS/s

NI 5733 = 120 MS/s
NI 5734 = 120 MS/s

Reference

clock

10 MHz

The internal VCXO
locks to an external
Reference clock,
which is provided
through the CLK IN
front panel connector.

External Clock
(CLK IN)

The supported

sample rate is equal

to the external clock

frequency.

Sample

clock

NI 5731 Min = 3 MHz

NI 5731 Max = 40 MHz

NI 5732 Min = 20 MHz

NI 5732 Min = 10 MHz

†

NI 5732 Max = 80 MHz

NI 5733 Min = 50 MHz

NI 5733 Max = 120 MHz

NI 5734 Min = 50 MHz

NI 5734 Max = 120 MHz

An external Sample
clock can be provided
through the CLK IN
front panel connector.

Duty Cycle Stabilizer (DCS) enabled. DCS enabled is the default setting for all NI 5731/5732/5733/5734 CLIP items. You

can disable the DCS by adjusting register 9 in the ADC.

†

DCS disabled.

Summary of Contents for NI 5731

Page 1: ...NI 5732...

Page 2: ...5733 5734 adapter module and your NI FlexRIO FPGA module NI 5731 5732 5733 5734 refers to your NI 5731 5732 5733 5734 adapter module only A description of each of the NI 5731 5732 5733 5734 devices is...

Page 3: ...degradation install and use this product in strict accordance with instructions in the product documentation Furthermore any changes or modifications to the product not expressly approved by National...

Page 4: ...Embedded in LabVIEW Help Contains information about the basic functionality of LabVIEW FPGA Module NI FlexRIO Help Embedded in LabVIEW FPGA Module Help Contains FPGA module adapter module and CLIP co...

Page 5: ...alog input channel 0 AI 1 50 single ended analog input channel 1 AI 2 50 single ended analog input channel 2 NI 5734 only AI 3 50 single ended analog input channel 3 NI 5734 only CLK IN Reference or e...

Page 6: ...ctor Pin Signal Signal Description 1 DIO Port 0 0 Bidirectional single ended digital I O data channel 2 GND Ground reference for signals 3 DIO Port 0 1 Bidirectional single ended digital I O data chan...

Page 7: ...t 0 WE DIO Port 0 Rd Data 0 DIO Port 0 Wr Data 0 DIO Port 0 Rd Data 1 DIO Port 0 Wr Data 1 DIO Port 0 Rd Data 2 DIO Port 0 Wr Data 2 DIO Port 0 Rd Data 3 DIO Port 0 Wr Data 3 DIO Port 1 Rd Data 0 DIO...

Page 8: ...the same IP integration functionality of the user defined CLIP but also allows the CLIP to communicate directly with circuitry external to the FPGA Adapter module socketed CLIP allows your IP to commu...

Page 9: ...put data is accessed using a U16 data type left justified The DIO signals are grouped into two ports of four signals each and are accessed using a U8 data type and Boolean write enable signal The four...

Page 10: ...ning clock Internal Clock PLL On IoModSyncClk NI 5731 40 MS s NI 5732 80 MS s NI 5733 120 MS s NI 5734 120 MS s 10 MHz The internal VCXO locks to IoModSyncClk Sync Clock which is provided only through...

Page 11: ...I 5731 5732 5733 5734 1 Connect one end of an BNC cable to AI 0 on the front panel of the NI 5731 5732 5733 5734 and the other end of the cable to your device under test DUT 2 Launch LabVIEW 3 In the...

Page 12: ...l The VI acquires data and displays the captured waveform on the Acquired Waveform graph as shown in Figure 5 14 Click the STOP button to stop the VI Close the VI Figure 5 NI 573x Getting Started Host...

Page 13: ...le Clock 0 7 Enter the default Sample clock rate for your device 40 80 or 120 in the Compile for single frequency control and click OK 8 Right click IO Module in the Project Explorer window and select...

Page 14: ...on the block diagram 4 Right click the Open FPGA VI Reference function and select Configure Open FPGA VI Reference 5 In the Configure Open FPGA VI Reference dialog box select VI in the Open section 6...

Page 15: ...31 5732 5733 5734 and the other end of the cable to your DUT 2 Open the front panel of 573xSampleAcq Host vi 3 Click the Run button to run the VI 4 The VI acquires data from the DUT on AI 0 Data N 5 C...

Page 16: ...level based on measurements taken during development or production Note Specifications for the NI 5731 5732 5733 5734 adapter modules were characterized only at the maximum sample rates Analog Input A...

Page 17: ...732 2 055 Vpk pk 1 028 Vpk pk 0 5138 Vpk pk NI 5733 5734 2 085 Vpk pk 1 043 Vpk pk 0 5212 Vpk pk Table 6 DC Gain Error Full Scale Device Gain 0 dB Gain 6 dB Gain 12 dB NI 5731 0 9 1 2 1 7 NI 5732 0 5...

Page 18: ...110 MHz 29 6 MHz 16 1 MHz NI 5733 5734 117 MHz 37 1 MHz 24 1 MHz Table 9 Maximum Frequency to 2 ns Device Elliptic Filter Bessel Filter NI 5731 9 MHz 18 MHz NI 5732 20 MHz 37 MHz NI 5733 5734 30 MHz 5...

Page 19: ...2 dB NI 5731 4 9 MHz 87 dBc 87 dBc 90 dBc NI 5732 9 7 MHz 85 dBc 89 dBc 91 dBc NI 5733 5734 9 7 MHz 83 dBc 86 dBc 87 dBc Table 13 NI 5731 5732 5733 5734 AI Channel Crosstalk Aggressor Channel N 0 3 Re...

Page 20: ...tion 19 NI 5731 5732 5733 5734R User Guide and Specifications Phase adjust DAC range NI 5731 406 13 degrees NI 5732 427 13 degrees NI 5733 5734 429 9 degrees Frequency adjust DAC range 160 ppm Data ra...

Page 21: ...sponse Figure 8 AC Coupled Low Frequency Response Multiple Channels Overlaid Figure 9 Filter Bypass Frequency Response Multiple Channels Overlaid 10 k 6 Amplitude dBFS Frequency Hz 100 k 1 2 3 4 5 0 1...

Page 22: ...Filter Frequency Response Multiple Channels Overlaid Figure 11 Elliptic Filter Frequency Response 0 to 6 dB Multiple Channels Overlaid 1 90 Amplitude dBFS Frequency MHz 10 100 80 70 60 50 40 30 20 10...

Page 23: ...ency Response Multiple Channels Overlaid Figure 13 Bessel Filter Frequency Response 0 to 6 dB Multiple Channels Overlaid 1 90 Amplitude dBFS Frequency MHz 10 100 80 70 60 50 40 30 20 10 0 NI 5732 NI 5...

Page 24: ...d Specifications NI 5731 Group Delay Figure 14 NI 5731 Elliptic Filter Group Delay 12 Channels Overlaid Figure 15 NI 5731 Bessel Filter Group Delay 12 Channels Overlaid 1 2 Group Delay ns Frequency MH...

Page 25: ...NI 5732 Group Delay Figure 16 NI 5732 Elliptic Filter Group Delay 12 Channels Overlaid Figure 17 NI 5732 Bessel Filter Group Delay 12 Channels Overlaid 1 Group Delay ns Frequency MHz 10 1 0 2 3 4 5 6...

Page 26: ...ications NI 5733 5734 Group Delay Figure 18 NI 5733 5734 Elliptic Filter Group Delay 44 Channels Overlaid Figure 19 NI 5733 5734 Bessel Filter Group Delay 44 Channels Overlaid 1 2 Group Delay ns Frequ...

Page 27: ...Onboard Oscillator 618 FS RMS Jitter NI 5732 Figure 21 NI 5732 AI Phase Noise 23 17 MHz Input PLL Unlocked Onboard Oscillator 466 FS RMS Jitter 150 10 100 1k 10k 100k 1M 10M 140 130 Amplitude dBc Hz...

Page 28: ...Oscillator 453 FS RMS Jitter Figure 23 NI 5733 5734 AI Phase Noise 40 MHz Input PLL Locked to PXI 10 MHz Reference Clock Onboard Oscillator 448 FS RMS Jitter 150 10 100 1k 10k 100k 1M 10M 140 130 Ampl...

Page 29: ...I 5731 Gain at 0 dB Elliptic Bessel or Filter Bypass AC or DC coupled Figure 25 NI 5731 Gain at 12 dB Elliptic Bessel or Filter Bypass AC or DC coupled 12 10 8 4 16 14 18 6 2 120 110 100 70 80 90 Ampl...

Page 30: ...Filter Bypass AC or DC coupled Figure 27 NI 5732 Gain at 12 dB Elliptic Bessel or Filter Bypass AC or DC coupled 120 110 100 70 80 90 Amplitude dBFS Frequency MHz 0 20 10 40 30 50 60 28 25 13 5 35 33...

Page 31: ...Filter Bypass AC or DC coupled Figure 29 NI 5733 5734 Gain at 12 dB Elliptic Bessel or Filter Bypass AC or DC coupled 120 110 100 0 10 15 5 20 25 30 35 40 50 45 55 60 70 80 90 Amplitude dBFS Frequency...

Page 32: ...Gain at 0 dB 1 dBFS at 4 9 MHz 95 dBc SFDR Bypass Filter 100 Averages RMS Figure 31 NI 5731 Gain at 12 dB 1 dBFS at 4 9 MHz 93 dBc SFDR Bypass Filter 100 Averages RMS 110 100 0 2 4 6 8 10 12 16 14 18...

Page 33: ...SFDR Bypass Filter 10 Averages RMS NI 5732 Figure 33 NI 5732 Gain at 0 dB 1 dBFS at 9 7 MHz 91 dBc SFDR Bypass Filter 100 Averages RMS 110 100 90 0 4 6 2 8 10 12 16 20 60 70 80 Amplitude dBFS Frequen...

Page 34: ...at 9 7 MHz 94 dBc SFDR Bypass Filter 100 Averages RMS Figure 35 NI 5732 Gain at 12 dB 1 dBFS at 9 7 MHz 94 dBc SFDR Bypass Filter 10 Averages RMS 110 100 90 0 15 5 20 25 35 40 60 70 80 Amplitude dBFS...

Page 35: ...c SFDR Bypass Filter 100 Averages RMS Figure 37 NI5733 5734 Gain at 12 dB 1 dBFSat20 1 MHz 87 dBc SFDR Bypass Filter 100AveragesRMS 110 100 0 10 15 5 20 25 30 35 40 50 45 55 60 70 80 90 Amplitude dBFS...

Page 36: ...c SFDR Bypass Filter 10 Averages RMS Two Tone FFT Figure 39 NI 5732 at 12 dB Gain and Filter Bypass 83 dBc fin 19 6 MHz 7 dBFS 20 8 MHz 7 dBFS 100 Average RMS 110 100 90 0 15 25 5 30 35 55 60 60 70 80...

Page 37: ...y NI 5731 40 MHz 50 ppm NI 5732 80 MHz 100 ppm NI 5733 5734 120 MHz 100 ppm Phase noise Refer to the Analog Input Total Phase Noise section Typical Specifications Frequency stability Temperature 30 pp...

Page 38: ...locks to IoModSyncClk Sync Clock which is provided only through the backplane of supported devices Internal Clock PLL On CLK IN NI 5731 40 MS s NI 5732 80 MS s NI 5733 120 MS s NI 5734 120 MS s Refere...

Page 39: ...OL 0 4 V Minimum VOH 2 7 V Maximum VOH 3 6 V Zout 50 20 Iout DC 2 mA Pull down resistor 150 k Recommended operating voltage 0 3 V to 3 6 V Overvoltage protection 10 V Maximum toggle frequency 6 6 MHz...

Page 40: ...e Shock and Vibration Operational shock 30 g peak half sine 11 ms pulse tested in accordance with IEC 60068 2 27 Test profile developed in accordance with MIL PRF 28800F Random vibration Operating 5 H...

Page 41: ...urposes Note For EMC declarations and certifications and additional information refer to the Online Product Certification section of this document CE Compliance This product meets the essential requir...

Page 42: ...elf help resources to email and phone assistance from NI Application Engineers National Instruments corporate headquarters is located at 11500 North Mopac Expressway Austin Texas 78759 3504 National I...

Page 43: ...ollowing instructions to install PXI EMC filler panels National Instruments part number 778700 01 in your PXI chassis 1 Remove the captive screw covers 2 Install the PXI EMC filler panels by securing...

Page 44: ...the patents txt file on your media or the National Instruments Patent Notice at ni com patents Refer to the Export Compliance Information at ni com legal export compliance for the National Instruments...

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