National Instruments Low-Cost Multifunction I/O Board for ISA..., User Manual

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Register-Level Programming Appendix E
Lab-PC+ User Manual E-10 © National Instruments Corporation
4. Program Counter A1 to force OUT1 low.
If OUT1 is high, Counter A0 is disabled. Write 70 (hex) to the Counter A Mode Register
(select Counter A1, Mode 0) to force OUT1 low. Counter A0 can be used as the Sample
Interval Counter.
5. Clear the A/D circuitry.
Before you start the data acquisition operation, the A/D FIFO must be emptied in order to
clear out any old A/D conversion results. This emptying must be performed after the
counters are programmed in case any spurious edges were caused while programming the
counters. Write 0 to the A/D Clear Register to empty the FIFO (8-bit write), followed by two
8-bit reads from the A/D FIFO. Ignore the data obtained in the read.
6. Start and service the data acquisition operation.
To start the data acquisition operation, set the SWTRIG bit in Command Register 2. This
enables Counter A0 to start counting.
Once the data acquisition operation is started, the operation must be serviced by reading the
A/D FIFO Register every time an A/D conversion result becomes available. To do this,
perform the following sequence until the desired number of conversion results have been
read:
a. Read the Status Register (8-bit read).
b. If the DAVAIL bit is set (bit 0), then read the A/D FIFO Register to obtain the result.
DMA or interrupts can also be used to service the data acquisition operation. These topics are
discussed in the A/D Interrupt Programming and Programming DMA Operation sections later in
this appendix.
Two error conditions may occur during a data acquisition operation: an overflow error or an
overrun error. These error conditions are reported through the Status Register and should be
checked every time the Status Register is read to check the DAVAIL bit.
An overflow condition occurs if more than 16 A/D conversions have been stored in the A/D
FIFO without the A/D FIFO being read; that is, the A/D FIFO is full and cannot accept any more
data. This condition occurs if the software loop reading the A/D FIFO Register is not fast
enough to keep up with the A/D conversion rate. When an overflow occurs, at least one A/D
conversion result is lost. An overflow condition has occurred if the OVERFLOW bit in the
Status Register is set.
An overrun condition occurs if a second A/D conversion is initiated before the previous
conversion is finished. This condition may result in one or more missing A/D conversions. This
condition occurs if the sample interval is too small (sample rate is too high). An overrun
condition has occurred if the OVERRUN bit in the Status Register is set. The minimum
recommended sampling interval on the Lab-PC+ is 16
µ
s.
Both the OVERFLOW and OVERRUN bits in the Status Register are cleared by writing to the
A/D Clear Register.