National Instruments Low-Cost Multifunction I/O Board for ISA..., User Manual

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Register-Level Programming Appendix E
Lab-PC+ User Manual E-12 © National Instruments Corporation
Using the EXTCONV* Signal to Initiate A/D Conversions
As mentioned earlier, A/D conversions can be initiated by a falling edge on either OUTA0 or
EXTCONV*. Setting the GATA0 bit low disables conversions from both OUTA0 and
EXTCONV*. Setting the GATA0 bit high enables conversions from both OUTA0 and
EXTCONV*. The GATA0 bit is set low whenever OUTA1 is high or SWTRIG in Command
Register 1 is cleared. If OUTA1 is low, GATA0 can be set high at any time by either setting the
SWTRIG bit or initiating a rising edge on EXTTRIG if the HWTRIG bit in Command Register 1
is set.
Programming Multiple A/D Conversions Using
External Timing
A data acquisition operation using the external timing signals EXTCONV* or EXTTRIG can be
in either controlled acquisition mode or freerun acquisition mode. In controlled acquisition
mode, Counter A1 shuts off A/D conversions after the programmed count expires. In freerun
acquisition mode, A/D conversions are disabled under software control.
Programming in Controlled Acquisition Mode
Posttrigger Mode
The following programming steps are required for a data acquisition operation in controlled
acquisition mode using EXTCONV*. In the following programming sequence, EXTTRIG is
used as a posttrigger signal; that is, data acquisition is not started until a rising edge is detected
on the EXTTRIG input.
1. Disable EXTCONV* and EXTTRIG input.
The EXTCONV* bit can be disabled by setting the GATA0 bit low. The GATA0 bit is low
whenever OUTA1 is high, regardless of the settings for the SWTRIG or HWTRIG bits in
Command Register 1 or the EXTTRIG signal. Writing 78 (hex) to the Counter A Mode
Register sets OUTA1 high. This write disables EXTCONV* and EXTTRIG input; that is,
any transitions on these two inputs are ignored.
2. Select analog input channel and gain and select posttrigger mode.
The analog input channel and gain are selected by writing to Command Register 1. The
SCANEN bit must be cleared for data acquisition operations on a single channel. See the bit
description for Command Register 1 earlier in this chapter for gain and analog input channel
bit descriptions. To use posttrigger mode, the PRETRIG bit and SWTRIG bit in
Command Register 2 must be cleared.