National Instruments Low-Cost Multifunction I/O Board for ISA... User Manual Download

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Register Map and Descriptions

Appendix D

Lab-PC+ User Manual

D-30

© National Instruments Corporation

Counter B1 Data Register

The Counter B1 Data Register is used for loading and reading back the contents of 8253(B)
Counter 1.

Address:

Base a 19 (hex)

Type:

Read-and-write

Word Size:

8-bit

Bit Map:

Bit

Name

Description

7-0

D<7..0>

8-bit Counter B1 contents.

Summary of Contents for Low-Cost Multifunction I/O Board for ISA...

Page 2: ...02 757 00 20 Canada Ontario 519 622 9310 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Italy 02 413091 Japan 03 547...

Page 3: ...ny damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAI...

Page 4: ...or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel an...

Page 5: ...Level Programming 1 3 Optional Equipment 1 4 Unpacking 1 4 Chapter 2 Configuration and Installation 2 1 Board Configuration 2 1 PC Bus Interface 2 1 Base I O Address Selection 2 3 DMA Channel Selectio...

Page 6: ...Sources NRSE Configuration 3 11 Common Mode Signal Rejection Considerations 3 12 Analog Output Signal Connections 3 12 Digital I O Signal Connections 3 13 Port C Pin Connections 3 15 Timing Specificat...

Page 7: ...5 4 Unipolar Input Calibration Procedure 5 5 Analog Output Calibration 5 6 Board Configuration 5 6 Bipolar Output Calibration Procedure 5 6 Unipolar Output Calibration Procedure 5 8 Appendix A Specifi...

Page 8: ...ions for Floating Signal Sources 3 11 Figure 3 6 Single Ended Input Connections for Grounded Signal Sources 3 12 Figure 3 7 Analog Output Signal Connections 3 13 Figure 3 8 Digital I O Connections 3 1...

Page 9: ...tling Time Versus Gain 4 7 Table 4 2 Lab PC Maximum Recommended Data Acquisition Rates 4 8 Table 4 3 Bipolar Analog Input Signal Range Versus Gain 4 8 Table 4 4 Unipolar Analog Input Signal Range Vers...

Page 10: ...tional overview of the Lab PC and explains the operation of each functional unit making up the Lab PC This chapter also explains the basic operation of the Lab PC circuitry Chapter 5 Calibration discu...

Page 11: ...tion to a key concept This text denotes text for which you supply the appropriate word or value such as in Windows 3 x italic monospace Italic text in this font denotes that you must supply the approp...

Page 12: ...Software documentation Examples of software documentation you may have are the LabVIEW and LabWindows CVI documentation sets and the NI DAQ documentation After you set up your hardware system use eit...

Page 13: ...logging The 12 bit ADC is useful in high resolution applications such as chromatography temperature measurement and DC voltage measurement The analog output channels can be used to generate experimen...

Page 14: ...es of functions for using LabWindows CVI with National Instruments DAQ hardware is included with the NI DAQ software kit The LabWindows CVI Data Acquisition libraries are functionally equivalent to th...

Page 15: ...station NI DAQ Driver Software DAQ or SCXI Hardware Personal Computer or Workstation Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware You can use your Lab PC bo...

Page 16: ...and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold and relays For more specific information about these products refer to your National Instruments catalog...

Page 17: ...or diagram in Figure 2 1 shows the Lab PC jumper settings Jumpers W3 and W4 configure the analog input circuitry Jumpers W1 and W2 configure the analog output circuitry Jumpers W6 and W5 select the DM...

Page 18: ...er 2 Lab PC User Manual 2 2 National Instruments Corporation 1 2 3 4 7 8 9 5 6 13 12 11 10 1 Assembly Number 5 W2 8 Serial Number 11 W6 2 Spare Fuse 6 W3 9 J1 12 W5 3 U1 7 W4 10 Fuse 13 Product Name 4...

Page 19: ...y National Instruments software packages for use with the Lab PC The Lab PC uses the base I O address space hex 260 through 27F with the factory setting Note Verify that this space is not already used...

Page 20: ...witch Settings The five least significant bits of the address A4 through A0 are decoded by the Lab PC to select the appropriate Lab PC register To change the base I O address remove the plastic cover...

Page 21: ...11F 0 1 0 0 1 120 120 13F 0 1 0 1 0 140 140 15F 0 1 0 1 1 160 160 17F 0 1 1 0 0 180 180 19F 0 1 1 0 1 1A0 1A0 1BF 0 1 1 1 0 1C0 1C0 1DF 0 1 1 1 1 1E0 1E0 1FF 1 0 0 0 0 200 200 21F 1 0 0 0 1 220 220 23...

Page 22: ...es not use and cannot be configured to use the 16 bit DMA channels on the PC AT I O channel Each DMA channel consists of two signal lines as shown in Table 2 3 Table 2 3 DMA Channels for the Lab PC DM...

Page 23: ...line The Lab PC can share interrupt lines with other devices by using a tristate driver to drive its selected interrupt line The Lab PC hardware supports interrupt lines IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 and I...

Page 24: ...asserting an interrupt line on the PC I O channel IRQ W5 3 4 5 6 7 9 Figure 2 6 Interrupt Jumper Setting for Disabling Interrupts Analog I O Configuration The Lab PC is shipped from the factory with t...

Page 25: ...le ended RSE factory setting Nonreferenced single ended NRSE Differential DIFF W4 A B W4 B C W4 B C Analog Output Configuration Two ranges are available for the analog outputs bipolar 5 V and unipolar...

Page 26: ...U Figure 2 8 Unipolar Output Jumper Configuration Analog Input Configuration You can select different analog input configurations by using the jumper and register bit software settings as shown in Ta...

Page 27: ...he negative input of the instrumentation amplifier referenced to analog ground While reading the following paragraphs you may find it helpful to refer to Analog Input Signal Connections in Chapter 3 S...

Page 28: ...tial amplifier is tied to analog ground This configuration is useful when measuring floating signal sources See Types of Signal Sources in Chapter 3 Signal Connections With this input configuration th...

Page 29: ...ollowing jumper W4 B C Jumper is in standby position and negative input of instrumentation amplifier is tied to multiplexed output This configuration is shown in Figure 2 11 W4 A B C RSE NRSE DIFF Fig...

Page 30: ...election You can select the unipolar 0 to 10 V input configuration by setting the following jumper Analog Input W3 B C This configuration is shown in Figure 2 13 A B C W3 B U Figure 2 13 Unipolar Inpu...

Page 31: ...nsion slot cover on the back panel of the computer 4 Insert the Lab PC into an 8 bit or a 16 bit slot 5 Screw the mounting bracket of the Lab PC to the back panel rail of the computer 6 Check the inst...

Page 32: ...C I O connector This connector is located on the back panel of the Lab PC board and is accessible at the rear of the PC after the board has been properly installed Warning Connections that exceed any...

Page 33: ...PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 DGND DAC1 OUT AGND ACH6 ACH4 ACH2 ACH5 AISENSE AIGND ACH7 PC4 PC5 PC6 PC7 EXTTRIG OUTB0 EXTCONV 5 V CLKB2 GA TB2 OUTB2 CCLKB1 GA TB1 COUTB1 GA TB0 DGND DAC0 OUT AC...

Page 34: ...A PA7 is the MSB PA0 the LSB 22 29 PB0 through PB7 Bidirectional data lines for Port B PB7 is the MSB PB0 the LSB 30 37 PC0 through PC7 Bidirectional data lines for Port C PC7 is the MSB PC0 the LSB 3...

Page 35: ...nges and maximum ratings apply to inputs ACH 0 7 Input signal range Bipolar input 5 gain V Unipolar input 0 to 10 gain V Maximum input voltage rating 45 V powered on or off Exceeding the input signal...

Page 36: ...s All signals must be referenced to ground either at the source device or at the Lab PC If you have a floating source you must use a ground referenced input connection at the Lab PC If you have a grou...

Page 37: ...te this ground potential difference from the measured signal Input Configurations The Lab PC can be configured for one of three input modes NRSE RSE or DIFF The following sections discuss the use of s...

Page 38: ...als to the Lab PC are greater than 15 ft Any of the input signals requires a separate ground reference point or return signal The signal leads travel through noisy environments Differential signal con...

Page 39: ...ifferential Input Connections for Grounded Signal Sources With this type of connection the instrumentation amplifier rejects both the common mode noise in the signal and the ground potential differenc...

Page 40: ...ate a return path to ground for the bias currents of the instrumentation amplifier If a return path is not provided the instrumentation amplifier bias currents charge up stray capacitances resulting i...

Page 41: ...eference signal at the source If any of the preceding criteria are not met using DIFF input configuration is recommended You can jumper configure the Lab PC for two different types of single ended con...

Page 42: ...al local ground reference is connected to the negative input of the Lab PC instrumentation amplifier The ground point of the signal should therefore be connected to the AISENSE pin Any potential diffe...

Page 43: ...instrumentation amplifier can reject common mode noise pickup in the leads connecting the signal sources to the Lab PC The common mode input range of the Lab PC instrumentation amplifier is defined a...

Page 44: ...g Output Channels Lab PC Board DAC1 OUT AGND 11 12 VOUT 1 VOUT 0 Load Load Figure 3 7 Analog Output Signal Connections Digital I O Signal Connections Pins 13 through 37 of the I O connector are digita...

Page 45: ...ines Absolute maximum voltage input rating 5 5 V with respect to DGND 0 5 V with respect to DGND Logical Inputs and Outputs Digital I O lines Minimum Maximum Input logic low voltage 0 3 V 0 8 V Input...

Page 46: ...nd sensing external device states such as the switch in Figure 3 8 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 3 8 Port C Pin C...

Page 47: ...ut transfers The handshaking lines OBF and ACK are used to synchronize output transfers The following signals are used in the timing diagrams shown later in this chapter Name Type Description STB Inpu...

Page 48: ...the 8255A is requesting service during a data transfer The appropriate interrupt enable signals must be set to generate this signal RD Internal Read signal This signal is the read signal generated fr...

Page 49: ...cations for an input transfer in Mode 1 are as follows DATA RD INTR IBF STB T1 T2 T4 T7 T6 T3 T5 Name Description Minimum Maximum T1 STB pulse width 500 T2 STB 0 to IBF 1 300 T3 Data before STB 1 0 T4...

Page 50: ...timing specifications for an output transfer in Mode 1 are as follows WR OBF INTR ACK DATA T1 T2 T3 T4 T5 T6 Name Description Minimum Maximum T1 WR 0 to INTR 0 450 T2 WR 1 to output 350 T3 WR 1 to OBF...

Page 51: ...e as follows T1 T6 T7 T3 T4 T10 T2 T5 T8 T9 WR OBF INTR ACK STB IBF RD DATA Name Description Minimum Maximum T1 WR 1 to OBF 0 650 T2 Data before STB 1 0 T3 STB pulse width 500 T4 STB 0 to IBF 1 300 T5...

Page 52: ...r Timer referred to as A1 is used as a sample counter in conjunction with Counter 0 for data acquisition These counters are not available for general use In addition to counter A0 EXTCONV can be used...

Page 53: ...ow a controlled acquisition mode data acquisition sequence that is Sample Counter A1 disables further A D conversions after the programmed count 3 in the examples shown in Figures 3 10 and 3 11 expire...

Page 54: ...ws a pretrigger data acquisition timing sequence tw 50 nsec minimum EXTTRIG EXTCONV CONVERT Sample Counter V IH V IL 4 tw tw 3 2 1 0 Figure 3 12 Pretrigger Data Acquisition Timing Because both pretrig...

Page 55: ...igure 3 14 illustrates a timing sequence where EXTUPDATE is being used to generate an interrupt EXTUPDATE CNTINT TMRINTCLR Figure 3 14 EXTUPDATE Signal Timing for Generating Interrupts The following r...

Page 56: ...to determine the number of edges that have occurred Counter operation can be gated on and off during event counting Figure 3 15 shows connections for a typical event counting operation where a switch...

Page 57: ...en equals the count value divided by the gate period Figure 3 16 shows the connections for a frequency measurement application You can also use a second counter to generate the gate signal in this app...

Page 58: ...output logic high voltage 3 7 V minimum VOL output logic low voltage 0 45 V maximum IOH output source current at VOH 1 mA maximum IOL output sink current at VOL 4 mA maximum tsc tpwh tpwl tgsu tgh tg...

Page 59: ...ble This section contains information and guidelines for designing custom cables The Lab PC I O connector is a 50 pin male ribbon cable header The manufacturer part numbers used by National Instrument...

Page 60: ...ion of the Lab PC circuitry Functional Overview The block diagram in Figure 4 1 shows a functional overview of the Lab PC board Data Address 12 Bit D A 12 Bit D A 1 MHz Timebase 2 MHz Timebase Control...

Page 61: ...some of the timing I O circuitry The internal data and control buses interconnect the components The theory of operation for each of these components is explained in the remainder of this chapter The...

Page 62: ...SA9 to generate the board enable signal and uses lines SA0 through SA4 plus timing signals to generate the onboard register select signals and read write signals The data buffers control the directio...

Page 63: ...ta Acquisition Circuitry The Lab PC provides eight channels of analog input with software programmable gain and 12 bit A D conversion Using the timing circuitry the Lab PC can also automatically time...

Page 64: ...rsion is complete the value is saved in the A D FIFO for later reading and the ADC is free to start a new conversion Secondly the A D FIFO can collect up to 512 A D conversion values before any inform...

Page 65: ...As stated in Appendix E Register Level Programming only Counter A0 is required for data acquisition operations in freerun acquisition mode The software must keep track of the number of conversions tha...

Page 66: ...curacy will not be achieved The settling time is a function of the gain selected The Lab PC data acquisition timing circuitry detects when data acquisition rates are high enough to cause A D conversio...

Page 67: ...hat voltage levels on all the channels included in the scan sequence are within range for the given gain and are driven by low impedance sources The signal ranges for the possible gains are shown in T...

Page 68: ...nalog output channel contains a 12 bit DAC The DAC in each analog output channel generates a voltage proportional to the input Vref multiplied by the digital code loaded into the DAC Each DAC can be l...

Page 69: ...s designed around an 8255A integrated circuit Figure 4 5 shows a block diagram of the digital I O circuitry The 8255A is a general purpose PPI containing 24 programmable I O pins These pins represent...

Page 70: ...h digital I O line When the ports are not enabled the digital I O lines act as high impedance inputs Timing I O Circuitry The Lab PC uses two 8253 Counter Timer integrated circuits for data acquisitio...

Page 71: ...UX CTR RD CTR WR Data 8 PC I O Channel 8253 Counter Timer Group B OUTB0 OUTB2 GATEB2 CLKB2 GATEB1 Scan Interval General Purpose Counter CLKB1 OUTB1 GATEB0 Timebase Extension General Purpose Counter CL...

Page 72: ...CLK pin of Counter B1 is driven by the same signal that is driving CLKA0 The OUTB1 pin on the I O connector initiates scan sequences that are separated by a programmable scan interval time The timebas...

Page 73: ...4 8 Single Channel Interval Timing The 16 bit counters in the 8253 can be diagrammed as shown in Figure 4 9 CLK GATE OUT Counter Figure 4 9 Counter Block Diagram Each counter has a CLK input pin a GA...

Page 74: ...you should calibrate the Lab PC so that its measurement accuracy is within 0 012 of its input range 0 5 LSB According to standard practice the equipment used to calibrate the Lab PC should be 10 time...

Page 75: ...3 R3 5 R5 7 R7 2 R2 4 R4 6 R6 Figure 5 1 Calibration Trimpot Location Diagram The following trimpots are used to calibrate the analog input circuitry R7 Input offset trim analog input R6 Output offse...

Page 76: ...correction to the readings at gains higher than one by subtracting the offset errors With this method you can use the board at all available gain levels without recalibrating the input The maximum of...

Page 77: ...e range 5 to 5 V then complete the following procedure in the order given This procedure assumes that ADC readings are in the range 2 048 to 2 047 that is the TWOSADC bit in Command Register 1 is set...

Page 78: ...ar Input Calibration Procedure If your board is configured for unipolar input which has an input range of 0 to 10 V then complete the following steps in sequence This procedure assumes that ADC readin...

Page 79: ...offsets contributed by each component in the circuitry This error appears as a voltage difference between the desired voltage and the actual output voltage generated and is independent of the D A set...

Page 80: ...b Set the analog output channel to 5 V by writing 2 048 to the DAC c Adjust trimpot R4 until the output voltage read is 5 V 2 Adjust the Analog Output Gain Adjust the analog output gain by measuring t...

Page 81: ...ith the DAC set at positive full scale 4 095 This output voltage should be V fs 0 5 LSB For unipolar output V fs 9 99756 V and 0 5 LSB 1 22 mV For analog output Channel 0 a Connect the voltmeter betwe...

Page 82: ...V 0 to 5 V 5 1 V 0 to 2 V 10 0 5 V 0 to 1 V 20 0 25 V 0 to 0 5 V 50 0 1 V 0 to 0 2 V 100 0 05 V 0 to 0 1 V Input coupling DC Overvoltage protection 45 V powered on 45 V powered off Inputs protected A...

Page 83: ...at 60 Hz 1 100 75 dB 105 dB Dynamic Characteristics Bandwidth 3 dB 400 kHz for gain 1 40 kHz for gain 100 Settling time to full scale step Gain Accuracy 0 2 LSB 10 20 50 100 14 s 20 s 33 s System nois...

Page 84: ...hin 1 2 LSB of the ideal one of its edges may be well beyond 1 LSB thus the ADC would have a relative accuracy of that amount National Instruments tests its boards to ensure that they meet all three l...

Page 85: ...upling DC Output impedance 0 2 max Current drive 2 mA max Protection Short to AGND Power on state 0 V for 5 V range 5 V for 0 to 10 V range Dynamic Characteristics Settling time to FSR for 10 V step 5...

Page 86: ...Level Min Max Input low voltage Input high voltage Input low current Vin 0 8 V Input high current Vin 2 2 V 0 3 V 2 2 V 0 8 V 5 3 V 1 0 A 1 0 A Output low voltage Iout 2 5 mA Output high voltage Iout...

Page 87: ...1 mA 3 7 V 0 45 V Triggers Digital Trigger Compatibility TTL Response Rising edge Pulse width 250 ns Bus Interface Slave Power Requirements from PC 5 VDC 10 180 mA 12 VDC 80 mA 12 VDC 450 mA Power av...

Page 88: ...contains the manufacturer data sheet for the OKI 82C53 System Timing Controller integrated circuit OKI Semiconductor This circuit is used on the Lab PC Copyright OKI Semiconductor 1991 Reprinted with...

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Page 100: ...ains the manufacturer data sheet for the OKI 82C55A Programmable Peripheral Interface integrated circuit OKI Semiconductor This circuit is used on the Lab PC Copyright OKI Semiconductor 1991 Reprinted...

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Page 117: ...re package such as NI DAQ NI DSP LabVIEW or LabWindows CVI with your Lab PC you need not read this appendix Refer to your software documentation for programming information Register Map The register m...

Page 118: ...Low Byte Register 06 Write only 8 bit DAC1 High Byte Register 07 Write only 8 bit 8253 Counter Timer Register Group A Counter A0 Data Register 14 Read and write 8 bit Counter A1 Data Register 15 Read...

Page 119: ...scription Format The remainder of this register description chapter discusses each of the Lab PC registers in the order shown in Table D 1 Each register group is introduced followed by a detailed bit...

Page 120: ...the A D and D A circuitry Command Register 3 enables or disables the interrupt and DMA operations Command Register 4 is used to select the analog input mode and also allows certain analog input conve...

Page 121: ...are sampled alternately If this bit is cleared a single analog channel specified by MA 2 0 is sampled during the entire data acquisition operation See Programming Multiple A D Conversions with Channel...

Page 122: ...0 2 2 3 4 5 011 3 2 3 6 7 100 4 4 5 0 1 101 5 4 5 2 3 110 6 6 7 4 5 111 7 6 7 6 7 In single ended mode RSE or NRSE if SCANEN is set analog channels MA 2 0 through 0 are sampled alternatively If SCANEN...

Page 123: ...status of the GATE 0 input on the counter timer chip Counter Group A This bit can be used as a busy indicator for data acquisition operations because conversions are enabled as long as GATE 0 is high...

Page 124: ...ed This bit is set if a convert command is issued to the ADC while the last conversion is still in progress 0 DAVAIL This bit indicates whether conversion output is available If this bit is set the AD...

Page 125: ...bit selects the binary coding scheme used for the DAC1 data If this bit is set a two s complement binary coding scheme is used for interpreting the 12 bit data Two s complement is useful if a bipolar...

Page 126: ...red the Counter A0 is disabled except when the HWTRIG mode is used 1 HWTRIG Setting this bit allows the external EXTTRIG signal to start a data acquisition operation that is controlled by Counter A0 a...

Page 127: ...tatus Register The interrupt is serviced by writing to the A D Clear Register If ERRINTEN is cleared no error interrupts are generated 3 CNTINTEN This bit enables the Counter A2 output or the EXTUPDAT...

Page 128: ...ready to transfer data and an interrupt request is set via PC3 or PC0 of 8255A See Appendix C OKI 82C55A Data Sheet for details If DIOINTEN is cleared the interrupts from PC3 or PC0 are disabled 0 DM...

Page 129: ...is cleared on board reset 3 SE __ D This bit along with jumper W4 selects the analog input mode of the Lab PC When clear it selects the single ended mode In this case multiplexer 1 selects Channels 0...

Page 130: ...than disconnect the output of Counter B1 from the I O Connector if INTSCAN is clear always clear EOIRCV This bit is cleared on reset 0 INTSCAN This bit selects the DAQ mode When you set this bit the...

Page 131: ...d to read the FIFO Reading the FIFO Register returns stored A D conversion results Writing to the Start Convert Register initiates an A D conversion Writing to the A D Clear Register clears the data a...

Page 132: ...he A D FIFO Register can be read to retrieve a value If the DAVAIL bit is cleared the A D FIFO is empty in which case reading the A D FIFO Register returns meaningless information The values returned...

Page 133: ...s Low Byte 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description High Byte 7 0 D 15 8 These bits contain the high byte of the 16 bit sign extended two s complement result of a 12 bit A D conver...

Page 134: ...the FIFO and loads the last conversion value into the FIFO All error bits in the Status Register are cleared as well Notice that the FIFO contains one data word after reset so two consecutive FIFO re...

Page 135: ...rd Size 8 bit Bit Map Not applicable no bits used Note A D conversions can be initiated in one of two ways by writing to the Start Convert Register or by detecting an active low signal on either the C...

Page 136: ...ents Corporation DMATC Interrupt Clear Register Writing to the DMA Terminal Count DMATC Clear Register clears the interrupt request asserted when a DMA terminal count pulse is detected Address Base ad...

Page 137: ...aking up the Analog Output Register Group are used for loading the two 12 bit DACs in the two analog output channels DAC0 controls analog output Channel 0 DAC1 controls analog output Channel 1 These D...

Page 138: ...d when an active low pulse occurs on the output of Counter A2 or on the EXTUPDATE line on the I O connector Address Base address 04 hex Load DAC0 low byte Base address 05 hex Load DAC0 high byte Base...

Page 139: ...three counters of Group A control onboard data acquisition timing and waveform generation The three counters of Group B are available for general purpose timing functions Each 8253 has three independe...

Page 140: ...tion Counter A0 Data Register The Counter A0 Data Register is used for loading and reading back contents of 8253 A Counter 0 Address Base address 14 hex Type Read and write Word Size 8 bit Bit Map 7 6...

Page 141: ...nual Counter A1 Data Register The Counter A1 Data Register is used for loading and reading back contents of 8253 A Counter 1 Address Base address 15 hex Type Read and write Word Size 8 bit Bit Map 7 6...

Page 142: ...ion Counter A2 Data Register The Counter A2 Data Register is used for loading and reading back contents of 8253 A Counter A2 Address Base address 16 hex Type Read and write Word Size 8 bit Bit Map 7 6...

Page 143: ...he Counter A Mode Register selects the counter involved its read load mode its operation mode that is any of the 8253 s six operation modes and the counting mode binary or BCD counting The Counter A M...

Page 144: ...ation Timer Interrupt Clear Register Writing to the Timer Interrupt Clear Register clears the interrupt request asserted when a low pulse is detected on the Counter A2 output or on EXTUPDATE line Addr...

Page 145: ...al Counter B0 Data Register The Counter B0 Data Register is used for loading and reading back the contents of 8253 B Counter 0 Address Base address 18 hex Type Read and write Word Size 8 bit Bit Map 7...

Page 146: ...on Counter B1 Data Register The Counter B1 Data Register is used for loading and reading back the contents of 8253 B Counter 1 Address Base address 19 hex Type Read and write Word Size 8 bit Bit Map 7...

Page 147: ...al Counter B2 Data Register The Counter B2 Data Register is used for loading and reading back the contents of 8253 B Counter 2 Address Base address 1A hex Type Read and write Word Size 8 bit Bit Map 7...

Page 148: ...ter B Mode Register selects the counter involved its read load mode its operation mode that is any of the 8253 s six operation modes and the counting mode binary or BCD counting The Counter Mode Regis...

Page 149: ...integrated circuit The 8255A is a general purpose peripheral interface containing 24 programmable I O pins These pins represent the three 8 bit I O ports A B and C of the 8255A These ports can be prog...

Page 150: ...A is configured for output the Port A Register can be written to in order to control the eight digital I O lines constituting Port A See Programming the Digital I O Circuitry in Appendix E Register Le...

Page 151: ...B is configured for output the Port B Register can be written to in order to control the eight digital I O lines constituting Port B See Programming the Digital I O Circuitry in Appendix E Register Le...

Page 152: ...handshaking latched mode If either Port A or Port B is configured for latched I O some of the bits in Port C are used for handshaking signals See Programming the Digital I O Circuitry in Appendix E Re...

Page 153: ...tputs as well as selecting simple mode basic I O or handshaking mode strobed I O for transfers See Programming the Digital I O Circuitry in Appendix E Register Level Programming for a description of t...

Page 154: ...val Counter Data Register and the Interval Counter Strobe Register The Interval Counter Data Register is loaded with the count Writing to the Interval Counter Strobe Register loads this count into the...

Page 155: ...samples of a single channel that will be acquired between intervals See Programming Multiple A D Conversions in Single Channel Interval Acquisition Mode in Appendix E Register Level Programming for a...

Page 156: ...the Interval Counter Data Register into the Interval Counter This action arms the Interval Counter which then decrements with each conversion pulse Address Base address 1F hex Type Write only Word Si...

Page 157: ...pecific register bits should be set or cleared without changing the current state of the remaining bits in the register However writing to these registers affects all register bits simultaneously You...

Page 158: ...wing state Counter A0 output is high Counter A1 output is high This disables EXTCONV All interrupts are disabled EXTTRIG is disabled The timebase for Counter A0 is the onboard 1 MHz source Analog inpu...

Page 159: ...e EXTCONV line To enable Counter A0 and the EXTCONV the SWTRIG bit in Command Register 2 must be set and OUTA1 must be low Alternatively a conversion can be performed by writing to the Start Convert R...

Page 160: ...ion result can be returned from the A D FIFO as a 16 bit two s complement or straight binary value by setting or clearing the TWOSCMP bit in Command Register 1 If the analog input circuitry is configu...

Page 161: ...red to in this manual as a data acquisition operation Two types of data acquisition operations are available on the Lab PC Controlled acquisition mode Freerun acquisition mode In controlled acquisitio...

Page 162: ...base source for Counter A0 The analog input channel and gain are selected by writing to Command Register 1 The SCANEN bit must be cleared for data acquisition operations on a single channel See the Co...

Page 163: ...e 8 bit write operations All values given are hexadecimal a Write 34 to the Counter A Mode Register select Counter A0 Mode 2 b Write the least significant byte of the sample interval to the Counter A0...

Page 164: ...s the A D FIFO is full and cannot accept any more data This condition occurs if the software loop reading the A D FIFO Register is not fast enough to keep up with the A D conversion rate When an overf...

Page 165: ...nificant byte of the timebase count to the Counter B Data Register c Write the most significant byte of the timebase count to the Counter B Data Register For example programming a timebase of 10 s req...

Page 166: ...he A D FIFO Register to obtain the result DMA or interrupts can also be used to service the data acquisition operation These topics are discussed in the A D Interrupt Programming and Programming DMA O...

Page 167: ...nversion data acquisition operation In this mode referred to as posttriggering the sample interval counter is gated off until a low to high edge is sensed on EXTTRIG No samples are collected until EXT...

Page 168: ...d under software control Programming in Controlled Acquisition Mode Posttrigger Mode The following programming steps are required for a data acquisition operation in controlled acquisition mode using...

Page 169: ...program the counters use the following programming sequence a Write 70 hex to the Counter A Mode Register select Counter A1 Mode 0 This step sets the output of Counter A1 OUTA1 low b Write the least s...

Page 170: ...val is too small sample rate is too high An overrun condition has occurred if the OVERRUN bit in the Status Register is low The minimum recommended sampling interval on the Lab PC is 16 s Both the OVE...

Page 171: ...the A D Clear Register also sets the GATA1 bit low A D conversions are not counted until GATA1 is set high by a rising edge on the EXTTRIG input 4 Program Counter A1 and enable EXTCONV input Counter...

Page 172: ...to check the DAVAIL bit An overflow condition occurs if more than 16 A D conversions have been stored in the A D FIFO without the A D FIFO being read that is the A D FIFO is full and cannot accept any...

Page 173: ...est channel number in the scan sequence the gain and the input polarity to Command Register 1 The SCANEN bit must be cleared during this first write to Command Register 1 2 Write the same configuratio...

Page 174: ...gister If you intend to use Counter B1 to generate your scan interval pulses remember to connect a source to the CLKB1 line on the I O connector 4 Finally take the Analog Configuration Register bit pa...

Page 175: ...g counter All writes are 8 bit write operations All values are hexadecimal a Write 74 to the Counter B Mode Register select Mode 2 b Write the least significant byte of the interval count to the Count...

Page 176: ...e the DMA terminal count interrupt set the DMAEN and TCINTEN bits in Command Register 3 If these bits are set an interrupt is generated and the DMATC bit in the Status Register is set whenever the DMA...

Page 177: ...2 Configuration and Installation Table E 3 shows the output voltage versus digital code for a unipolar analog output configuration Table E 4 shows the voltage versus digital code for a bipolar analog...

Page 178: ...errupts can be used for writing successive values in a sequence to the DAC Data Registers during a waveform generation operation The CNTINTEN bit in Command Register 3 enables and disables Counter A2...

Page 179: ...dual 8 bit ports The following paragraphs include programming information for the Lab PC The three 8 bit ports are divided into two groups Group A and Group B two groups of 12 signals One 8 bit config...

Page 180: ...nibble 1 input 0 output Figure E 1 Control Word Format with Control Word Flag Set to 1 D7 D3 D2 D1 D0 Control Word Flag 0 Bit Set Reset Bit Set Reset 1 set 0 reset Bit Select 000 001 010 111 X X X Fi...

Page 181: ...ode is for simple I O operations for each of the ports No handshaking is required data is simply written to or read from a specified port Mode 0 has the following features Two 8 bit ports A and B and...

Page 182: ...Input Input 10011000 Input Input Output Output 10011001 Input Input Output Input 10011010 Input Input Input Output 10011011 Input Input Input Input 1 Upper nibble of Port C 2 Lower nibble of Port C Pr...

Page 183: ...contains one 8 bit port and one 4 bit control data port The 8 bit port can be either an input port or an output port and the 4 bit port is used for control and status information for the 8 bit port Th...

Page 184: ...tatus for Port A When INTEA is high and IBFA is high this bit is high indicating that an interrupt request is asserted 2 INTEB Interrupt enable bit for Port B Enables interrupts from the 8255A for Por...

Page 185: ...ort B Output The control word written to the Digital Control Register to configure Port A for output in Mode 1 is shown here Bits PC4 and PC5 of Port C can be used as extra input or output lines when...

Page 186: ...t status for Port A When INTEA is high and OBFA is high this bit is high indicating that an interrupt request is asserted 2 INTEB Interrupt enable bit for Port B If this bit is high interrupts are ena...

Page 187: ...t generation and enable disable functions are also available Other features of this mode include the following Used in Group A only Port A and upper nibble of Port C One 8 bit bidirectional port Port...

Page 188: ...buffer full Low indicates that the CPU has written data out to Port A 6 INTE1 Interrupt enable bit for output If this bit is set interrupts are enabled from the 8255A for OBF Controlled by bit set res...

Page 189: ...o Port A Wait for bit 5 of Port C IBFA to be set indicating that data is available in Port A to be read Read data from Port A Single Bit Set Reset Control Words Table E 6 shows the control words for s...

Page 190: ...cuitry Interrupts can be enabled on PC0 PC3 or both PC0 and PC3 by setting the DIOINTEN bit in Command Register 3 See the Command Register 3 description earlier in this chapter for corresponding bit p...

Page 191: ...fice You may fax questions to us at any time Corporate Headquarters 512 795 8248 Technical support fax 512 794 5678 Branch Offices Phone Number Fax Number Australia 03 9 879 9422 03 9 879 9179 Austria...

Page 192: ...nstruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax Phone Computer b...

Page 193: ...Output Channel 1 Configuration _____________________________________________ Factory Setting Bipolar W2 A B Analog Input Configuration _____________________________________________ Factory Setting Bip...

Page 194: ...Part Number 320502B 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for...

Page 195: ...ge BCD binary coded decimal C Celsius CMOS complementary metallic oxide semiconductor D A digital to analog DAC D A converter dB decibels DC direct current DIFF differential DIP dual inline package DM...

Page 196: ...RSE referenced single ended RTSI Real Time System Integration s seconds SCXI Signal Conditioning eXtensions for Instrumentation bus SDK System Development Kit STC system timing controller TTL transis...

Page 197: ...canning E 18 single channel interval acquisition mode E 19 Counter B2 Data Register D 31 overview D 23 register map D 2 Timer Interrupt Clear Register D 28 8255A Digital I O Register Group D 33 to D 3...

Page 198: ...nal table 3 3 Analog Configuration Register E 18 analog input calibration 5 3 to 5 6 bipolar input procedure 5 4 to 5 5 board configuration 5 4 unipolar input procedure 5 5 to 5 6 voltage values of AD...

Page 199: ...cations A 4 to A 5 dynamic characteristics A 4 explanation A 4 to A 5 output characteristics A 4 stability A 4 transfer characteristics A 4 voltage output A 4 B base I O address selection 2 3 to 2 5 e...

Page 200: ...hannel scanning cycle E 17 circuitry See theory of operation circular buffer E 11 CLK signal See GATE CLK and OUT signals CLKB2 signal table 3 3 CNTINT bit data acquisition timing 3 24 description D 7...

Page 201: ...rolled acquisition mode multiple A D conversions external timing E 12 to E 16 posttrigger mode E 12 to E 14 pretrigger mode E 14 to E 16 overview E 5 programming steps E 6 to E 8 single input channel...

Page 202: ...e 4 8 unipolar analog input signal range versus gain table 4 8 multiple channel scanned data acquisition 4 6 to 4 7 single channel data acquisition 4 6 data acquisition timing connections EXTCONV sign...

Page 203: ...D 7 DMA request generation E 20 DMATC Interrupt Clear Register description D 20 DMA request generation E 20 documentation conventions used in manual xii National Instruments documentation xiii organiz...

Page 204: ...block diagram 4 14 event counting application figure 3 25 frequency measurement application figure 3 26 general purpose timing 3 24 to 3 27 timing requirements figure 3 27 general purpose timing conne...

Page 205: ...2 8 factory setting of IRQ5 figure 2 7 interrupts control circuitry 4 3 generating with EXTUPDATE signal figure 3 24 types of interrupts 4 3 to 4 4 Interval Counter Register Group D 38 to D 40 Interva...

Page 206: ...status word bit definitions E 28 programming example E 29 timing 3 18 Mode 1 output E 29 to E 31 control words E 29 Port C pin assignments E 30 Port C status word bit definitions E 30 programming exam...

Page 207: ...interrupt programming E 20 description D 7 OVERRUN bit A D FIFO overrun condition clearing the analog input circuitry E 5 controlled acquisition programming E 8 posttrigger mode E 14 pretrigger mode E...

Page 208: ...nments E 30 Port C status word bit definitions E 30 programming example E 31 Mode 2 operation E 31 to E 34 control words E 31 to E 32 Port C pin assignments E 33 Port C status word bit definitions E 3...

Page 209: ...15 Mode 1 input timing 3 18 Mode 1 output timing 3 19 Mode 2 bidirectional timing 3 20 Port C pin connections 3 15 to 3 16 timing specifications 3 16 to 3 17 input configurations 3 6 to 3 28 common mo...

Page 210: ...per and switch settings SWTRIG bit controlled acquisition mode E 7 posttrigger mode E 12 pretrigger mode E 16 description D 10 freerun acquisition mode E 10 multiple A D conversions using EXTTRIG sign...

Page 211: ...nel interval timing figure 4 14 two channel interval scanning timing figure 4 13 timing I O specifications A 5 to A 6 trigger specifications A 6 two channel interval scanning timing figure 4 13 TWOSCM...

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