Register Bit Descriptions
Chapter 4
GPIB-1014 User Manual
4-22
© National Instruments Corporation
Address Mode Register (ADMR)
VMEbus Address:
Base A 119 (hex)
Attributes:
Write Only, Internal to TLC
W
7
6
5
4
3
2
1
ton
1on
TRM1
TRM0
0
0
ADM1
ADM0
0
Bit
Mnemonic
Description
7w
ton
Talk Only Bit
By setting ton programs, the TLC becomes a GPIB Talker. If ton is
set, the lon, ADM1, and ADM0 bits must be cleared. This method
must be used in place of the addressing method when the TLC will be
only a Talker.
Note:
Clearing ton does not by itself take the TLC out of GPIB
Talker Active State (TACS). It is also necessary to execute the
Chip Reset or Immediate Execute pon auxiliary command.
6w
lon
Listen Only Bit
By setting lon programs, the TLC becomes a GPIB Listener. If lon is
set, ton, ADM1, and ADM0 must be cleared.
Note:
Clearing lon does not, by itself, take the TLC out of GPIB
Listener Active State (LACS). It is also necessary to execute
the Chip Reset or Immediate Execute pon auxiliary command.
5-4w
TRM[1-0]
Transmit/Receive Mode Bits 1 through 0
TRM1 and TRM0 control the function of the TLC T/R2 and T/R3
output pins.
For proper operation, set both TRM1 and TRM0 to 1. These are set to
configure the
µ
PD7210 to match the transceivers chosen for hardware
implementation of the GPIB interface.
3-2w
0
Reserved Bits
Write zeros to these bits.
