Chapter 4
Register Descriptions
© National Instruments Corporation
4-37
GPIB-1014 User Manual
Auxiliary Register A (AUXRA)
VMEbus Address:
Base A 11B (hex)
AUXMR Control Code: 100 (Binary, Bits 7 - 5)
Attributes:
Write Only, Internal to TLC
Accessed through AUXMR
4
3
2
1
0
W
BIN
XEOS
REOS
HLDE
HLDA
Writing to Auxiliary Register A (AUXRA) is done via the AUXMR. Writing the binary value
100 into the Control Code (CNT[2-0]) and a bit pattern into the Command Code (COM[4-0])
portion of the AUXMR causes the Command Code to be written to AUXRA. When the data is
written to AUXRA, the bits are denoted by the mnemonics shown in the register bit map above.
This 5-bit code controls the data transfer messages Holdoff and EOS/END.
Bit
Mnemonic
Description
4w
BIN
Binary Bit
The BIN bit selects the length of the EOS message. Setting BIN
causes the End Of String Register (EOSR) to be treated as a full 8-bit
byte. When BIN=0, the EOSR is treated as a 7-bit register (for ASCII
characters) and only a 7-bit comparison is done with the data on the
GPIB.
3w
XEOS
Transmit END with EOS Bit
The XEOS bit permits or prohibits automatic transmission of the GPIB
END message at the same time as the EOS message when the TLC is
in Talker Active State (TACS). If XEOS is set and the byte in the
CDOR matches the contents of the EOSR, the EOI line is sent true
along with the data.
2w
REOS
END on EOS Received Bit
The REOS bit permits or prohibits setting the END bit (ISR1[4]r) at
reception of the EOS message when the TLC is in Listener Active
State (LACS). If REOS is set and the byte in the DIR matches the
byte in the EOSR, the END bit (ISR1[4]r) is set.
