Diagnostic and Troubleshooting Test Procedures
Chapter 7
GPIB-1014 User Manual
7-6
© National Instruments Corporation
00A
MTC0 = 0001
one byte
004
DCR0 = A0
005
OCR0 = 82
006
SCR0 = 0
000
CSR0 = FF
040
CSR1 = FF
045
OCR1 = 0
029
MFC0 = 06
00C
MAR0 = daddr
4-byte data address
daddr= 0
clear data location
101
CFG1 = 19
BRG3*, IN, enable ROR feature
11B
AUXMR = 2
TLC Reset
119
ADMR = C0
ton,lon
007
CCR0 = 80
Start channel 0
115
IMR2 = 10
DMA in enable
11B
AUXMR = 0
Immediate execute pon
113
ISR1 = 02?
wait for DI cleared before writing a byte to TLC
Data In Register
111
DIR = 55
send data to TLC, DIR is full, TLC request for a
DMA transfer to put the byte in DIR to memory
000
CSR0 = 81?
DMA channel finished (COC)
040
CSR1 = 02?
GPIB synchronized (PCL)
113
ISR1 = 02?
DIR is empty, DI is cleared
daddr= 55?
verify data has been transferred from TLC to
memory
101
CFG1 = 18
clear GPIB synchronization detecting circuitry, also
to pull PCL1 high
040
CSR1 = 02
clear PCT bit in CSR1
040
CSR1 = 01?
PCT bit cleared, PCL1 high
13. Test DMA transfer (flyby) to GPIB, one byte, memory read, use the Carry Cycle feature.
Addresses 3000 to 300E are used for this test, other locations may be used if required.
3000
data = 0102
two data bytes (01 and 02) to be transferred on
Channel 0
3002
data = 0306
data byte (03) and CC byte (06=SEOI) to be
transferred on Channel 1
3004
data = 0000
define carry cycle array's first entry
3006
data = 3003
4-byte address of carry cycle byte (00003003)
3008
data = 0001
first entry's transfer count (0001)
300A
data = 0000
define carry cycle array's second entry
300C
data = 3002
4-byte address of last data byte (00003002)
300E
data = 0002
second entry's transfer count (0002)
105
CFG2 = 0A
Set LMR and turn LED green
105
CFG2 = 08
Clear LMR
101
CFG1 = 1C
BRG3*, OUT, CC, enable ROR feature
004
DCR0 = A0
044
DCR1 = A0