Chapter 4
Theory of Operation
4-8
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These settling time specifications assume that voltage levels on all the
channels included in the scan sequence are within range and are driven by
low-impedance sources. Signal levels outside the ranges on the channels
included in the scan sequence adversely affect the input settling time.
Similarly, greater settling time may be required for channels driven by
high-impedance signal sources.
Digital I/O Circuitry
The DAQCard-700 has 16 TTL-compatible DIO lines. DIN<0..7> are
digital input lines, and DOUT<0..7> are digital output lines. These lines are
monitored, or driven, by the Digital Input Register and the Digital Output
Register, respectively. Reading the Digital Input Register returns the
current state of DIN<0..7>. Writing the Digital Output Register drives the
new value onto DOUT<0..7>. An external device may drive the EXTINT*
signal to indicate readiness for data transfer. Figure 4-4 shows a diagram of
this circuitry.
Figure 4-4.
Digital I/O Circuitry Block Diagram
PCMCIA
I/O
Channel
I/O RD
I/O WR
Digital
Input
Register
Digital
Output
Register
Status Register
Interrupt
Interface
I/O
Connector
EXTINT*
DIN<0..7>
DOUT<0..7>
8
8
8
8
