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Theory of Operation
Chapter 4
DAQCard-500 User Manual
4-6
© National Instruments Corporation
PC I/O Channel
PCMCIA
I/O Channel
Digital
Output
Register
4
/
4
/
Digital
Input
Register
I/O Connector
4
/
4
/
I/O RD
I/O WR
DIN <0..3>
DOUT<0..3>
Figure 4-4. Digital I/O Circuitry Block Diagram
Timing I/O Circuitry
The DAQCard-500 uses an MSM82C54 counter/timer integrated circuit for data acquisition
timing and for general-purpose timing I/O functions. Counters 1 and 2 of the MSM82C54 are
available for general use, but counter 0 is used internally for data acquisition timing. The gate
signal of counter 1 is internally pulled up and is always active. Figure 4-5 shows a block
diagram of both groups of timing I/O circuitry.