Theory of Operation
Chapter 4
DAQCard-500 User Manual
4-4
© National Instruments Corporation
benefits. First, when an A/D conversion is complete, the value is saved in the A/D FIFO for later
reading, and the ADC is free to start a new conversion. Secondly, the A/D FIFO can collect up
to 16 A/D conversion values before any information is lost, thus giving the software some extra
time (16 times the sample interval) to catch up with the hardware. If more than 16 values are
stored in the A/D FIFO without the A/D FIFO being read from, an error condition called A/D
FIFO overflow occurs and A/D conversion information is lost.
The A/D FIFO generates a signal that indicates when it contains A/D conversion data. The state
of this signal can be read from the Status Register.
The output from the ADC is a two's complement number ranging from -2,048 to 2,047. The
output from the 12-bit ADC is always sign-extended to 16 bits by the board circuitry so that data
values read from the FIFO are 16 bits wide.
Data Acquisition Timing Circuitry
A data acquisition operation refers to the process of obtaining a series of successive A/D
conversions at a carefully timed interval. This interval is called the sample interval. The data
acquisition timing circuitry consists of various clocks and timing signals that perform this timing.
The DAQCard-500 can perform two types of data acquisition—single-channel data acquisition
and multichannel (scanned) data acquisition. Scanned data acquisition uses a counter to
automatically switch between analog input channels during data acquisition.
Data acquisition timing consists of signals that initiate a data acquisition operation and generate
scanning clocks. One of the three counters of the onboard MSM82C54 is reserved for this
purpose.
An A/D conversion can be initiated during data acquisition by a low-to-high transition on the
counter 0 output (OUT0) of the MSM82C54 onboard counter/timer chip on the DAQCard-500,
or by a low-to-high transition on EXTCONV* input.
The sample-interval timer is a 16-bit down counter that uses the onboard 1 MHz clock to
generate sample intervals from 2 µs to 65,535 µs (see Timing I/O Circuitry later in this chapter).
Each time the sample-interval timer reaches zero, it generates a pulse and reloads with the
programmed sample-interval count. This operation continues until the counter is reprogrammed.
Notice that only counter 0 is required for data acquisition operations. The software must track
the number of conversions that have occurred and turn off counter 0 after the required number
has been obtained.
Single-Channel Data Acquisition
During single-channel data acquisition, a control register is set to select the analog input channel
before data acquisition is initiated. This multiplexer setting remains constant during the entire
data acquisition process; therefore, all A/D conversion data is read from a single channel.
