ENV - Set Environment
http://www.motorola.com/computer/literature
5-11
5
ROM Bank A Access Speed (ns) = 80?
This defines the minimum access speed for the Bank A Flash device(s)
in nanoseconds.
ROM Bank B Access Speed (ns) = 70?
This defines the minimum access speed for the Bank B Flash device(s)
in nanoseconds.
DRAM Parity Enable [On-Detection/Always/Never - O/A/N] = O?
Note
This DRAM Parity Enable parameter also applies to enabling
ECC for DRAM.
L2 Cache Parity Enable [On-Detection/Always/Never - O/A/N] = O?
PCI Interrupts Route Control Registers (PIRQ0/1/2/3) = 0A0B0E0F?
Initializes the PIRQx (PCI Interrupts) route control registers in the
PIBC (PCI/ISA bus bridge controller). The ENV parameter is a 32-bit
value that is divided by 4 to yield the values for route control registers
PIRQ0/1/2/3. The default is determined by system type.
LED/Serial Startup Diagnostic Codes
These codes can be displayed at key points in the initialization of the
hardware devices. If the debugger fails to come up to a prompt, the last
code displayed will indicate how far the initialization sequence had
progressed before stalling. The codes are enabled by an ENV
parameter similar to the following:
O
DRAM parity is enabled upon detection. (Default)
A
DRAM parity is always enabled.
N
DRAM parity is never enabled.
O
L2 Cache parity is enabled upon detection. (Default)
A
L2 Cache parity is always enabled.
N
L2 Cache parity is never enabled.
