Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 34. Parallel I/O Ports 34-17
Part V. The Communications Processor Module
34.4.1.5 Port C Interrupt Control Register (PCINT)
Each bit of the port C interrupt control (PCINT) register, shown in Figure 34-15,
corresponds to a port C signal to determine whether that line asserts an interrupt request on
a high-to-low transition or on any transition. PCINT is cleared by reset.
Table 34-16 describes PCINT bits.
34.5 Port D
The 13 port D signals are conÞgured independently as general-purpose I/O signals if the
corresponding port D pin assignment register (PDPAR) is cleared. They are conÞgured as
dedicated on-chip peripheral signals if the corresponding PDPAR bit is set.
The port I/O signal is conÞgured as an input if the corresponding bit in the port D data
direction register (PDDIR) is cleared and as an output if the bit is set. PDPAR and PDDIR
5, 7,
9, 11 CTS x Clear to send
0 PC
x
is a general-purpose interrupt I/O signal. The SCC internal CTS
x
signal is always asserted. If
PCDIR conÞgures this signal as an input, the signal can generate an interrupt to the core, as
controlled by the PCINT bits.
1 PC
x
is connected to the corresponding SCC input as well as being a general-purpose interrupt
signal.
14Ð15 DREQ x Enable DMA request to the CPM. Set DREQ x only if IDMA is being used. Note that the IDMA request
function and the general-purpose interrupt function operate concurrently and independently.
0 PC
x
is a general-purpose interrupt I/O signal. If PCDIR conÞgures this signal as an input, the
signal can generate an interrupt to the core, as controlled by the PCINT bits.
1 As well as being a general-purpose interrupt signal PC
x
becomes an external request to the CPM
for IDMA service. RCCR[DR x M] controls whether IDMA requests are edge- or level-sensitive. The
corresponding PCINT bits still control when a general-purpose interrupt is generated.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ EDM4ÐEDM15
Reset 0
R/W R/W
Addr 0x968
Figure 34-15. Port C Interrupt Control Register (PCINT)
Table 34-16. PCINT Bit Descriptions
Bits Name Description
0Ð3 Ñ Reserved and should be cleared.
4Ð15 EDM n Edge detect mode. The corresponding port C signal asserts an interrupt request.
0 Any edge on PC
x
generates an interrupt request.
1 A falling edge on PC
x
generates an interrupt request.
Table 34-15. PCSO Bit Descriptions (Continued)
Bits Name Description