Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 5. PowerPC Core Register Set 5-11
Part II. PowerPC Microprocessor Module
5.1.3.1 Accessing SPRs
All SPRs are accessed using the mtspr and mfspr instructions, regardless of whether they
are within the processor core. To access registers outside of the core, an internal bus tenure
occurs using the address lines as described in Table 5-11.
Address errors in this tenure cause a software emulation exception.
5.2 Register Initialization at Reset
This section describes how basic registers are set under reset conditions, other register
settings are described in Chapter 8, ÒInstruction and Data Caches,Ó and Chapter 9,
ÒMemory Management Unit (MMU).Ó
A system reset interrupt occurs when a nonmaskable interrupt is generated either by the
software watchdog timer or the assertion of IRQ0. The only registers affected by the system
reset interrupt are MSR, SRR0, and SRR1; no other reset activity occurs. Section 7.1.2.1,
152 00100 11000 CMPE Write: Fetch sync
Read: Sync relative to load/store operations
153 00100 11001 CMPF Write: Fetch sync
Read: Sync relative to load/store operations
154 00100 11010 CMPG Write: Fetch sync
Read: Sync relative to load/store operations
155 00100 11011 CMPH Write: Fetch sync
Read: Sync relative to load/store operations
156 00100 11100 LCTRL1 Write: Fetch sync
Read: Sync relative to load/store operations
157 00100 11101 LCTRL2 Write: Fetch sync
Read: Sync relative to load/store operations
158 00100 11110 ICTRL Fetch sync on write
159 00100 11111 BAR Write: Fetch sync
Read: Sync relative to load/store operations. See
Section 5.1.2.1, ÒDAR, DSISR, and BAR Operation.Ó
630 10011 10110 DPDR Read and Write
Table 5-11. Addresses of SPRs Located Outside of the Core
Address Lines
0Ð17 18Ð22 23Ð27 28Ð31
0...0 SPR[0Ð4] SPR[5Ð9] 0000
Table 5-10. MPC860-Specific Debug-Level SPRs (Continued)
SPR Number
Name Serialize Access
Decimal SPR[5Ð9] SPR[0Ð4]