Motorola MPC564EVB, User Manual

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MPC564EVB User’s Manual 1-7
System Memory
x
32KByte Internal SRAM
x
MPC564
512K byte Internal FLASH Memory (U1)
x
128K x 32bit (512KByte) Synchronous Static RAM (U2), 1M Byte with U3 option.
x
512K x 32bit (2MByte) Synchronous Flash EEPROM (U4)
x
Peripherals 10/100T Ethernet and LCD Port
Each external RAM or Flash memory bank can be configured individually to operate from the
MPC564 chip selects. Caution should be used not to place more than one memory bank on the CS0
chip select and to properly configure the chip select to control the memory devices provided in the
memory bank correctly. Failure to observe precautions may render the external memory bus
inoperable.
The MAP Switch (MAP_SW) connects MPC564 chip selects to the different external memory
banks. If memory access problems occur, the settings of these options and the associated chip
select configurations should be reviewed with some detail. Information to configure the chip
selects and memory is detailed in the following section.
1.2.5.2
Memory Bank Chip Select Configuration
Application software that executes on Reset must configure each memory bank chip select
properly for correct operation. Chip Select Memory Options shows the default memory settings
programmed by the dBUG ROM monitor and may be applied for most user applications:
Table 1-2. Chip Select Memory Options
1.2.5.3 Reset Vector Mapping
After reset, the processor attempts to execute at physical address 0x0000_0100 if the hard reset
configuration word IP bit is cleared to 0 or physical address 0xFFF0_0100 if the hard reset
Memory Bank Reg. Default Value Notes
CS1 = SRAM BR1 0xFFF0_0003 Base Address = 0xFFF0_0000, Port width = 32 bit *Default
CS1 = SRAM, asynchro-
nous access mode OR1 0xFFF0_0000 Memory Range = 0xFFF0_0000 > 0xFFF7_FFFF, wait state
= 0. Note U2 = 512K bytes and will mirror 4x with this set-
ting. Usable range = 0xFFF0_8000 – 0xFFF7_FFFF.
CS0 = FLASH BR0 0x0080_0003 Base address 0x0080_0000, Port width = 32 bit *Default
CS0 = FLASH, asynchro-
nous access mode OR0 0xFFE0_0030 Memory range = 0x0080_0000 > 0x009F_FFFF, wait state
= 3, asynchronous operation 40Mhz clock, 95ns device.
Note U4 = 2M bytes and will mirror 2x with this setting.
Usable range = 0x0080_0000 > 0x008F_FFFF (dBUG mon-
itor is in upper half starting at 0x0090_0000)
CS3 = Peripheral BR3 0x0100_0807 Base address = 0x0100_0000, Port width = 16 bit *Default
External TA* generation provided.
CS3 = Peripheral, asyn-
chronous OR3 0xFFFF_80F0 Memory Range 0x0100_0000 > 0100_7FFF, wait state =
External Terminate (TA*) *Default Note Peripheral memory
map.