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Motorola MC9S12A256 User Manual Download Page 68

MC9S12DT256 Device User Guide —  V03.07

68

2.4.7  VREGEN — On Chip Voltage Regulator Enable

Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be
supplied externally.

V

DDPLL

43

2.5 V

Provides operating voltage and ground for the Phased-Locked

Loop. This allows the supply voltage to the PLL to be
bypassed independently. Internal power and ground
generated by internal regulator.

V

SSPLL

45

0 V

VREGEN

97

5V

Internal Voltage Regulator enable/disable

Mnemonic

Pin Number

Nominal

Voltage

Description

112-pin QFP

Summary of Contents for MC9S12A256

Page 1: ...rola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or ind...

Page 2: ...nable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part DOCUMENT NUMBER 9S12DT256DGV3 D 2 Revision History Version Number Revision Date Effective Date Author Description of Changes V03 00 24 March 2003 Ini...

Page 3: ...MC9S12DT256 Device User Guide 9S12DT256DGV3 D V03 07 3 ...

Page 4: ...MC9S12DT256 Device User Guide 9S12DT256DGV3 D V03 07 4 ...

Page 5: ...L Loop Filter Pin 57 2 3 6 BKGD TAGHI MODC Background Debug Tag High and Mode Pin 57 2 3 7 PAD15 AN15 ETRIG1 Port AD Input Pin of ATD1 57 2 3 8 PAD 14 08 AN 14 08 Port AD Input Pins of ATD1 57 2 3 9 PAD7 AN07 ETRIG0 Port AD Input Pin of ATD0 58 2 3 10 PAD 06 00 AN 06 00 Port AD Input Pins of ATD0 58 2 3 11 PA 7 0 ADDR 15 8 DATA 15 8 Port A I O Pins 58 2 3 12 PB 7 0 ADDR 7 0 DATA 7 0 Port B I O Pin...

Page 6: ...N0 TXCAN4 SCK0 Port M I O Pin 5 63 2 3 37 PM4 RXCAN0 RXCAN4 MOSI0 Port M I O Pin 4 63 2 3 38 PM3 TXCAN1 TXCAN0 SS0 Port M I O Pin 3 63 2 3 39 PM2 RXCAN1 RXCAN0 MISO0 Port M I O Pin 2 63 2 3 40 PM1 TXCAN0 TXB Port M I O Pin 1 64 2 3 41 PM0 RXCAN0 RXB Port M I O Pin 0 64 2 3 42 PP7 KWP7 PWM7 SCK2 Port P I O Pin 7 64 2 3 43 PP6 KWP6 PWM6 SS2 Port P I O Pin 6 64 2 3 44 PP5 KWP5 PWM5 MOSI2 Port P I O P...

Page 7: ... 6 VDDPLL VSSPLL Power Supply Pins for PLL 67 2 4 7 VREGEN On Chip Voltage Regulator Enable 68 Section 3 System Clock Description 3 1 Overview 69 Section 4 Modes of Operation 4 1 Overview 71 4 2 Chip Configuration Summary 71 4 3 Security 72 4 3 1 Securing the Microcontroller 72 4 3 2 Operation of the Secured Microcontroller 72 4 3 3 Unsecuring the Microcontroller 73 4 4 Low Power Modes 73 4 4 1 St...

Page 8: ...e specific information 80 7 1 1 XCLKS 80 Section 8 Enhanced Capture Timer ECT Block Description Section 9 Analog to Digital Converter ATD Block Description Section 10 Inter IC Bus IIC Block Description Section 11 Serial Communications Interface SCI Block Description Section 12 Serial Peripheral Interface SPI Block Description Section 13 J1850 BDLC Block Description Section 14 Pulse Width Modulator...

Page 9: ...1 10 Supply Currents 97 A 2 ATD Characteristics 99 A 2 1 ATD Operating Characteristics 99 A 2 2 Factors influencing accuracy 99 A 2 3 ATD accuracy 101 A 3 NVM Flash and EEPROM 103 A 3 1 NVM timing 103 A 3 2 NVM Reliability 105 A 4 Voltage Regulator 109 A 5 Reset Oscillator and PLL 111 A 5 1 Startup 111 A 5 2 Oscillator 112 A 5 3 Phase Locked Loop 113 A 6 MSCAN 117 A 7 SPI 119 A 7 1 Master Mode 119...

Page 10: ...MC9S12DT256 Device User Guide V03 07 10 ...

Page 11: ...scillator 84 Figure 20 2 Recommended PCB Layout for 80QFP Colpitts Oscillator 85 Figure 20 3 Recommended PCB Layout for 112LQFP Pierce Oscillator 86 Figure 20 4 Recommended PCB Layout for 80QFP Pierce Oscillator 87 Figure A 1 ATD Accuracy Definitions 102 Figure A 2 Typical Endurance vs Temperature 107 Figure A 3 Basic PLL functional diagram 113 Figure A 4 Jitter Definitions 115 Figure A 5 Maximum ...

Page 12: ...MC9S12DT256 Device User Guide V03 07 12 ...

Page 13: ... 2 ESD and Latch up Test Conditions 92 Table A 3 ESD and Latch Up Protection Characteristics 92 Table A 4 Operating Conditions 93 Table A 5 Thermal Package Characteristics 95 Table A 6 5V I O Characteristics 96 Table A 7 Supply Current Characteristics 98 Table A 8 ATD Operating Characteristics 99 Table A 9 ATD Electrical Characteristics 100 Table A 10 ATD Conversion Performance 101 Table A 11 NVM ...

Page 14: ...MC9S12DT256 Device User Guide V03 07 14 Table A 21 Expanded Bus Timing Characteristics 125 ...

Page 15: ...rences Generic device MC9S12A256 MC9S12DT256 MC9S12DJ256 MC9S12DG256 of CANs 0 3 2 2 CAN0 CAN1 CAN4 J1850 BDLC Package 112 LQFP 80 QFP 112 LQFP 80 QFP 112 LQFP 80 QFP 112 LQFP 80 QFP Mask set L91N L01Y L91N L01Y L91N L01Y L91N L01Y Temp Options C M V C M V C M V C Package Code PV FU PV FU PV FU PV FU Notes An errata exists contact Sales Office An errata exists contact Sales Office An errata exists...

Page 16: ...t CAN1 Fill the four CAN4 interrupt vectors FF90 FF97 according to your coding policies for unused interrupts if using a derivative without CAN4 Fill the BDLC interrupt vector FFC2 FFC3 according to your coding policies for unused interrupts if using a derivative without BDLC Ports The CAN0 pin functionality TXCAN0 RXCAN0 is not available on port PJ7 PJ6 PM5 PM4 PM3 PM2 PM1 and PM0 if using a deri...

Page 17: ...1 S12BKPV1 D Clock and Reset Generator CRG Block User Guide V04 S12CRGV4 D Enhanced Capture Timer ECT_16B8C Block User Guide V01 S12ECT16B8CV1 D Analog to Digital Converter 10 Bit 8 Channels ATD_10B8C Block User Guide V02 S12ATD10B8CV2 D Inter IC Bus IIC Block User Guide V02 S12IICV2 D Asynchronous Serial Interface SCI Block User Guide V02 S12SCIV2 D Serial Peripheral Interface SPI Block User Guid...

Page 18: ...56 Device User Guide V03 07 18 EETS4K FTS256K Reliability Specification for Non Volatile Memories PIM_9DP256 CAN0 can be routed to PORTJ Table 0 3 Specification Change Summary for Maskset L91N Block Spec Change ...

Page 19: ... capability three CAN 2 0 A B software compatible modules MSCAN12 and an Inter IC Bus The MC9S12DT256 has full 16 bit data paths throughout However the external bus can operate in an 8 bit narrow mode so single 8 bit wide memory can be interfaced for lower cost systems The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements 1 2 Featur...

Page 20: ...6 bit main counter with 7 bit prescaler 8 programmable input capture or output compare channels Four 8 bit or two 16 bit pulse accumulators 8 PWM channels Programmable period and duty cycle 8 bit 8 channel or 16 bit 4 channel Separate control for each pulse width and duty cycle Center aligned or left aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency sh...

Page 21: ...Development support Single wire background debug mode BDM On chip hardware breakpoints 1 3 Modes of Operation User modes Normal and Emulation Operating Modes Normal Single Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Operating Modes Special Single Chip Mode with active Background Debug Mode Special Test Mode Mot...

Page 22: ...MC9S12DT256 Device User Guide V03 07 22 1 4 Block Diagram Figure 1 1 shows a block diagram of the MC9S12DT256 device ...

Page 23: ...01 PAD02 IOC2 IOC6 IOC0 IOC7 IOC1 IOC3 IOC4 IOC5 PT3 PT4 PT5 PT6 PT7 PT0 PT1 PT2 VRH VRL VDDA VSSA VRH VRL ATD1 AN2 AN6 AN0 AN7 AN1 AN3 AN4 AN5 PAD11 PAD12 PAD13 PAD14 PAD15 PAD08 PAD09 PAD10 VDDA VSSA RXD TXD MISO MOSI PS3 PS4 PS5 PS0 PS1 PS2 SCI1 RXD TXD PP3 PP4 PP5 PP6 PP7 PP0 PP1 PP2 PIX2 PIX0 PIX1 PIX3 ECS PK3 PK7 PK0 PK1 XADDR17 ECS XADDR14 XADDR15 XADDR16 SCK SS PS6 PS7 SPI0 IIC SDA SCL PJ6...

Page 24: ...0 009F Analog to Digital Converter 10 bit 8 channels ATD0 32 00A0 00C7 Pulse Width Modulator 8 bit 8 channels PWM 40 00C8 00CF Serial Communications Interface SCI0 8 00D0 00D7 Serial Communications Interface SCI1 8 00D8 00DF Serial Peripheral Interface SPI0 8 00E0 00E7 Inter IC Bus 8 00E8 00EF Byte Data Link Controller BDLC 8 00F0 00F7 Serial Peripheral Interface SPI1 8 00F8 00FF Serial Peripheral...

Page 25: ...EPROM array incl 0 5K 1K 2K or 4K Protected Sector at start 16384 8000 BFFF Flash EEPROM Page Window 16384 C000 FFFF Fixed Flash EEPROM array incl 0 5K 1K 2K or 4K Protected Sector at end and 256 bytes of Vector Space at FF80 FFFF 16384 Table 1 1 Device Memory Map Address Module Size Bytes ...

Page 26: ... CHIP REGISTERS Mappable to any 2k Block within the first 32K 0000 03FF 0000 0FFF 4K Bytes EEPROM Mappable to any 4K Block 12K Bytes RAM Mappable to any 16K 1000 3FFF and alignable to top or bottom 4000 7FFF 16K Fixed Flash Page 3E 62 This is dependant on the state of the ROMHM bit 8000 BFFF 16K Page Window 16 x 16K Flash EEPROM pages C000 FFFF 16K Fixed Flash Page 3F 63 FF00 FFFF BDM if active is...

Page 27: ...Write 0006 Reserved Read 0 0 0 0 0 0 0 0 Write 0007 Reserved Read 0 0 0 0 0 0 0 0 Write 0008 PORTE Read Bit 7 6 5 4 3 2 Bit 1 Bit 0 Write 0009 DDRE Read Bit 7 6 5 4 3 Bit 2 0 0 Write 000A PEAR Read NOACCE 0 PIPOE NECLK LSTRE RDWE 0 0 Write 000B MODE Read MODC MODB MODA 0 IVIS 0 EMK EME Write 000C PUCR Read PUPKE 0 0 PUPEE 0 0 PUPBE PUPAE Write 000D RDRIV Read RDPK 0 0 RDPE 0 0 RDPB RDPA Write 000E...

Page 28: ...erved Read 0 0 0 0 0 0 0 0 Write 0018 001B Miscellaneous Peripherals Device User Guide Table 1 3 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0018 Reserved Read 0 0 0 0 0 0 0 0 Write 0019 Reserved Read 0 0 0 0 0 0 0 0 Write 001A PARTIDH Read ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 Write 001B PARTIDL Read ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Write 001C 001D MMC map 3 of 4 Core and Device U...

Page 29: ...rite 0021 Reserved Read 0 0 0 0 0 0 0 0 Write 0022 Reserved Read 0 0 0 0 0 0 0 0 Write 0023 Reserved Read 0 0 0 0 0 0 0 0 Write 0024 Reserved Read 0 0 0 0 0 0 0 0 Write 0025 Reserved Read 0 0 0 0 0 0 0 0 Write 0026 Reserved Read 0 0 0 0 0 0 0 0 Write 0027 Reserved Read 0 0 0 0 0 0 0 0 Write 0028 002F BKP Core User Guide Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0028 BKPCT0 Read ...

Page 30: ...7 6 5 4 3 2 1 Bit 0 Write 0034 003F CRG Clock and Reset Generator Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0034 SYNR Read 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 Write 0035 REFDV Read 0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0 Write 0036 CTFLG TEST ONLY Read TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0 Write 0037 CRGFLG Read RTIF PROF 0 LOCKIF LOCK TRACK SCMIF SCM Write 0038 CRGINT Read ...

Page 31: ...11 10 9 Bit 8 Write 0045 TCNT lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0046 TSCR1 Read TEN TSWAI TSFRZ TFFCA 0 0 0 0 Write 0047 TTOV Read TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 Write 0048 TCTL1 Read OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 Write 0049 TCTL2 Read OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 Write 004A TCTL3 Read EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A Write 004B TCTL4 Read EDG3B EDG3A EDG2B EDG2A E...

Page 32: ...8 Write 005F TC7 lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0060 PACTL Read 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI Write 0061 PAFLG Read 0 0 0 0 0 0 PAOVF PAIF Write 0062 PACN3 hi Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0063 PACN2 lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0064 PACN1 hi Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0065 PACN0 lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0066 MCCTL Read MCZI MODMC RDMCL 0 0 MCEN M...

Page 33: ... Write 0078 TC0H hi Read Bit 15 14 13 12 11 10 9 Bit 8 Write 0079 TC0H lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 007A TC1H hi Read Bit 15 14 13 12 11 10 9 Bit 8 Write 007B TC1H lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 007C TC2H hi Read Bit 15 14 13 12 11 10 9 Bit 8 Write 007D TC2H lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 007E TC3H hi Read Bit 15 14 13 12 11 10 9 Bit 8 Write 007F TC3H lo Read Bit 7 6 5 4 3 2...

Page 34: ...0 Write 008D ATD0DIEN Read Bit 7 6 5 4 3 2 1 Bit 0 Write 008E Reserved Read 0 0 0 0 0 0 0 0 Write 008F PORTAD0 Read Bit7 6 5 4 3 2 1 BIT 0 Write 0090 ATD0DR0H Read Bit15 14 13 12 11 10 9 Bit8 Write 0091 ATD0DR0L Read Bit7 Bit6 0 0 0 0 0 0 Write 0092 ATD0DR1H Read Bit15 14 13 12 11 10 9 Bit8 Write 0093 ATD0DR1L Read Bit7 Bit6 0 0 0 0 0 0 Write 0094 ATD0DR2H Read Bit15 14 13 12 11 10 9 Bit8 Write 00...

Page 35: ...CKA2 PCKA1 PCKA0 Write 00A4 PWMCAE Read CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 Write 00A5 PWMCTL Read CON67 CON45 CON23 CON01 PSWAI PFRZ 0 0 Write 00A6 PWMTST Test Only Read 0 0 0 0 0 0 0 0 Write 00A7 PWMPRSC Read 0 0 0 0 0 0 0 0 Write 00A8 PWMSCLA Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00A9 PWMSCLB Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00AA PWMSCNTA Read 0 0 0 0 0 0 0 0 Write 00AB PWMSCNTB Read 0 0 0 0...

Page 36: ...Bit 0 Write 00BB PWMPER7 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00BC PWMDTY0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00BD PWMDTY1 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00BE PWMDTY2 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00BF PWMDTY3 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00C0 PWMDTY4 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00C1 PWMDTY5 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00C2 PWMDTY6 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00C3...

Page 37: ...ress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00D0 SCI1BDH Read 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 Write 00D1 SCI1BDL Read SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Write 00D2 SCI1CR1 Read LOOPS SCISWAI RSRC M WAKE ILT PE PT Write 00D3 SCI1CR2 Read TIE TCIE RIE ILIE TE RE RWU SBK Write 00D4 SCI1SR1 Read TDRE TC RDRF IDLE OR NF FE PF Write 00D5 SCI1SR2 Read 0 0 0 0 0 BRK13 TXDIR RAF Write ...

Page 38: ... D4 D3 D2 D1 D 0 Write 00E5 Reserved Read 0 0 0 0 0 0 0 0 Write 00E6 Reserved Read 0 0 0 0 0 0 0 0 Write 00E7 Reserved Read 0 0 0 0 0 0 0 0 Write 00E8 00EF BDLC Bytelevel Data Link Controller J1850 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00E8 DLCBCR1 Read IMSG CLKS 0 0 0 0 IE WCM Write 00E9 DLCBSVR Read 0 0 I3 I2 I1 I0 0 0 Write 00EA DLCBCR2 Read SMRST DLOOP RX4XE NBFS TEOD TS...

Page 39: ...s Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00F8 SPI2CR1 Read SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE Write 00F9 SPI2CR2 Read 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0 Write 00FA SPI2BR Read 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0 Write 00FB SPI2SR Read SPIF 0 SPTEF MODF 0 0 0 0 Write 00FC Reserved Read 0 0 0 0 0 0 0 0 Write 00FD SPI2DR Read Bit7 6 5 4 3 2 1 Bit0 Write 00FE Reserved Read 0 0 0 ...

Page 40: ...Reserved Read 0 0 0 0 0 0 0 0 Write 010F Reserved Read 0 0 0 0 0 0 0 0 Write 0110 011B EEPROM Control Register eets4k Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0110 ECLKDIV Read EDIVLD PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 Write 0111 Reserved Read 0 0 0 0 0 0 0 0 Write 0112 Reserved for Factory Test Read 0 0 0 0 0 0 0 0 Write 0113 ECNFG Read CBEIE CCIE 0 0 0 0 0 0 Write 011...

Page 41: ... Bit 0 0120 ATD1CTL0 Read 0 0 0 0 0 0 0 0 Write 0121 ATD1CTL1 Read 0 0 0 0 0 0 0 0 Write 0122 ATD1CTL2 Read ADPU AFFC AWAI ETRIGLE ETRIGP ETRIG ASCIE ASCIF Write 0123 ATD1CTL3 Read 0 S8C S4C S2C S1C FIFO FRZ1 FRZ0 Write 0124 ATD1CTL4 Read SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 Write 0125 ATD1CTL5 Read DJM DSGN SCAN MULT 0 CC CB CA Write 0126 ATD1STAT0 Read SCF 0 ETORF FIFOR 0 CC2 CC1 CC0 Write 0...

Page 42: ...4 13 12 11 10 9 Bit8 Write 0139 ATD1DR4L Read Bit7 Bit6 0 0 0 0 0 0 Write 013A ATD1DR5H Read Bit15 14 13 12 11 10 9 Bit8 Write 013B ATD1DR5L Read Bit7 Bit6 0 0 0 0 0 0 Write 013C ATD1DR6H Read Bit15 14 13 12 11 10 9 Bit8 Write 013D ATD1DR6L Read Bit7 Bit6 0 0 0 0 0 0 Write 013E ATD1DR7H Read Bit15 14 13 12 11 10 9 Bit8 Write 013F ATD1DR7L Read Bit7 Bit6 0 0 0 0 0 0 Write 0140 017F CAN0 Motorola Sc...

Page 43: ...R Read TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 Write 0150 0153 CAN0IDAR0 CAN0IDAR3 Read AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write 0154 0157 CAN0IDMR0 CAN0IDMR3 Read AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write 0158 015B CAN0IDAR4 CAN0IDAR7 Read AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write 015C 015F CAN0IDMR4 CAN0IDMR7 Read AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write 0160 016F CAN0RXFG Read FOREGROUND RECE...

Page 44: ...D8 ID7 ID6 ID5 ID4 ID3 Write xx10 Extended ID Read ID20 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 CANxTIDR1 Write Standard ID Read ID2 ID1 ID0 RTR IDE 0 Write xx12 Extended ID Read ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 CANxTIDR2 Write Standard ID Read Write xx13 Extended ID Read ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR CANxTIDR3 Write Standard ID Read Write xx14 xx1B CANxTDSR0 CANxTDSR7 Read DB7 DB6 DB5 DB4 DB3 ...

Page 45: ... Write 0189 CAN1TAAK Read 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 Write 018A CAN1TBSEL Read 0 0 0 0 0 TX2 TX1 TX0 Write 018B CAN1IDAC Read 0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0 Write 018C Reserved Read 0 0 0 0 0 0 0 0 Write 018D Reserved Read 0 0 0 0 0 0 0 0 Write 018E CAN1RXERR Read RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 Write 018F CAN1TXERR Read TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2...

Page 46: ...PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 Write 0241 PTIT Read PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 Write 0242 DDRT Read DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 Write 0243 RDRT Read RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 Write 0244 PERT Read PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 Write 0245 PPST Read PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 Write 0246 Rese...

Page 47: ...TP1 PTP0 Write 0259 PTIP Read PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 Write 025A DDRP Read DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 Write 025B RDRP Read RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 Write 025C PERP Read PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 Write 025D PPSP Read PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSS0 Write 025E PIEP Read PIEP7 PIEP6 PIEP5 PIEP4 P...

Page 48: ...it 3 Bit 2 Bit 1 Bit 0 0280 CAN4CTL0 Read RXFRM RXACT CSWAI SYNCH TIME WUPE SLPRQ INITRQ Write 0281 CAN4CTL1 Read CANE CLKSRC LOOPB LISTEN 0 WUPM SLPAK INITAK Write 0282 CAN4BTR0 Read SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Write 0283 CAN4BTR1 Read SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Write 0284 CAN4RFLG Read WUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF Write 0285 CAN4RIER Re...

Page 49: ...Write 0296 CAN4IDMR2 Read AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write 0297 CAN4IDMR3 Read AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write 0298 CAN4IDAR4 Read AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write 0299 CAN4IDAR5 Read AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write 029A CAN4IDAR6 Read AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write 029B CAN4IDAR7 Read AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write 029C CAN4IDMR4 Read AM7 AM6 AM5 AM4 AM3 AM2 AM...

Page 50: ... Module Mapping and Control MMC of HCS12 Core User Guide for further details 02C0 03FF Reserved space Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 02C0 03FF Reserved Read 0 0 0 0 0 0 0 0 Write Table 1 3 Assigned Part ID Numbers Device Mask Set Number Part ID1 NOTES 1 The coding is as follows Bit 15 12 Major family identifier Bit 11 8 Minor family identifier Bit 7 4 Major mask set r...

Page 51: ...l description sections of the Block User Guides of the individual IP blocks on the device 2 1 Device Pinout The MC9S12DT256 MC9S12DJ256 MC9S12DG256 and MC9S12A256 is available in a 112 pin low profile quad flat pack LQFP and MC9S12DJ256 MC9S12DG256 and MC9S12A256 is also available in a 80 pin quad flat pack QFP Most pins perform two or more functions as described in the Signal Descriptions Figure ...

Page 52: ...P1 PP1 MISO1 PWM0 KWP0 PP0 XADDR17 PK3 XADDR16 PK2 XADDR15 PK1 XADDR14 PK0 IOC0 PT0 IOC1 PT1 IOC2 PT2 IOC3 PT3 VDD1 VSS1 IOC4 PT4 IOC5 PT5 IOC6 PT6 IOC7 PT7 XADDR19 PK5 XADDR18 PK4 KWJ1 PJ1 KWJ0 PJ0 MODC TAGHI BKGD ADDR0 DATA0 PB0 ADDR1 DATA1 PB1 ADDR2 DATA2 PB2 ADDR3 DATA3 PB3 ADDR4 DATA4 PB4 ADDR5 DATA5 PB5 ADDR6 DATA6 PB6 ADDR7 DATA7 PB7 SS2 KWH7 PH7 SCK2 KWH6 PH6 MOSI2 KWH5 PH5 MISO2 KWH4 PH4 ...

Page 53: ...TA11 PA2 ADDR10 DATA10 PA1 ADDR9 DATA9 PA0 ADDR8 DATA8 PP4 KWP4 PWM4 MISO2 PP5 KWP5 PWM5 MOSI2 PP7 KWP7 PWM7 SCK2 VDDX VSSX PM0 RXCAN0 RXB PM1 TXCAN0 TXB PM2 RXCAN1 RXCAN0 MISO0 PM3 TXCAN1 TXCAN0 SS0 PM4 RXCAN0 RXCAN4 MOSI0 PM5 TXCAN0 TXCAN4 SCK0 PJ6 KWJ6 RXCAN4 SDA PJ7 KWJ7 TXCAN4 SCL VREGEN PS3 TXD1 PS2 RXD1 PS1 TXD0 PS0 RXD0 VSSA VRL SS1 PWM3 KWP3 PP3 SCK1 PWM2 KWP2 PP2 MOSI1 PWM1 KWP1 PP1 MISO...

Page 54: ... 6 0 AN0 6 0 VDDA None None Port AD Inputs Analog Inputs AN 6 0 of ATD0 PA 7 0 ADDR 15 8 DATA 15 8 VDDR PUCR Disabled Port A I O Multiplexed Address Data PB 7 0 ADDR 7 0 DATA 7 0 VDDR PUCR Disabled Port B I O Multiplexed Address Data PE7 NOACC XCLKS VDDR PUCR Up Port E I O Access Clock Select PE6 IPIPE1 MODB VDDR While RESET pin is low Down Port E I O Pipe Status Mode Input PE5 IPIPE0 MODA VDDR Wh...

Page 55: ... PERM PPSM Disabled Port M I O TX of CAN4 PM6 RXCAN4 VDDX PERM PPSM Disabled Port M I O RX of CAN4 PM5 TXCAN0 TXCAN4 SCK0 VDDX PERM PPSM Disabled Port M I OCAN0 CAN4 SCK of SPI0 PM4 RXCAN0 RXCAN4 MOSI0 VDDX PERM PPSM Disabled Port M I O CAN0 CAN4 MOSI of SPI0 PM3 TXCAN1 TXCAN0 SS0 VDDX PERM PPSM Disabled Port M I O TX of CAN1 CAN0 SS of SPI0 PM2 RXCAN1 RXCAN0 MISO0 VDDX PERM PPSM Disabled Port M I...

Page 56: ...DX PERP PPSP Disabled Port P I O Interrupt Channel 2 of PWM SCK of SPI1 PP1 KWP1 PWM1 MOSI1 VDDX PERP PPSP Disabled Port P I O Interrupt Channel 1 of PWM MOSI of SPI1 PP0 KWP0 PWM0 MISO1 VDDX PERP PPSP Disabled Port P I O Interrupt Channel 0 of PWM MISO2 of SPI1 PS7 SS0 VDDX PERS PPSS Up Port S I O SS of SPI0 PS6 SCK0 VDDX PERS PPSS Up Port S I O SCK of SPI0 PS5 MOSI0 VDDX PERS PPSS Up Port S I O ...

Page 57: ...ain pin for the background debug communication In MCU expanded modes of operation when instruction tagging is on an input low on this pin during the falling edge of E clock tags the high half of the instruction word being read into the instruction queue It is used as a MCU operating mode select pin during reset The state of this pin is latched to the MODC bit at the rising edge of RESET This pin h...

Page 58: ...ed for the multiplexed external address and data bus 2 3 13 PE7 NOACC XCLKS Port E I O Pin 7 PE7 is a general purpose input or output pin During MCU expanded modes of operation the NOACC signal when enabled is used to indicate that the current bus cycle is an unused or free cycle This signal will assert when the CPU is not using the bus The XCLKS is an input signal which controls whether a crystal...

Page 59: ...rystal or VSSPLL ceramic resonator C1 CDC Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal Please contact the crystal manufacturer for crystal DC MCU EXTAL XTAL RS RB VSSPLL Crystal or ceramic resonator C2 C1 Rs can be zero shorted when use with higher frequency crystals Refer to manufacturer s data ...

Page 60: ...e of this pin is latched to the MODA bit at the rising edge of RESET This pin is shared with the instruction queue tracking signal IPIPE0 This pin is an input with a pull down device which is only active when RESET is low 2 3 16 PE4 ECLK Port E I O Pin 4 PE4 is a general purpose input or output pin It can be configured to drive the internal bus clock ECLK ECLK can be used as a timing reference 2 3...

Page 61: ...pheral Interface 2 SPI2 2 3 22 PH6 KWH6 SCK2 Port H I O Pin 6 PH6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 SPI2 2 3 23 PH5 KWH5 MOSI2 Port H I O Pin 5 PH5 is a general purpose input or output pin It can be configured to generate a...

Page 62: ...pose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as the transmit pin TXCAN for the Motorola Scalable Controller Area Network controller 4 CAN4 or the serial clock pin SCL of the IIC module 2 3 30 PJ6 KWJ6 RXCAN4 SDA PORT J I O Pin 6 PJ6 is a general purpose input or output pin It can be configured to generate an i...

Page 63: ... pin SCK of the Serial Peripheral Interface 0 SPI0 2 3 37 PM4 RXCAN0 RXCAN4 MOSI0 Port M I O Pin 4 PM4 is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 0 or 4 CAN0 or CAN4 It can be configured as the master output during master mode or slave input pin during slave mode MOSI for the Serial Peripheral ...

Page 64: ...e It can be configured as Pulse Width Modulator PWM channel 6 output It can be configured as slave select pin SS of the Serial Peripheral Interface 2 SPI2 2 3 44 PP5 KWP5 PWM5 MOSI2 Port P I O Pin 5 PP5 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 5 output I...

Page 65: ...be configured as Pulse Width Modulator PWM channel 0 output It can be configured as master input during master mode or slave output during slave mode pin MISO of the Serial Peripheral Interface 1 SPI1 2 3 50 PS7 SS0 Port S I O Pin 7 PS6 is a general purpose input or output pin It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 SPI0 2 3 51 PS6 SCK0 Port S I O Pin 6...

Page 66: ... 2 4 Power Supply Pins MC9S12DT256 power and ground pins are described below NOTE All VSS pins must be connected together in the application 2 4 1 VDDX VSSX Power Ground Pins for I O Drivers External power and ground for I O drivers Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them ...

Page 67: ...ce Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter 2 4 6 VDDPLL VSSPLL Power Supply Pins for PLL Provides operating voltage and ground for the Oscillator and the Phased Locked Loop This allows the supply voltage to the Oscillator and PLL to be bypassed independently This 2 5V voltage is generated by the internal voltage regulator NOTE No load...

Page 68: ...VDDPLL must be supplied externally VDDPLL 43 2 5 V Provides operating voltage and ground for the Phased Locked Loop This allows the supply voltage to the PLL to be bypassed independently Internal power and ground generated by internal regulator VSSPLL 45 0 V VREGEN 97 5V Internal Voltage Regulator enable disable Mnemonic Pin Number Nominal Voltage Description 112 pin QFP ...

Page 69: ...gnals for the core and all peripheral modules Figure 3 1 shows the clock connections from the CRG to all modules Consult the CRG Block User Guide for details on clock generation Figure 3 1 Clock Connections CRG bus clock core clock EXTAL XTAL oscillator clock S12_CORE IIC RAM SCI0 SCI1 PWM ATD0 1 EEPROM Flash ECT BDLC SPI0 1 2 CAN0 1 2 3 4 PIM BDM ...

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Page 71: ...ther the internal Flash is visible in the memory map ROMON 1 mean the Flash is visible in the memory map The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal For further explanation on the modes refer to the Core User Guide Table 4 1 Mode Selection BKGD MODC PE6 MODB PE5 MODA PK7 ROMCTL ROMON Bit Mode Description 0 0 0 X 1 Special Si...

Page 72: ...d in EEPROM 4 3 1 Securing the Microcontroller Once the user has programmed the FLASH and EEPROM if desired the part can be secured by programming the security bits located in the FLASH module These non volatile bits will keep the part secured through resetting the part and through powering down the part The security byte resides in a portion of the Flash array Check the Flash Block User Guide for...

Page 73: ...rity bits are reprogrammed to the unsecure state the part will be secured again 4 4 Low Power Modes The microcontroller features three main low power modes Consult the respective Block User Guide for information on the module behavior in Stop Pseudo Stop and Wait Mode An important source of information about the clock system is the Clock and Reset Generator User Guide CRG 4 4 1 Stop Executing the ...

Page 74: ...MC9S12DT256 Device User Guide V03 07 74 4 4 4 Run Although this is not a low power mode unused peripheral modules should not be enabled in order to save power ...

Page 75: ...F0 FFF1 Real Time Interrupt I Bit CRGINT RTIE F0 FFEE FFEF Enhanced Capture Timer channel 0 I Bit TIE C0I EE FFEC FFED Enhanced Capture Timer channel 1 I Bit TIE C1I EC FFEA FFEB Enhanced Capture Timer channel 2 I Bit TIE C2I EA FFE8 FFE9 Enhanced Capture Timer channel 3 I Bit TIE C3I E8 FFE6 FFE7 Enhanced Capture Timer channel 4 I Bit TIE C4I E6 FFE4 FFE5 Enhanced Capture Timer channel 5 I Bit TI...

Page 76: ...FB6 FFB7 CAN0 wake up I Bit CAN0RIER WUPIE B6 FFB4 FFB5 CAN0 errors I Bit CAN0RIER CSCIE OVRIE B4 FFB2 FFB3 CAN0 receive I Bit CAN0RIER RXFIE B2 FFB0 FFB1 CAN0 transmit I Bit CAN0TIER TXEIE2 TXEIE0 B0 FFAE FFAF CAN1 wake up I Bit CAN1RIER WUPIE AE FFAC FFAD CAN1 errors I Bit CAN1RIER CSCIE OVRIE AC FFAA FFAB CAN1 receive I Bit CAN1RIER RXFIE AA FFA8 FFA9 CAN1 transmit I Bit CAN1TIER TXEIE2 TXEIE0 ...

Page 77: ...guration of port A B E and K out of reset Refer to the PIM Block User Guide for reset configurations of all peripheral module ports NOTE For devices assembled in 80 pin QFP packages all non bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs Refer to Table 2 1 for affected pins 5 3 2 Memory Refer to Table 1 1 for locations of the memorie...

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Page 79: ... specific information INITEE Reset state 01 Bits EE11 EE15 are writeable once in Normal and Emulation Mode PPAGE Reset state 00 Register is writeable anytime in all modes 6 3 HCS12 Multiplexed External Bus Interface MEBI Block Description Consult the MEBI Block Guide for information on Multiplexed External Bus Interface 6 3 1 Device specific information PUCR Reset State 90 6 4 HCS12 Interrupt INT ...

Page 80: ..._16B8C Block User Guide for information about the Enhanced Capture Timer module When the ECT_16B8C Block Guide refers to freeze mode this is equivalent to active BDM mode Section 9 Analog to Digital Converter ATD Block Description There are two Analog to Digital Converters ATD1 and ATD0 implemented on the MC9S12DT256 Consult the ATD_10B8C Block User Guide for information about each Analog to Digit...

Page 81: ... Description The S12 LRAE is a generic Load RAM and Execute LRAE program which will be programmed into the flash memory of this device during manufacture This LRAE program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using CAN or SCI after it is assembled on the PCB Use of the LRAE program is at the discretion of the end user and if...

Page 82: ...three MSCAN modules CAN4 CAN1 and CAN0 implemented on the MC9S12DT256 Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module Section 19 Port Integration Module PIM Block Description Consult the PIM_9DP256 Block User Guide for information about the Port Integration Module Section 20 Voltage Regulator VREG Block Description Consult the VREG Block User Guide for inf...

Page 83: ... C7 C8 C11 and Q1 as small as possible Do not place other signals or supplies underneath area occupied by C7 C8 C10 and Q1 and the connection area to the MCU Central power input should be fed in at the VDDA VSSA pins Component Purpose Type Value C1 VDD1 filter cap ceramic X7R 100 220nF C2 VDD2 filter cap ceramic X7R 100 220nF C3 VDDA filter cap ceramic X7R 100nF C4 VDDR filter cap X7R tantalum 100...

Page 84: ...256 Device User Guide V03 07 84 Figure 20 1 Recommended PCB Layout for 112LQFP Colpitts Oscillator C5 C4 C1 C6 C3 C2 C8 C7 Q1 C10 C9 R1 VDDX VSSX VDDR VSSR VDD1 VSS1 VDD2 VSS2 VDDPLL VSSPLL VDDA VSSA VREGEN C11 ...

Page 85: ...T256 Device User Guide V03 07 85 Figure 20 2 Recommended PCB Layout for 80QFP Colpitts Oscillator C5 C4 C3 C2 C8 C7 C10 C9 R1 C11 C6 C1 Q1 VDD1 VSS1 VSS2 VDD2 VSSR VDDR VSSPLL VDDPLL VDDA VSSA VSSX VREGEN VDDX ...

Page 86: ...256 Device User Guide V03 07 86 Figure 20 3 Recommended PCB Layout for 112LQFP Pierce Oscillator C5 C4 C1 C6 C3 C2 C10 C9 R1 VDDX VSSX VDDR VSSR VDD1 VSS1 VDD2 VSS2 VDDPLL VSSPLL VDDA VSSA VREGEN R2 C7 R3 C8 Q1 ...

Page 87: ... Device User Guide V03 07 87 Figure 20 4 Recommended PCB Layout for 80QFP Pierce Oscillator C5 C4 C3 C2 C10 C9 R1 C6 C1 VDD1 VSS1 VSS2 VDD2 VSSR VDDR VSSPLL VDDPLL VDDA VSSA VSSX VREGEN VDDX R2 C7 R3 C8 Q1 VSSPLL ...

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Page 89: ...ding the following classification is used and the parameters are tagged accordingly in the tables where appropriate NOTE This classification is shown in the column labeled C in the parameter tables where appropriate P Those parameters are guaranteed during production testing on each individual device C Those parameters are achieved by the design characterization by measuring a statistically releva...

Page 90: ... VDDPLL VSS is used for VSS1 VSS2 and VSSPLL IDD is used for the sum of the currents flowing into VDD1 and VDD2 A 1 3 Pins There are four groups of functional pins A 1 3 1 5V I O pins Those I O pins have a nominal level of 5V This class of pins is comprised of all port I O pins the analog inputs BKGD and the RESET pins The internal structure of all those pins is identical however some of the funct...

Page 91: ...ic voltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g either VSS5 or VDD5 Table A 1 Absolute Maximum Ratings1 NOTES 1 Beyond absolute maximum ratings device mi...

Page 92: ...y when the device is powered from an external source 3 All digital I O pins are internally clamped to VSSX and VDDX VSSR and VDDR or VSSA and VDDA 4 Those pins are internally clamped to VSSPLL and VDDPLL 5 This pin is clamped low to VSSR but not clamped high This pin must be tied low in applications Table A 2 ESD and Latch up Test Conditions Model Description Symbol Value Unit Human Body Series Re...

Page 93: ... V Digital Logic Supply Voltage 1 NOTES 1 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source VDD 2 35 2 5 2 75 V PLL Supply Voltage 1 VDDPLL 2 35 2 5 2 75 V Voltage Difference VDDX to VDDR and VDDA VDDX 0 1 0 0 1 V Voltage Di...

Page 94: ... the overall current flowing into VDDR which additionally contains the current flowing into the external loads with output high PIO is the sum of all output currents on I O ports associated with VDDX and VDDR T J T A P D Θ JA T J Junction Temperature C T A Ambient Temperature C P D Total Chip Power Dissipation W Θ JA Package Thermal Resistance C W P D P INT P IO P INT Chip Internal Power Dissipati...

Page 95: ...for thermal resistance are achieved by package simulations Num C Rating Symbol Min Typ Max Unit 1 T Thermal Resistance LQFP112 single sided PCB2 2 PC Board according to EIA JEDEC Standard 51 2 θJA 54 o C W 2 T Thermal Resistance LQFP112 double sided PCB with 2 internal planes3 3 PC Board according to EIA JEDEC Standard 51 7 θJA 41 o C W 3 T Thermal Resistance LQFP 80 single sided PCB θJA 51 oC W 4...

Page 96: ... V OH VDD5 0 8 V 6 P Output High Voltage pins in output mode Full Drive IOH 10mA VOH VDD5 0 8 V 7 C Output Low Voltage pins in output mode Partial Drive IOL 2mA VOL 0 8 V 8 P Output Low Voltage pins in output mode Full Drive IOL 10mA V OL 0 8 V 9 P Internal Pull Up Device Current tested at V IL Max IPUL 130 µA 10 C Internal Pull Up Device Current tested at V IH Min IPUH 10 µA 11 P Internal Pull Do...

Page 97: ...ise noted the currents are measured in single chip mode internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode Production testing is performed using a square wave signal at the EXTAL input A 1 10 2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address data and control signals as well a...

Page 98: ...DW 40 5 mA 3 C P C C P C P C P Pseudo Stop Current RTI and COP disabled 1 2 40 C 27 C 70 C 85 C C Temp Option 100 C 105 C V Temp Option 120 C 125 C M Temp Option 140 C NOTES 1 PLL off 2 At those low power dissipation levels TJ TA can be assumed IDDPS 370 400 450 550 600 650 800 850 1200 500 1600 2100 5000 µA 4 C C C C C C C Pseudo Stop Current RTI and COP enabled 1 2 40 C 27 C 70 C 85 C 105 C 125 ...

Page 99: ... a voltage drop from the signal source to the ATD input The maximum source resistance RS Table A 8 ATD Operating Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 D Reference Potential Low High VRL VRH VSSA VDDA 2 VDDA 2 VDDA V V 2 C Differential Reference Voltage1 NOTES 1 Full accuracy is not guaranteed when differential voltage is les...

Page 100: ...s greater than VRH and 000 for values less than VRL unless the current is higher than specified as disruptive condition 2 Current is injected into pins in the neighborhood of the channel being converted A portion of this current is picked up by the channel coupling ratio K This additional current impacts the accuracy of the conversion depending on the source resistance The additional input voltage...

Page 101: ... unless otherwise noted VREF VRH VRL 5 12V Resulting to one 8 bit count 20mV and one 10 bit count 5mV fATDCLK 2 0MHz Num C Rating Symbol Min Typ Max Unit 1 P 10 Bit Resolution LSB 5 mV 2 P 10 Bit Differential Nonlinearity DNL 1 1 Counts 3 P 10 Bit Integral Nonlinearity INL 2 5 1 5 2 5 Counts 4 P 10 Bit Absolute Error1 NOTES 1 These values include the quantization error which is inherently 1 2 coun...

Page 102: ...1 5 Vin mV 10 15 20 25 30 35 40 5085 5090 5095 5100 5105 5110 5115 5120 5065 5070 5075 5080 5060 0 3 2 5 4 7 6 50 3F7 3F9 3F8 3FB 3FA 3FD 3FC 3FE 3FF 3F4 3F6 3F5 8 9 1 2 FF FE FD 3F3 10 Bit Resolution 8 Bit Resolution Ideal Transfer Curve 10 Bit Transfer Curve 8 Bit Transfer Curve 5055 10 Bit Absolute Error Boundary 8 Bit Absolute Error Boundary LSB Vi 1 Vi DNL ...

Page 103: ... using the FCLKDIV and ECLKDIV registers respectively The frequency of this clock must be set within the limits specified as fNVMOP The minimum program and erase times shown in Table A 11 are calculated for maximum fNVMOP and maximum fbus The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz A 3 1 1 Single Word Programming The programming time for single word programming is depend...

Page 104: ...p Max Unit 1 D External Oscillator Clock MC9S12DT256C V M fNVMOSC 0 5 50 1 NOTES 1 Restrictions for oscillator in crystal mode apply MHz 2 D Bus frequency for Programming or Erase Operations fNVMBUS 1 MHz 3 D Operating Frequency fNVMOP 150 200 kHz 4 P Single Word Programming Time tswpgm 46 2 2 Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequ...

Page 105: ...OP and bus frequency fbus Refer to formulae in Sections A 3 1 1 A 3 1 4 for guidance 4 Burst Programming operations are not applicable to EEPROM 5 Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP 6 Minimum time if first word in the array is not blank 7 Maximum time to complete check on an erased block ...

Page 106: ...d de rated to 25 C using the Arrhenius equation For additional information on how Freescale defines Typical Data Retention please refer to Engineering Bulletin EB618 Years 2 C Data retention with 100 program erase cycles at an average junction temperature TJavg 85 C 20 1002 3 C Number of program erase cycles 40 C TJ 0 C nFL 10 000 Cycles 4 C Number of program erase cycles 0 C TJ 140 C 10 000 100 0...

Page 107: ...evice User Guide V03 07 107 Figure A 2 Typical Endurance vs Temperature Typical Endurance 10 3 Cycles Operating Temperature TJ C 0 50 100 150 200 250 300 350 400 450 500 40 20 0 20 40 60 80 100 120 140 Flash EEPROM ...

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Page 109: ...e regulator is intended to supply the internal logic and oscillator circuits No external DC load is allowed Table A 13 Voltage Regulator Recommended Load Capacitances Rating Symbol Min Typ Max Unit Load Capacitance on VDD1 2 CLVDD 220 nF Load Capacitance on VDDPLL CLVDDfcPLL 220 nF ...

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Page 111: ...ided an appropriate external reset signal is applied to the MCU preventing the CPU from executing code when VDD5 is out of specification limits the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set A 5 1 3 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset and the CP...

Page 112: ...art up time tUPOSC The device also features a clock monitor A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA Table A 15 Oscillator Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1a C Crystal oscillator range Colpitts fOSC 0 5 16 MHz 1b C Crystal oscillator range Pierc...

Page 113: ... The following procedure can be used to calculate the resistance and capacitance values using typical values for K1 f1 and ich from Table A 16 The grey boxes show the calculation for fVCO 50MHz and fref 1MHz E g these frequencies are used for fOSC 4MHz and a 25MHz bus clock The VCO Gain at the desired VCO frequency is approximated by The phase detector relationship is given by ich is the current i...

Page 114: ...he basic functionality of the PLL is shown in Figure A 3 With each transition of the clock fcmp the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly The adjustment is done continuously with no abrupt changes in the clock output frequency Noise voltage temperature and other factors cause slight variations in the control loop resulting in a clo...

Page 115: ...clock period and decreases towards zero for larger number of clock periods N Defining the jitter as For N 100 the following equation is a good fit for the maximum jitter Figure A 5 Maximum bus clock jitter approximation 2 3 N 1 N 1 0 tnom tmax1 tmin1 tmaxN tminN J N max 1 tmax N N tnom 1 tmin N N tnom J N j1 N j2 1 5 10 20 N J N ...

Page 116: ...frequency 4 D Lock Detection Lock 0 1 5 1 5 D Un Lock Detection unl 0 5 2 5 1 6 D Lock Detector transition from Tracking to Acquisition mode unt 6 8 1 7 C PLLON Total Stabilization delay Auto Mode 2 2 fosc 4MHz fBUS 25MHz equivalent fVCO 50MHz REFDV 03 SYNR 018 Cs 4 7nF Cp 470pF Rs 10KΩ tstab 0 5 ms 8 D PLLON Acquisition mode stabilization delay 2 tacq 0 3 ms 9 D PLLON Tracking mode stabilization ...

Page 117: ...MSCAN Table A 17 MSCAN Wake up Pulse Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P MSCAN Wake up dominant pulse filtered tWUP 2 µs 2 P MSCAN Wake up dominant pulse pass tWUP 5 µs ...

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Page 119: ...PHA 0 In Figure A 7 the timing diagram for master mode with transmission format CPHA 1 is depicted Table A 18 Measurement Conditions Description Value Unit Drive mode full drive mode Load capacitance CLOAD on all outputs 50 pF Thresholds for delay measurement points 20 80 VDDX V SCK OUTPUT SCK OUTPUT MISO INPUT MOSI OUTPUT SS1 OUTPUT 1 9 5 6 MSB IN2 BIT 6 1 LSB IN MSB OUT2 LSB OUT BIT 6 1 11 4 4 2...

Page 120: ...4 Clock SCK High or Low Time twsck 1 2 tsck 5 Data Setup Time Inputs tsu 8 ns 6 Data Hold Time Inputs thi 8 ns 9 Data Valid after SCK Edge tvsck 30 ns 10 Data Valid after SS fall CPHA 0 tvss 15 ns 11 Data Hold Time Outputs tho 20 ns 12 Rise and Fall Time Inputs trfi 8 ns 13 Rise and Fall Time Outputs trfo 8 ns SCK OUTPUT SCK OUTPUT MISO INPUT MOSI OUTPUT 1 5 6 MSB IN2 BIT 6 1 LSB IN MASTER MSB OUT...

Page 121: ... 0 is depicted Figure A 8 SPI Slave Timing CPHA 0 In Figure A 9 the timing diagram for slave mode with transmission format CPHA 1 is depicted SCK INPUT SCK INPUT MOSI INPUT MISO OUTPUT SS INPUT 1 9 5 6 MSB IN BIT 6 1 LSB IN SLAVE MSB SLAVE LSB OUT BIT 6 1 11 4 4 2 7 CPOL 0 CPOL 1 3 13 NOTE Not defined 12 12 11 SEE 13 NOTE 8 10 see note ...

Page 122: ...Data Setup Time Inputs tsu 8 ns 6 Data Hold Time Inputs thi 8 ns 7 Slave Access Time time to data active ta 20 ns 8 Slave MISO Disable Time tdis 22 ns 9 Data Valid after SCK Edge tvsck 30 tbus 1 NOTES 1 tbus added due to internal synchronization delay ns 10 Data Valid after SS fall tvss 30 tbus 1 ns 11 Data Hold Time Outputs tho 20 ns 12 Rise and Fall Time Inputs trfi 8 ns 13 Rise and Fall Time Ou...

Page 123: ... values shown on table Table A 21 All major bus signals are included in the diagram While both a data write and data read cycle are shown only one or the other would occur on a particular bus cycle A 8 1 General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions The timing parameters shown assume a balanced load across all outputs ...

Page 124: ...Timing Addr Data read Addr Data write addr data data 5 10 11 8 16 6 ECLK 1 2 3 4 addr data data 12 15 9 7 14 13 ECS 21 20 22 23 Non Multiplexed 17 19 LSTRB 29 NOACC 32 IPIPO0 IPIPO1 PE6 5 35 18 27 28 30 33 36 31 34 R W 24 26 25 Addresses PE4 PA PB PA PB PK5 0 PK7 PE2 PE3 PE7 ...

Page 125: ...data hold time tDHW 2 ns 14 D Write data setup time1 PWEH tDDW tDSW 12 ns 15 D Address access time1 tcyc tAD tDSR tACCA 19 ns 16 D E high access time1 PWEH tDSR tACCE 6 ns 17 D Non multiplexed address delay time tNAD 6 ns 18 D Non muxed address valid to E rise PWEL tNAD tNAV 15 ns 19 D Non multiplexed address hold time tNAH 2 ns 20 D Chip select delay time tCSD 16 ns 21 D Chip select access time1 ...

Page 126: ...11 ns 35 D IPIPO 1 0 delay time1 PWEH tP1V tP1D 2 25 ns 36 D IPIPO 1 0 valid time to E fall tP1V 11 ns NOTES 1 Affected by clock stretch add N x tcyc where N 0 1 2 or 3 depending on the number of clock stretches Table A 21 Expanded Bus Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted CLOAD 50pF Num C Rating Symbol Min Typ Max Unit ...

Page 127: ...MC9S12DT256 Device User Guide V03 07 127 Appendix B Package Information B 1 General This section provides the physical dimensions of the MC9S12DT256 packages ...

Page 128: ... 56 B V V1 B1 A1 S1 A S VIEW AB 0 10 3 C C2 θ 2 θ 0 050 SEATING PLANE GAGE PLANE 1 θ θ VIEW AB C1 Z Y E K R2 R1 0 25 J1 VIEW Y J1 P G 108X 4X SECTION J1 J1 BASE ROTATED 90 COUNTERCLOCKWISE METAL J AA F D L M M 0 13 N T 1 2 3 C L L M 0 20 N T L N M T T 112X X X L M OR N R R NOTES 1 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 2 DIMENSIONS IN MILLIMETERS 3 DATUMS L M AND N TO BE DETERMINED AT S...

Page 129: ... DETERMINED AT DATUM PLANE H 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT SECTION B B 61 60 DETAIL A L 41 40 80 A L D A S A B M 0 20 D S H 0 05 A B S 1 20 21 B B V J F N D VIEW ROTATED 90 DETAIL A B B P A B D E H G M M DETAIL C SEAT...

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Page 131: ...MC9S12DT256 Device User Guide V03 07 131 User Guide End Sheet ...

Page 132: ...MC9S12DT256 Device User Guide V03 07 132 FINAL PAGE OF 132 PAGES ...

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