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MC68VZ328 User’s Manual

Programming Example

8.3.20

DMA Control Register

The LCD controller contains an 8

×

16 pixel buffer, which stores DMA-in data from system memory. This

data is then passed to the LCD for display. When enough data has been removed from the buffer that it
needs to be refilled, a new DMA transfer must be initiated. The DMA control register controls when the
buffer should be refilled and the DMA burst length used when refilling. The bit assignments for the
register are shown in the following register display. The settings for the bits are listed in Table 8-20.

DMACR

DMA Control Register

0x(FF)FFFA39

8.4

Programming Example

The following is an example of how to program the related registers to properly configure an LCD panel
with a resolution of 240

×

160 pixels, 4 levels of grayscale, and a 4-bit LCD data interface. The virtual

image is 320 pixels wide and panned by 3 pixels.

Example 8-1. Programming Example

LCDINT

move.l #$A80000,#$FFFA00 ;display data address starts at $A80000
move.w #240,#$FFFA08

;LCD horizontal size is 240

move.w #159,#$FFFA0A

;LCD vertical size is 160

move.b #40,#$FFFA05

;4 level gray and 320 pixels wide image

move.b #$09,#$FFFA20

;LCD panel data bus is 4 bits,4 level gray

move.b #3,#$FFFA25

;pixel clock rate equal 1/4 of LCDCLK from PLL

move.b #10,#$FFFA29

;refresh rate adjustment

move.b #$03,#$FFFA2D

;shift picture by 3 pixels

move.b #$82,#$FFFA27

;switch on LCDC, 2 wait state for memory cycle

BIT 7

6

5

4

3

2

1

BIT 0

DMABL[3:0]

DMATM[2:0]

TYPE

rw

rw

rw

rw

rw

rw

rw

RESET

0

1

1

0

0

0

1

0

0x62

Table 8-20. DMA Control Register Description

Name

Description

Setting

DMABL[3:0]
Bits 7

–

4

DMA Burst Length—This field sets the number of words to be
loaded to the pixel buffer in each DMA cycle.

See description and table
footnote.

Reserved
Bit 3

Reserved

This bit is reserved and
should be set to 0.

DMATM[2:0]
Bits 2

–

0

DMA Trigger Mark—This field sets the low-level mark in the pixel
buffer to trigger a DMA request. The low-level mark equals to the
number of words left in the pixel buffer.

See description and table
footnote.

Note:

Since the FIFO size is 8

×

16, DMABL and DMATM must be programmed based on the following criteria:

F_HI + F_LO <= 8
1 <= F_HI <= 8
1<= F_LO <= 6

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Summary of Contents for MC68VZ328

Page 1: ...MC68VZ328UM D Rev 0 02 2000 MC68VZ328 Integrated Processor User s Manual ...

Page 2: ...personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or deat...

Page 3: ...ol 1 9 1 3 4 Chip Select Logic 1 9 1 3 5 DRAM Controller 1 9 1 3 6 LCD Controller 1 9 1 3 7 Interrupt Controller 1 9 1 3 8 General Purpose I O GPIO Lines 1 10 1 3 9 Real Time Clock 1 10 1 3 10 General Purpose Timer 1 10 1 3 11 Serial Peripheral Interfaces SPI 1 10 1 3 12 Universal Asynchronous Receiver Transmitter UART Modules 1 10 1 3 13 Pulse Width Modulators PWM 1 11 1 3 14 In Circuit Emulation...

Page 4: ...CGM Clock Descriptions 4 4 4 3 1 CLK32 Clock Signal 4 4 4 3 2 PLLCLK Clock Signal 4 4 4 3 2 1 PLLCLK Initial Power up Sequence 4 5 4 3 2 2 PLL Frequency Selection 4 6 4 3 2 3 PLLCLK Frequency Selection Programming Example 4 6 4 3 2 4 Programming Considerations When Changing Frequencies 4 7 4 4 CGM Programming Model 4 8 4 4 1 PLL Control Register 4 8 4 4 2 PLL Frequency Select Register 4 10 4 5 Int...

Page 5: ...Register 2 6 18 6 3 7 Chip Select Control Register 3 6 20 Chapter 7 DRAM Controller 7 1 Introduction to the DRAM Controller 7 1 7 2 DRAM Controller Operation 7 3 7 2 1 Address Multiplexing 7 3 7 2 2 DTACK Generation 7 7 7 2 3 Refresh Control 7 7 7 2 4 LCD Interface 7 8 7 2 5 8 Bit Mode 7 9 7 2 6 Low Power Standby Mode 7 9 7 2 7 Data Retention During Reset 7 10 7 2 8 Data Retention Sequence 7 11 7 ...

Page 6: ...erface Configuration Register 8 15 8 3 10 LCD Polarity Configuration Register 8 16 8 3 11 LACD Rate Control Register 8 16 8 3 12 LCD Pixel Clock Divider Register 8 17 8 3 13 LCD Clocking Control Register 8 18 8 3 14 LCD Refresh Rate Adjustment Register 8 18 8 3 15 LCD Panning Offset Register 8 19 8 3 16 LCD Frame Rate Control Modulation Register 8 19 8 3 17 LCD Gray Palette Mapping Register 8 20 8...

Page 7: ... Pull up Enable Register 10 8 10 4 2 Port B Registers 10 8 10 4 2 1 Port B Direction Register 10 8 10 4 2 2 Port B Data Register 10 9 10 4 2 3 Port B Dedicated I O Functions 10 10 10 4 2 4 Port B Pull up Enable Register 10 10 10 4 2 5 Port B Select Register 10 11 10 4 3 Port C Registers 10 11 10 4 3 1 Port C Direction Register 10 12 10 4 3 2 Port C Data Register 10 12 10 4 3 3 Port C Dedicated I O...

Page 8: ...elect Register 10 30 10 4 9 Port J Registers 10 31 10 4 9 1 Port J Direction Register 10 31 10 4 9 2 Port J Data Register 10 32 10 4 9 3 Port J Dedicated I O Functions 10 32 10 4 9 4 Port J Pull up Enable Register 10 33 10 4 9 5 Port J Select Register 10 33 10 4 10 Port K Registers 10 34 10 4 10 1 Port K Direction Register 10 34 10 4 10 2 Port K Data Register 10 34 10 4 10 3 Port K Dedicated I O F...

Page 9: ... Cascaded Timers 12 4 12 1 5 1 Compare and Capture Using Cascaded Timers 12 4 12 2 Programming Model 12 6 12 2 1 Timer Control Registers 1 and 2 12 6 12 2 2 Timer Prescaler Registers 1 and 2 12 8 12 2 3 Timer Compare Registers 1 and 2 12 9 12 2 4 Timer Capture Registers 1 and 2 12 10 12 2 5 Timer Counter Registers 1 and 2 12 11 12 2 6 Timer Status Registers 1 and 2 12 12 Chapter 13 Serial Peripher...

Page 10: ...tion 14 6 14 3 3 Baud Rate Generator Operation 14 6 14 3 3 1 Divider 14 7 14 3 3 2 Non Integer Prescaler 14 7 14 3 3 3 Integer Prescaler 14 9 14 4 Programming Model 14 10 14 4 1 UART 1 Status Control Register 14 10 14 4 2 UART 1 Baud Control Register 14 12 14 4 3 UART 1 Receiver Register 14 13 14 4 4 UART 1 Transmitter Register 14 14 14 4 5 UART 1 Miscellaneous Register 14 16 14 4 6 UART 1 Non Int...

Page 11: ... Module 16 3 16 1 5 Using the A Line Insertion Unit 16 3 16 2 Programming Model 16 4 16 2 1 In Circuit Emulation Module Address Compare and Mask Registers 16 4 16 2 2 In Circuit Emulation Module Control Compare and Mask Register 16 6 16 2 3 In Circuit Emulation Module Control Register 16 8 16 2 4 In Circuit Emulation Module Status Register 16 10 16 3 Typical Design Programming Example 16 10 16 3 1...

Page 12: ...it Access CPU Bus Master 19 8 19 3 7 DRAM Write Cycle 16 Bit Access CPU Bus Master 19 10 19 3 8 DRAM Hidden Refresh Cycle Normal Mode 19 11 19 3 9 DRAM Hidden Refresh Cycle Low Power Mode 19 12 19 3 10 LCD SRAM ROM DMA Cycle 16 Bit Mode Access 1 Wait State 19 13 19 3 11 LCD DRAM DMA Cycle 16 Bit EDO RAM Mode Access LCD Bus Master 19 14 19 3 12 LCD DRAM DMA Cycle 16 Bit Fast Page Mode Access LCD Bu...

Page 13: ...ing DATA_READY Level Trigger 19 33 19 3 29 SPI 1 Master Don t Care DATA_READY 19 33 19 3 30 SPI 1 Slave FIFO Advanced by Bit Count 19 33 19 3 31 SPI 1 Slave FIFO Advanced by SS Rising Edge 19 34 19 3 32 Normal Mode Timing 19 35 19 3 33 Emulation Mode Timing 19 35 19 3 34 Bootstrap Mode Timing 19 36 Chapter 20 Mechanical Data and Ordering Information 20 1 Ordering Information 20 1 20 2 TQFP Pin Ass...

Page 14: ...xiv MC68VZ328 User s Manual ...

Page 15: ...etention for the Reset Cycle 7 10 Figure 8 1 LCD Controller Block Diagram 8 2 Figure 8 2 LCD Interface Timing for 4 2 and 1 Bit Data Widths 8 4 Figure 8 3 LCD Screen Format 8 5 Figure 8 4 Mapping Memory Data on the Screen 8 6 Figure 9 1 Interrupt Processing Flowchart 9 2 Figure 10 1 I O Port Warm Reset Timing 10 3 Figure 10 2 I O Port Operation 10 5 Figure 10 3 Interrupt Port Operation 10 15 Figur...

Page 16: ...9 12 Figure 19 10 LCD SRAM ROM DMA Cycle 16 Bit Mode Access Timing Diagram 19 13 Figure 19 11 LCD DRAM DMA Cycle 16 Bit EDO RAM Mode Access LCD Bus Master Timing Diagram 19 14 Figure 19 12 LCD DRAM DMA Cycle 16 Bit Fast Page Mode Access LCD Bus Master Timing Diagram 19 16 Figure 19 13 LCD Controller Timing Diagram Normal Mode 19 17 Figure 19 14 LCD Controller Timing Diagram Self Refresh Mode 19 18...

Page 17: ...anced by Bit Count Timing Diagram 19 33 Figure 19 32 SPI 1 Slave FIFO Advanced by SS Rising Edge Timing Diagram 19 34 Figure 19 33 Normal Mode Timing Diagram 19 35 Figure 19 34 Emulation Mode Timing Diagram 19 35 Figure 19 35 Bootstrap Mode Timing Diagram 19 36 Figure 20 1 MC68VZ328 TQFP Pin Assignments Top View 20 2 Figure 20 2 MC68VZ328 TQFP Mechanical Drawing 20 3 Figure 20 3 MC68VZ328 MAPBGA P...

Page 18: ...xviii MC68VZ328 User s Manual ...

Page 19: ...cription 6 5 Table 6 4 Chip Select Group C Base Address Register Description 6 5 Table 6 5 Chip Select Group D Base Address Register Description 6 6 Table 6 6 Chip Select Upper Group Base Address Register Description 6 6 Table 6 7 Chip Select Register A Description 6 8 Table 6 8 Chip Select Register B Description 6 10 Table 6 9 Chip Select Register C Description 6 12 Table 6 10 Chip Select Registe...

Page 20: ...4 LCD Clocking Control Register Description 8 18 Table 8 15 LCD Refresh Rate Adjustment Register Description 8 18 Table 8 16 LCD Panning Offset Register Description 8 19 Table 8 17 LCD Gray Palette Mapping Register Description 8 20 Table 8 18 PWM Contrast Control Register Description 8 20 Table 8 19 Refresh Mode Control Register Description 8 21 Table 8 20 DMA Control Register Description 8 22 Tab...

Page 21: ...t Edge Register Description 10 21 Table 10 26 Port E Direction Register Description 10 21 Table 10 27 Port E Data Register Description 10 22 Table 10 28 Port E Dedicated Function Assignments 10 22 Table 10 29 Port E Pull up Enable Register Description 10 23 Table 10 30 Port E Select Register Description 10 23 Table 10 31 Port F Direction Register Description 10 24 Table 10 32 Port F Data Register ...

Page 22: ...le 11 9 Real Time Interrupt Frequency Settings 11 12 Table 11 10 RTC Interrupt Enable Register Description 11 13 Table 11 11 Stopwatch Minutes Register Description 11 14 Table 12 1 Cascade Timer Settings 12 4 Table 12 2 Timer Control Register Description 12 6 Table 12 3 Timer Prescaler Register Description 12 8 Table 12 4 Timer Compare Register Description 12 9 Table 12 5 Timer Capture Register De...

Page 23: ...2 Period Register Description 15 9 Table 15 7 PWM 2 Pulse Width Control Register Description 15 10 Table 15 8 PWM 2 Counter Register Description 15 10 Table 16 1 ICE Module Address Compare and Mask Registers Description 16 5 Table 16 2 ICE Module Control Compare Register Description 16 6 Table 16 3 ICE Control Mask Register Description 16 6 Table 16 4 ICE Module Control Register Description 16 8 T...

Page 24: ...19 14 LCD DRAM DMA Cycle 16 Bit Fast Page Mode Access LCD Bus Master Timing Parameters 19 16 Table 19 15 LCD Controller Timing Parameters 19 18 Table 19 16 Timing Parameters for Figure 19 15 Through Figure 19 26 19 31 Table 19 17 Timing Parameters for Figure 19 27 Through Figure 19 32 19 34 Table 19 18 Timing Parameters for Figure 19 33 Through Figure 19 35 19 36 Table 20 1 MC68VZ328 Ordering Info...

Page 25: ...18 Example 6 2 Programming Example 6 21 Example 7 1 Calculating REF Field Values for Refresh Times 7 13 Example 8 1 Programming Example 8 22 Example 14 1 Sample Divisor Calculation 14 8 Example 17 1 System Initialization Programming Example 17 4 Example 17 2 Application Programming Example 17 5 Example 17 3 Using Instruction Buffers 17 6 List of Examples ...

Page 26: ...xxvi MC68VZ328 User s Manual ...

Page 27: ...organized into functional groups Chapter 3 Memory Map This chapter summarizes the memory organization programming information and registers addresses and reset values Chapter 4 Clock Generation Module and Power Control Module This chapter provides detailed information about the operation and programming of the clock generation module as well as the recommended circuit schematics for external clock...

Page 28: ...ver transmitter UART ports allow the incorporation of serial communication in existing and new designs This section describes how data is transported in character blocks using the standard start stop format It also discusses how to configure and program the UART modules Chapter 15 Pulse Width Modulator 1 and 2 This chapter describes both pulse width modulators Programming information is also provi...

Page 29: ... used to indicate a signal that is active when pulled low for example RESET Logic level one is a voltage that corresponds to Boolean true 1 state Logic level zero is a voltage that corresponds to Boolean false 0 state To set a bit or bits means to establish logic level one To clear a bit or bits means to establish logic level zero A signal is an electronic construct whose state conveys or changes ...

Page 30: ...tion module DRAM dynamic RAM FIFO first in first out ICE in circuit emulation MAP mold array process MAPBGA mold array process ball grid array MIPS million instructions per second PWM pulse width modulator RTC real time clock SIM system integration module SPI serial peripheral interface SRAM static RAM TQFP thin quad flat pack UART universal asynchronous receiver transmitter XTAL crystal ...

Page 31: ...bine to make the MC68VZ328 microprocessor attractive to many system designers Its functionality and glue logic are all optimally connected and timed with the same clock Also only the essential signals are brought out to the pins allowing the MC68VZ328 s primary packages TQFP and MAPBGA to occupy the smallest possible footprint on the circuit board To improve total system throughput and reduce comp...

Page 32: ...stem integration module SIM that incorporates many functions typically related to external array logic reducing parts counts in design with functions that include the following System configuration and programmable address mapping Glueless interface to SRAM DRAM SDRAM EPROM and flash memory Eight programmable chip selects with wait state generation logic Four programmable interrupt I Os with keybo...

Page 33: ...terrupt generation 30 ns resolution at 33 MHz system clock Timer input output pin Real time clock sampling timer Separate power supply for the RTC One programmable alarm Capability of counting up to 512 days Sampling timer with selectable frequency 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz 256 Hz 512 Hz 1 kHz Interrupt generation for digitizer sampling or keyboard debouncing LCD controller Software programmable...

Page 34: ... or 38 4 kHz external crystal for full frequency control Low power stop capabilities Modules that can be individually shut down Operation from DC to 33 MHz processor clock Operating voltage of 2 7 V to 3 3 V Compact 144 lead thin quad flat pack TQFP and MAPBGA 1 2 CPU The FLX68000 CPU in the MC68VZ328 is an updated implementation of the 68000 32 bit microprocessor architecture The main features of...

Page 35: ...0 registers can be used as index registers Figure 1 2 User Programming Model In supervisor mode the upper byte of the status register and the supervisor stack pointer SSP can also be programmed as shown in Figure 1 3 Figure 1 3 Supervisor Programming Model Supplement The status register contains the interrupt mask with seven available levels as well as an extend X negative N zero Z overflow V and ...

Page 36: ...hmetic operations binary coded decimal BCD arithmetic and expanded operations through traps Table 1 1 Address Modes Address Mode Syntax Register direct address Data register direct Address register direct Dn An Absolute data address Absolute short Absolute long xxx W xxx L Program counter relative address Relative with offset Relative with index offset d16 PC d8 PC Xn Register indirect address Reg...

Page 37: ...right NEGX Negate with extend Bcc Branch conditionally NOP No operation BCHG Bit test and change NOT One s complement BCLR Bit test and clear OR Logical OR BRA Branch always ORI OR immediate BSET Bit test and set ORI to CCR OR immediate to condition codes BSR Branch to subroutine ORI to SR OR immediate to status register BTST Bit test PEA Push effective address CHK Check register against bounds RE...

Page 38: ... source for the internal clock generation module CGM The output frequency can be adjusted by writing to the CGM frequency select register The CGM can be disabled to shut down the system clock divider chain for maximum power saving while the real time clock RTC and DRAM controller remain active The power control module can be configured to control the CPU cycles to optimize power consumption The po...

Page 39: ...ler provides a glueless interface for either 8 bit or 16 bit DRAM It supports EDO RAM Fast Page Mode and synchronous DRAM The DRAM controller provides row address strobe RAS and column address strobe CAS signals for up to a maximum of two banks of DRAM In addition to controlling DRAM the DRAM controller supports access for LCD controller burst accesses See Chapter 7 DRAM Controller for more inform...

Page 40: ... has an 8 bit prescaler to allow a programmable clock input frequency to be derived from the system clock The two timers can also be cascaded together as one 32 bit timer This module is described in detail in Chapter 12 General Purpose Timers 1 3 11 Serial Peripheral Interfaces SPI The MC68VZ328 contains two serial peripheral interface SPI modules SPI 1 and SPI 2 The serial peripheral interfaces a...

Page 41: ...0xFFFC0000 to 0xFFFCFFFF is covered by the EMUCS signal and primarily dedicated to the emulator debug monitor However the EMUCS signal can be used to select the monitor ROM or system I O port Keep in mind that if the monitor ROM is selected the system must boot up in emulator mode Refer to Chapter 16 In Circuit Emulation for more details 1 3 15 Bootstrap Mode The bootstrap mode is designed to allo...

Page 42: ...1 12 MC68VZ328 User s Manual Modules of the MC68VZ328 ...

Page 43: ...illustrated in Figure 2 1 on page 2 2 The MC68VZ328 uses a standard M68000 bus to communicate with on chip and external peripherals This single continuous bus exists both on and off the chip CPU read cycles to internal memory mapped registers of the device are invisible on the external bus but write cycles to internal or external memory mapped locations are visible ...

Page 44: ...PE3 DWE UCLK PE4 RXD1 PE5 TXD1 PE6 RTS1 PE7 CTS1 PJ0 MISO PJ1 MOSI PJ2 SPICLK1 PJ3 SS PJ4 RXD2 PJ5 TXD2 PJ6 RTS2 PJ7 CTS2 PK0 DATA_READY PWMO2 M S SPI with FIFO 16 Bit Timer Ports C F K Port E Ports J K LCD Controller Master SPI UART with IRDA1 0 UART Voltage Regulator System Integration Module 8 16 Bit 68000 Bus Interface Clock Synthesizer Power Control Real Time Clock Interrupt Controller Port F...

Page 45: ...D7 IRQ5 PF1 9 9 LCD controller PCIO LACD PC7 LCLK PC6 LLP PC5 LFLM PC4 LD 7 4 PK 7 4 LD 3 0 PC 3 0 LCON TRAST PF0 13 13 UART1 PEIO UART2 PJIO PE4 RXD1 PE5 TXD1 PE6 RTS1 PE7 CTS1 PJ4 RXD2 PJ5 TXD2 PJ6 RTS2 PJ7 CTS2 8 8 Timer PBIO TOUT TIN PB6 1 1 Pulse width modulator PBIO PWMO1 PB7 PM5 DATA_READY PWMO2 1 1 Master SPI PEIO config urable SPI PJIO PKIO SPITXD PE0 SPIRXD PE1 SPICLK2 PE2 PJ0 MOSI PJ1 M...

Page 46: ...equency crystal The MC68VZ328 microprocessor supports both a 32 768 kHz and a 38 4 kHz crystal frequency For a 32 768 kHz input the internal phase locked loop generates a PLLCLK signal that passes through two prescalers and the resulting output DMACLK and SYSCLK clock is 16 58 MHz Figure 2 2 illustrates how a crystal is usually connected to the MC68VZ328 For specific circuit design values see Figu...

Page 47: ...ddress lines 19 17 A 23 20 PF 6 3 Address bits 23 20 or Port F bits 6 3 These address lines are multiplexed with Port F These signals default to address functions after reset 2 5 Data Bus Signals The flexible data bus interface design of the MC68VZ328 microprocessor allows programming of the lower byte of the data bus in an 8 bit only system to operate as general purpose I O signals In sleep mode ...

Page 48: ...face Signals on page 14 3 This pin defaults to GPIO input pulled high BUSW DTACK PG0 Bus Width Data Transfer Acknowledge or Port G bit 0 BUSW is the default bus width for the CSA0 signal The DTACK signal is the external input data acknowledge signal The MC68VZ328 microprocessor will latch the BUSW signal at the rising edge of the RESET signal Its mode will determine the default bus width for CSA0 ...

Page 49: ...e MSB of the panel displays pixel 0 0 For these panels the connection between the MC68VZ328 s LCD data bus and the LCD panel s data bus may have a reversed bit significance For a 4 bit LCD panel of this type connect the MC68VZ328 s LD0 signal to the LCD panel s data bit 3 and then connect LD1 to LCD data 2 LD2 to LCD data 1 and LD3 to LCD data 0 The four pins can also be programmed as I O ports fr...

Page 50: ...rDA LED These pins default to GPIO input pulled high RTS1 PE6 RTS2 PJ6 UART 1 and UART 2 Request to Send or Port E bit 6 and Port J bit 6 RTS indicates that it is ready to receive data by asserting this pin low This pin would be connected to the far end transmitter s CTS pin When the receiver detects a pending overrun it negates this pin These pins default to GPIO input pulled high CTS1 PE7 CTS2 P...

Page 51: ...SPICLK1 PJ2 SPI Clock or Port J bit 2 SPICLK1 is the master clock output slave clock input signal for SPI In polarity 0 mode this signal is low while the serial peripheral interface master is idle In polarity 1 mode this signal is high during idle This pin defaults to GPIO input pulled high SS PJ3 SPI Slave Select or Port J bit 3 SS is the master output slave input chip select signal This pin defa...

Page 52: ...ead cycles In continuous page mode RAS is held low until a page miss refresh required or RAS duration time out During an RAS low period there may be other memory access cycles and if OE is used to enable the DRAM data output DRAM will drive data producing bus contention Therefore a dedicated output enable DMOE is required connecting to DRAM if continuous page mode is enabled Using this mode will m...

Page 53: ...hich is described in Chapter 16 In Circuit Emulation For normal operation this pin must be pulled high during system reset or left unconnected After system reset this pin defaults to an EMUIRQ function in normal or emulation mode EMUIRQ is an active low level 7 interrupt input signal EMUBRK PG5 Emulator Breakpoint or Port G bit 5 During system reset a logic low of this input signal will put the MC...

Page 54: ...2 12 MC68VZ328 User s Manual In Circuit Emulation ICE Signals ...

Page 55: ...s sorted by address or Table 3 2 on page 3 8 which is sorted alphabetically by register name Figure 3 1 MC68VZ328 System Memory Map User s Memory Map Monitor Program MC68VZ328 Emulator Monitor 0xFFFFF000 0xFFFC0000 0xFFFDFFFF System Memory Register Supervisor Memory Map Program Data Defined by User Memory 512 Mbyte Reserved 0x1FFFFFFF 0xFFFFFDff Bootstrap 0xFFFFFF00 0xFFFFFfff ...

Page 56: ... base register 0x0000 6 4 0xFFFFF104 CSGBC 16 Chip select group C base register 0x0000 6 4 0xFFFFF106 CSGBD 16 Chip select group D base register 0x0000 6 4 0xFFFFF108 CSUGBA 16 Chip select upper group address register 0x0000 6 6 0xFFFFF10A CSCR 16 Chip select control register 0x0000 6 16 0xFFFFF110 CSA 16 Group A chip select register 0x00B0 6 8 0xFFFFF112 CSB 16 Group B chip select register 0x0000...

Page 57: ... Port C select register 0xFF 10 11 0xFFFFF418 PDDIR 8 Port D direction register 0x00 10 16 0xFFFFF419 PDDATA 8 Port D data register 0xFF 10 16 0xFFFFF41A PDPUEN 8 Port D pull up enable register 0xFF 10 16 0xFFFFF41B PDSEL 8 Port D select register 0xF0 10 16 0xFFFFF41C PDPOL 8 Port D polarity register 0x00 10 16 0xFFFFF41D PDIRQEN 8 Port D interrupt request enable register 0x00 10 16 0xFFFFF41E PDK...

Page 58: ...rt K pull up pull down enable register 0xFF 10 36 0xFFFFF443 PKSEL 8 Port K select register 0xFF 10 36 0xFFFFF448 PMDIR 8 Port M direction register 0x00 10 37 0xFFFFF449 PMDATA 8 Port M data register 0x20 10 38 0xFFFFF44A PMPUEN 8 Port M pull up pull down enable regis ter 0x3F 10 39 0xFFFFF44B PMSEL 8 Port M select register 0x3F 10 40 0xFFFFF500 PWMC1 16 PWM unit 1 control register 0x0020 15 4 0xF...

Page 59: ...PITXD 16 SPI unit 1 transmit data register 0x0000 13 5 0xFFFFF704 SPICONT1 16 SPI unit 1 control status register 0x0000 13 6 0xFFFFF706 SPIINTCS 16 SPI unit 1 interrupt control status register 0x0000 13 8 0xFFFFF708 SPITEST 16 SPI unit 1 test register 0x0000 13 10 0xFFFFF70A SPISPC 16 SPI unit 1 sample period control register 0x0000 13 11 0xFFFFF800 SPIDATA2 16 SPI unit 2 data register 0x0000 13 1...

Page 60: ... 0x0000 8 13 0xFFFFFA1C LCWCH 16 LCD cursor width and height register 0x0101 8 14 0xFFFFFA1F LBLKC 8 LCD blink control register 0x7F 8 14 0xFFFFFA20 LPICF 8 LCD panel interface configuration register 0x00 8 15 0xFFFFFA21 LPOLCF 8 LCD polarity configuration register 0x00 8 16 0xFFFFFA23 LACDRC 8 LACD rate control register 0x00 8 16 0xFFFFFA25 LPXCD 8 LCD pixel clock divider register 0x00 8 17 0xFFF...

Page 61: ... DRAMMC 16 DRAM memory configuration register 0x0000 7 12 0xFFFFFC02 DRAMC 16 DRAM control register 0x0000 7 14 0xFFFFFC04 SDCTRL 16 SDRAM control register 0x003C 7 16 0xFFFFFC06 SDPWDN 16 SDRAM power down register 0x0000 7 18 0xFFFFFC80 RES Reserved 0xFFFFFD00 ICEMACR 32 ICEM address compare register 0x00000000 16 4 0xFFFFFD04 ICEMAMR 32 ICEM address mask register 0x00000000 16 4 0xFFFFFD08 ICEMC...

Page 62: ...r 0x0000 6 6 DAYALARM 0xFFFFFB1C 16 RTC day alarm register 0x0000 11 8 DAYR 0xFFFFFB1A 16 RTC day count register 0x0xxx 11 6 DMACR 0xFFFFFA39 8 DMA control register 0x62 8 22 DRAMC 0xFFFFFC02 16 DRAM control register 0x0000 7 14 DRAMMC 0xFFFFFC00 16 DRAM memory configuration register 0x0000 7 12 EMUCS 0xFFFFF118 16 Emulation chip select register 0x0060 6 16 HMARK 0xFFFFF91C 16 UART unit 2 FIFO hal...

Page 63: ...uration register 0x00 8 15 LPOLCF 0xFFFFFA21 8 LCD polarity configuration register 0x00 8 16 LPOSR 0xFFFFFA2D 8 LCD panning offset register 0x00 8 19 LPXCD 0xFFFFFA25 8 LCD pixel clock divider register 0x00 8 17 LRRA 0xFFFFFA29 8 LCD refresh rate adjustment register 0xFF 8 18 LSSA 0xFFFFFA00 32 LCD screen starting address register 0x00000000 8 10 LVPW 0xFFFFFA05 8 LCD virtual page width register 0...

Page 64: ... 0x00 10 16 PDKBEN 0xFFFFF41E 8 Port D keyboard enable register 0x00 10 16 PDPOL 0xFFFFF41C 8 Port D polarity register 0x00 10 16 PDPUEN 0xFFFFF41A 8 Port D pull up enable register 0xFF 10 16 PDSEL 0xFFFFF41B 8 Port D select register 0xF0 10 16 PEDATA 0xFFFFF421 8 Port E data register 0xFF 10 21 PEDIR 0xFFFFF420 8 Port E direction register 0x00 10 21 PEPUEN 0xFFFFF422 8 Port E pull up enable regis...

Page 65: ...448 8 Port M direction register 0x00 10 37 PMPUEN 0xFFFFF44A 8 Port M pull up pull down enable register 0x3F 10 39 PMSEL 0xFFFFF44B 8 Port M select register 0x3F 10 40 PWMC1 0xFFFFF500 16 PWM unit 1 control register 0x0020 15 4 PWMC2 0xFFFFF510 16 PWM unit 2 control register 0x0000 15 8 PWMCNT1 0xFFFFF505 8 PWM unit 1 counter register 0x00 15 7 PWMCNT2 0xFFFFF516 16 PWM unit 2 counter register 0x0...

Page 66: ...14 SPIINTCS 0xFFFFF706 16 SPI unit 1 interrupt control status register 0x0000 13 8 SPIRXD 0xFFFFF700 16 SPI unit 1 receive data register 0x0000 13 4 SPISPC 0xFFFFF70A 16 SPI unit 1 sample period control register 0x0000 13 11 SPITEST 0xFFFFF708 16 SPI unit 1 test register 0x0000 13 10 SPITXD 0xFFFFF702 16 SPI unit 1 transmit data register 0x0000 13 5 STPWCH 0xFFFFFB12 8 Stopwatch minutes register 0...

Page 67: ...neous register 0x0000 14 16 UMISC2 0xFFFFF918 16 UART unit 2 miscellaneous register 0x0000 14 16 URX1 0xFFFFF904 16 UART unit 1 receiver register 0x0000 14 13 URX2 0xFFFFF914 16 UART unit 2 receiver register 0x0000 14 13 USTCNT1 0xFFFFF900 16 UART unit 1 status control register 0x0000 14 10 USTCNT2 0xFFFFF910 16 UART unit 2 status control register 0x0000 14 10 UTX1 0xFFFFF906 16 UART unit 1 transm...

Page 68: ...3 14 MC68VZ328 User s Manual Programmer s Memory Map ...

Page 69: ...ughout the MC68VZ328 integrated processor The frequency of all clock signals except the low frequency reference are individually selectable through software control The MC68VZ328 has four different power modes to provide optimum power efficiency The PCM controls the power consumption of the CPU by applying clock signals to the CPU at reduced burst widths For maximum power savings the MC68VZ328 can...

Page 70: ...clock for the LCD controller SYSCLK Used by most modules including the CPU LCDCLK Used as reference by the LCD The distribution of the clock signals generated by the CGM is shown in Table 4 1 With the exception of the CLK32 signal the frequency of the clock signals can be individually programmed Table 4 1 CGM Clock Signal Distribution Used by or Available To CLK32 SYSCLK DMACLK LCDCLK CLKO PF2 pin...

Page 71: ...K is controlled by the prescaler select 2 PRESC2 bit in the PLLCR The DMACLK signal is applied to the LCD controller in the MC68VZ328 and also serves as the clock source for the LCD clock divider and the SYSCLK divider The output of the LCD clock divider is LCDCLK whose frequency is controlled by the LCD clock selection LCDCLK field in the PLLCR The LCDCLK signal is only used by the LCD controller...

Page 72: ... load capacitance CL PCB stray capacitance Cstray measured or approximated and DragonBall input capacitance Cdbvz 1 0 pf according to the following formula CL Cstray Cdbvz C1 C2 C1 C2 Eqn 4 1 Typical design values are C1 C2 20 pf The user should consult the crystal manufacturer for appropriate circuit layout and circuit values The CLK32 clock signal is unique in that while the other clock sources ...

Page 73: ...sors The length of the delay 1 2 s is an approximate value and should only be used as a starting point The RESET pin input is a Schmitt trigger device with a threshold of 1 4 V high and 1 0 V low NOTE On power up the RESET signal should be deasserted after the crystal has energized and its output has stabilized as shown in Figure 4 3 While most crystal oscillators typically operate with a value of...

Page 74: ...he default multiplier value is 2024 Using any multiplier equal to or greater than 794 decimal allows changing the PLLCLK in 32 768 kHz or 38 4 kHz steps The minimum PC and QC values are P 0x1B and Q 0x04 which produce a multiplier of 794 decimal 4 3 2 3 PLLCLK Frequency Selection Programming Example Example 4 1 on page 4 7 demonstrates the recommended sequence of events to change the PLLCLK freque...

Page 75: ...MR restore the Interrupt Mask Register rts PLL is now at the new frequency The PLL has reacquired lock and SYSCLK is stable 4 3 2 4 Programming Considerations When Changing Frequencies The following information is provided to assist the user in programming the MC68VZ328 When programming the SYSCLK frequency ensure that it does not exceed 33 161216 MHz at any time Since the PRESC1 and PRESC2 bits a...

Page 76: ...elect This field controls the divide ratio used by the LCD clock divider to convert DMACLK to LCDCLK This field can be changed at any time 000 DMACLK 2 001 DMACLK 4 010 DMACLK 8 011 DMACLK 16 1xx DMACLK 1 100 after reset SYSCLK SEL Bits 10 8 System Clock Select This field controls the divide ratio used by the SYSCLK divider to convert DMACLK to SYSCLK This field can be changed at any time 000 DMAC...

Page 77: ...y of the PLL output from the initiation of the wake up until an output is available Since the delay time is calculated by counting CLK32 cycles the frequency of the crystal oscillator will determine the amount of delay that each setting produces See Table 4 3 for delay settings Table 4 3 WKSEL Field PLLCR Delay Settings Bits 1 0 CLK32 Periods Delay in Milliseconds 32 768 kHz Delay in Milliseconds ...

Page 78: ...clock is immediately enabled allowing the CPU to service the request The DMA controller is not affected by the PCM having full access to the bus while the CPU is idle keeping the LCD screen refreshed BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 CLK32 PROT QC PC TYPE r rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 0x0347 This bit can be set by software but is cleared...

Page 79: ... 100 percent Software can then change the burst width to a lower value and the clock is applied to the CPU in bursts The burst width register can be programmed for burst widths of any value between zero thirty firsts and thirty one thirty firsts This effectively produces a system clock with a variable burst width and power dissipation between 3 percent and 100 percent in incremental steps of 3 per...

Page 80: ...the PLLCR allowing sufficient time to execute the stop instruction When a wake up event occurs the PLL is enabled and after a delay determined by the WKSEL setting in the PLLCR the PLLCLK begins as do as the rest of the clocks in the divider chain of the CGM The CPU executes an interrupt service routine for the level of the wake up event After the rte instruction in the wake up service routine the...

Page 81: ...As described previously a width setting of 11111 represents 31 periods of CLK32 or approximately 1 ms In this example the width setting in the PCTLR is 00011 The clock bursts are applied at a burst width of three thirty firsts or approximately at 10 percent on time making the CPU active about 10 percent of the time The remainder of the time the CPU is in doze mode When a wake up event occurs CPUCL...

Page 82: ...the CPU in bursts or disables it When this bit is high a masked interrupt can disable the power control module 0 Power control is disabled default 1 Power control is enabled Reserved Bits 6 5 Reserved These bits are reserved and should remain set to 0 WIDTH Bits 4 0 Width This field controls the width of the CPU clock bursts in increments of one thirty first While this bit is set to 1 and the PCM ...

Page 83: ...and watchdog protection The system control register contains status bits that allow exception handler code to interrogate the cause of both exceptions and resets The bus time out monitor and the watchdog timer provide system protection The bus time out monitor generates a bus error when a bus cycle is not terminated by the DTACK signal after 128 clock cycles have elapsed 5 1 1 Bus Monitors and Wat...

Page 84: ... cleared by writing a 1 writing a 0 has no effect 0 A bus error timer time out did not occur 1 A bus error timer time out has occurred because an undecoded address space has been accessed or because a write protect or privilege violation has occurred WPV Bit 6 Write Protect Violation This status bit indi cates that a write protect violation has occurred If a write protect violation occurs and the ...

Page 85: ...The on chip registers are mapped at 0xFFFFF000 0xFFFFFFFF and 0xXXFFF000 0xXXFFFFF XX don t care Reserved Bit 1 Reserved This bit is reserved and reads 0 WDTH8 Bit 0 8 Bit Width Select This control bit allows the D 7 0 pins to be used for Port A input output 0 Not an 8 bit system 1 8 bit system Table 5 1 System Control Register Description Continued Name Description Setting ...

Page 86: ...or UART 2 s UCLK for UCLK pin output When UCLK of UART 1 and UART 2 is configured as input this bit is don t care and UCLK pin is an input signal 0 UCLK pin is connected to UART 1 1 UCLK pin is connected to UART 2 P 1 0 Bits 3 2 PWM Outputs Logic Operation These bits select the logical combination for final PWM pin output 00 8 bit PWM out only default 01 16 bit PWM out only 10 Logic OR of both PWM...

Page 87: ...r r r r r r RESET 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0x5600 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 SWID TYPE r r r r r r r r r r r r r r r r RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 5 3 ID Register Description Name Description Setting CHIPID Bits 31 24 Chip ID Field This field contains the chip identification number for the DragonBall series MPU See description MASKID Bits 23 16 Mask...

Page 88: ...4 I O Drive Control Register Description Name Description Setting Reserved Bits 15 13 Reserved Do not use these bits AB Bit 12 Address Bus Signals I O Drive Control It should be noted that A 23 20 are controlled by the PF bit 0 I O drive current for each pin is 2 mA 1 I O drive current for each pin is 4 mA DB Bit 11 Upper Data Bus Signals I O Drive Control The lower data bus is controlled by the P...

Page 89: ...when decoded from the programming information in the chip select register Group C CSC0 CSC1 and Group D CSD0 CSD1 chip selects are unique in that they can also be programmed as row address strobe RAS0 RAS1 and column address strobe CAS0 CAS1 for the DRAM interface For details refer to Section 7 3 2 DRAM Control Register on page 7 14 and Section 6 3 3 Chip Select Registers in this chapter Each memo...

Page 90: ... when an address is matched and after the AS signal goes low The base address and address mask registers are used in the compare logic to generate an address match The byte size of the matching block must be a power of two and the base address must be an integer multiple of this size Therefore an 8K block size must begin on an 8K boundary and a 64K block size can only begin on a 64K boundary Each ...

Page 91: ...isters can be read or written in a zero wait state cycle Except for CSA0 and EMUCS all chip select signals are disabled by default The data bus width BSW field of the chip select option register enables 16 and 8 bit data bus widths for each of the 16 chip select ranges The initial bus width for the boot chip select can be selected by placing a logic 0 or 1 on the BUSW pin at reset to specify the w...

Page 92: ...ter selects the starting address for the chip select address range The GBAx field is compared to the address on the address bus to determine if the group is decoded The chip select base address must be set according to the size of the corresponding chip select signals of the group For example if CSA1 and CSA0 are each assigned a 2 Mbyte memory space the CSGBA register must be set in a 4 Mbyte spac...

Page 93: ...elect base address must be set according to the size of the corresponding chip select signals of the group Reserved Bit 0 Reserved This bit is reserved and should be set to 0 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 GB C2 8 GB C2 7 GB C2 6 GB C2 5 GB C2 4 GB C2 3 GB C2 2 GB C2 1 GB C2 0 GB C1 9 GB C1 8 GB C1 7 GB C1 6 GB C1 5 GB C1 4 TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0...

Page 94: ...rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 6 5 Chip Select Group D Base Address Register Description Name Description Setting GBDx Bits 15 1 Group D Base Address These bits select the high order bits 28 14 of the starting address for the chip select range The chip select base address must be set according to the size of the corresponding chip select signals of the group Reserved B...

Page 95: ...GBA 31 29 Bits 6 4 MSB for Chip Select C The upper most sig nificant bits for chip select group C base address The value will be ignored if UGEN is disabled Enter value for bits 31 29 of chip select regis ter C Reserved Bit 3 Reserved This bit is reserved and should be set to 0 DGBA 31 29 Bits 2 0 MSB for Chip Select D The upper most sig nificant bits for chip select group D base address The value...

Page 96: ...tem Control Register on page 5 2 for more information 0 Read write 1 Read only Reserved Bits 14 9 Reserved These bits are reserved and should be set to 0 FLASH Bit 8 Flash Memory Support When enabled this bit provides support for flash memory by forc ing the LWE UWE signal to go active after chip select Note This bit is used for expanded memory size for CSD when the DRAM bit in the CSD register is...

Page 97: ...or 16 Mbyte for CSCx and CSDx 010 512K 128K for CSCx and CSDx 011 1 Mbyte 256K for CSCx and CSDx 100 2 Mbyte 512K for CSCx and CSDx 101 4 Mbyte 1 Mbyte for CSCx and CSDx 110 8 Mbyte 2 Mbyte for CSCx and CSDx 111 16 Mbyte 4 Mbyte for CSCx and CSDx Note Large DRAM size selection requires the DSIZ3 bit in the chip select control register to be set EN Bit 0 Chip Select Enable This write only bit enabl...

Page 98: ... BETEN bit of the SCR is set See Section 5 2 1 System Control Register on page 5 2 for more information 0 Supervisor user 1 Supervisor only ROP Bit 13 Read Only for Protected Memory Block This bit sets the protected mem ory block to read only Otherwise read and write accesses are allowed If you write to a read only area you will get a bus error 0 Read write 1 Read only UPSIZ Bits 12 11 Unprotected...

Page 99: ...ts 3 1 Chip Select Size This field determines the memory range of the chip select For CSAx and CSBx the chip select size is between 128K and 16 Mbyte For CSCx and CSDx the chip select size is between 32K and 16 Mbyte 000 128K 32K or 8 Mbyte for CSCx and CSDx 001 256K 64K or 16 Mbyte for CSCx and CSDx 010 512K 128K for CSCx and CSDx 011 1 Mbyte 256K for CSCx and CSDx 100 2 Mbyte 512K for CSCx and C...

Page 100: ... BETEN bit of the SCR is set See Section 5 2 1 System Control Register on page 5 2 for more information 0 Supervisor user 1 Supervisor only ROP Bit 13 Read Only for Protected Memory Block This bit sets the protected mem ory block to read only Otherwise read and write accesses are allowed If you write to a read only area you will get a bus error 0 Read write 1 Read only UPSIZ Bits 12 11 Unprotected...

Page 101: ...ts 3 1 Chip Select Size This field determines the memory range of the chip select For CSAx and CSBx the chip select size is between 128K and 16 Mbyte For CSCx and CSDx the chip select size is between 32K and 16 Mbyte 000 128K 32K or 8 Mbyte for CSCx and CSDx 001 256K 64K or 16 Mbyte for CSCx and CSDx 010 512K 128K for CSCx and CSDx 011 1 Mbyte 256K for CSCx and CSDx 100 2 Mbyte 512K for CSCx and C...

Page 102: ...result in a bus error if the BETEN bit of the SCR is set See Section 5 2 1 System Con trol Register on page 5 2 for more informa tion 0 Supervisor user 1 Supervisor only ROP Bit 13 Read Only for Protected Memory Block This bit sets the protected memory block to read only Otherwise read and write accesses are allowed If you write to a read only area you will get a bus error 0 Read write 1 Read only...

Page 103: ...states 010 4 WS0 wait states 011 6 WS0 wait states 100 8 WS0 wait states 101 10 WS0 wait states 110 12 WS0 wait states 111 External DTACK When using the external DTACK signal you must select DTACK function in Port G WS0 is the DWS0 CWS0 BWS0 or AWS0 bit in the CSCTRL1 register SIZ Bits 3 1 Chip Select Size This field determines the memory range of the chip select For CSAx and CSBx the chip select ...

Page 104: ...emory space and extended size for DRAM See the following register display and Table 6 12 on page 6 17 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 WS3 1 TYPE rw rw rw RESET 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0x0060 Table 6 11 Emulation Chip Select Register Description Name Description Setting Reserved Bits 15 7 Reserved These bits are reserved and should be set to 0 WS3 1 Bits 6 4 Wait State This fi...

Page 105: ...hip select register for the wait state set ting DWSO Bit 11 CSD Wait State Bit 0 This bit is the lowest significant bit of the CSD wait state register Refer to Table 6 10 on page 6 14 on the chip select register D for the wait state setting CWSO Bit 10 CSC Wait State Bit 0 This bit is the lowest significant bit of the CSC wait state register Refer to Table 6 9 on page 6 12 on the chip select regis...

Page 106: ...is is the most significant bit for UPSIZ 2 0 when the EUPEN bit is set For information on calculating unprotected memory size see Example 6 1 Reserved Bit 1 Reserved This bit is reserved and should be set to 0 BUPS2 Bit 0 UPSIZ Bit 2 CSB Register This is the most significant bit for UPSIZ 2 0 when the EUPEN bit is set For information on calculating unprotected memory size see Example 6 1 BIT 15 14...

Page 107: ...e CPU from being asserted before a valid address is present from the CPU the early ASB can be pro grammed so it is delayed before going to the chip select generator This bit must be pro grammed appropriately when early ASB is chosen as the early cycle detection signal 0 Use selectable delay chain as the delay processing method 1 Use negative CPU edge synchronization as the delay processing method ...

Page 108: ...e Trim for LCD SRAM Access When this bit is set one additional wait state is added to the LCD SRAM access cycle For example if the wait state is set to zero all CPU accesses require 4 cycles to complete the chip select signal to SRAM lasts 2 5 CPU clock cycles and 2 cycles are used for LCD access When LCWS is enabled the LCD access is delayed the access is increased from 2 to 3 clock cycles 0 No a...

Page 109: ...register PBSel equ PORTBASE 0x0B port B select register Initialization START move b 0x00 PBSel disable PortB select chip selects move w 0x0000 BASEA set base address 0x0000000 move w 0x8081 CSA read only 16 bit 0 wait state 128K move w 0x2000 BASEB set base address 0x4000000 move w 0x0093 CSB read write 16 bit 1 wait state 256K move w 0x2040 BASEC set base addrs 0x4080000 move w 0x0191 CSC read wr...

Page 110: ...6 22 MC68VZ328 User s Manual Programming Model ...

Page 111: ...CAS signals for up to a maximum of two banks of DRAM In addition to controlling DRAM the DRAM controller provides support for LCD controller burst accesses The DRAM controller has the following features 68000 CPU zero wait state operation support CAS before RAS refresh cycles and self refresh mode DRAM support 8 and 16 bit port DRAM support Fast Page Mode and EDO RAM modes or synchronous burst for...

Page 112: ...ler Figure 7 1 DRAM Controller Block Diagram Data SYSCLK Control Address CLK32 CSD0 CSD1 MD 15 0 MPU Interface Mode Refresh DRAM DRAM Address Control DTACK RAS0 A 31 1 RAS1 CAS0 CAS1 Control Control Control Signal Control Page Access from LCD 8 Bit Port from SIM ...

Page 113: ...tions are provided in Table 7 1 on page 7 4 The MC68VZ328 s DRAM controller uses PA 8 1 as the column addresses for MD 7 0 and then allows software to select either PA0 or PA9 for column address MD8 Similar address selection options are provided for MD9 and MD10 column addresses the MD0 row address and the row addresses MD8 through MD12 The MD 12 0 signals share the same address pins that output a...

Page 114: ...2 PA23 PA24 Column Address Options PA0 PA1 PA9 PA0 PA10 PA0 PA11 PA12 PA13 PA22 PA23 PA24 Column Address Options for SDRAM PA12 PA9 2 Pin A9 MD8 has column address options of PA1 and PA9 for SDRAM The COL8 bit bit 5 of the DRAM memory configuration register 0xFFFFFC00 determines the selection When COL8 0 PA9 is selected When COL8 1 PA1 is selected PA1 0 PA203 PA22 3 Pin A12 MD11 has column address...

Page 115: ...mn Address Options 16 Bit PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 X X 0 PA20 Column Address Options 8 Bit PA0 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA1 X 0 PA20 Note X don t care Table 7 3 64 Mbit SDRAM 256 16 Bit and 512 8 Bit Page Size SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BS0 BS1 VZ Pins A1 MD 0 A2 MD 1 A3 MD 2 A4 MD 3 A5 MD 4 A6 MD 5 A7 MD 6 A8 MD 7 A9 MD 8 A10 MD 9 A11 MD 10 A12 MD 11 A13 MD 12 A14 ...

Page 116: ... Column Address Options 8 Bit PA 0 PA 2 PA 3 PA 4 PA 5 PA 6 PA 7 PA 8 PA 9 PA 1 0 PA22 X PA23 Note X don t care Table 7 5 256 Mbit SDRAM 512 16 Bit and 1024 8 Bit Page Size SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BS 0 BS 1 VZ Pins A1 MD 0 A2 MD 1 A3 MD 2 A4 MD 3 A5 MD 4 A6 MD 5 A7 MD 6 A8 MD 7 A9 MD 8 A10 MD 9 A11 MD 10 A12 MD 11 A13 MD 12 A15 MD 14 A16 MD 15 Row Address Options PA 11...

Page 117: ...her priority NOTE The value of N can be 1 4 clocks depending on the collision overlap of the refresh cycle and CPU bus cycle 7 2 3 Refresh Control During normal operation the MC68VZ328 DRAM cycles are distributed evenly over the refresh period The DRAM refresh rate requirement may vary between different DRAM chips Users can program the REF field in the DRAM configuration register DRAMMC to select ...

Page 118: ... LCD controller cycle starts refresh will go first and N more clocks will be added to the first access N is the number of system clock cycles required for refresh Therefore in EDO RAM mode for a 4 1 1 1 cycle the access will become 4 N 1 1 1 When consecutive LCD controller burst accesses cross a memory page boundary the DRAM controller will hold the LCD controller that is negating the internal DTA...

Page 119: ...he address multiplexer options in the DRAMMC register 7 2 6 Low Power Standby Mode If DRAM that supports self refresh mode is being used the RM bit in the DRAMC register can be programmed to self refresh mode before entering sleep mode The DRAM controller will generate one CAS before RAS cycle negate RAS and CAS for the required precharge time then assert CAS before RAS and continue to assert them...

Page 120: ...AM controller itself has a special design to support this feature Figure 7 3 illustrates the timing for data retention Figure 7 3 Data Retention for the Reset Cycle 32 kHz DRAM Sync with System Clock 15 6 µs Sleep with No SYSCLK Reprogram DRAM Controller External RESET Hardware reset Internal RESET DRAM Refresh DRAM Reset Port CSCx CSDx Reset System Clock Chip Selects I O Port CSCx CSDx CPCRESET ...

Page 121: ...AS refresh cycle 4 The external RESET signal continues asserting 5 The external RESET signal is negated 6 The internal RESET signal is negated 7 The DRAM controller terminates the burst CAS before RAS refresh cycle 8 The internal CPCRESET signal is generated for 16 clocks to reset the DRAM controller and the CSCx and CSDx port signals 9 The chip is now reset 10 The core processor programs the DRAM...

Page 122: ...Bits 15 14 Row Address MD12 This field selects the row address bit for multiplexed address MD12 00 PA10 01 PA21 10 PA23 11 Not valid ROW0 Bits 13 12 Row Address MD0 This field selects the row address bit for multiplexed address MD0 00 PA11 01 PA22 10 PA23 11 Not valid ROW11 Bit 11 Row Address MD11 This bit selects the row address bit for multiplexed address MD11 0 PA20 1 PA22 ROW10 Bit 10 Row Addr...

Page 123: ...f REF 1 the refresh rate 32 kHz If REF 2 to 15 the refresh rate 32 kHz REF 1 When CLK 1 the system clock is used for refresh control The refresh rate SYSCLK 32 REF 1 REF Bits 4 0 Refresh Cycle This value determines the refresh rate for the DRAM controller The refresh rate can be calculated using the equation shown in Example 7 1 See description Table 7 6 DRAM Memory Configuration Register Descript...

Page 124: ...dditional clock 2 clocks transfer 01 2 additional clocks 3 clocks transfer 10 3 additional clocks 4 clocks transfer 11 4 additional clocks 5 clocks transfer CLK Bit 11 Clock This bit selects the clock that is provided to the refresh timer 0 CLK32 Period A is selected 1 System clock Period B is selected EDO Bit 10 Extended Data Out This bit selects the page access mode for LCD DMA DRAM accesses Thi...

Page 125: ...stem clock or 120 ns 16 58 MHz system clock 0 Normal RAS precharge 2 system clocks 1 Extended RAS precharge for slower DRAM devices 4 system clocks LPR Bit 2 Low Power Refresh Enable This bit is used to control the refresh during low power modes 0 Disable low power refresh mode 1 Enable low power refresh mode RST Bit 1 Reset Burst Refresh Enable This bit controls the refresh type during RESET asse...

Page 126: ... miss condition 0 SDRAM not in continuous page mode 1 SDRAM in continuous page mode Reserved Bit 13 Reserved This bit is reserved and must be set to 0 RE Bit 12 Refresh Enable This bit enables the refresh cycle for SDRAM 0 SDRAM Refresh cycle not enabled 1 SDRAM refresh cycle enabled IP Bit 11 Initiate All Bank Precharge Command Setting this bit triggers the precharge command for all banks of SDRA...

Page 127: ...tency This bit selects the latency for SDRAM from refresh to active cycle 0 3 Clock counts 1 6 Clock counts Table 7 9 SDRAM Bank Address Programming Examples Application BNKADDH BNKADDL Remarks Make all SDRAM appear as one single bank 11 11 None Two banks of SDRAM for exam ple 16 Mbyte 00 11 Choose PA20 as bank selection address Four banks of SDRAM for example 64 Mbyte 01 10 Choose PA22 and PA21 a...

Page 128: ... immediately when the DRAM controller is not sending a command writ ing data or reading data with the SDRAM 0 APEN disabled 1 APEN enabled PDEN Bit 14 SDRAM Precharged Power down Enable The bit is set to make the SDRAM Chip Enable signal go low when the DRAM controller is not sending a command after the SDRAM is precharged for a certain time The time depends on the value in PDTOUT 3 0 0 PDEN disab...

Page 129: ... list describes the features of the LCD controller Both system and display memory that is shared so that dedicated video memory is not required Standard panel interface for industry standard LCD drivers Support for single nonsplit monochrome screen and color STN LCD panels through preprocessing of image data with software Fast fly by type 16 bit wide burst DMA screen refresh transfers from system ...

Page 130: ... the cursor logic block The input is synchronized with the fast DMA clock while the output is synchronized to the relatively slow LCD pixel clock The cursor control logic when enabled is used to generate a block shaped cursor on the display screen The height and width of the cursor can be changed as long as a number between 1 and 31 is used The cursor may also be completely black or reversed video...

Page 131: ...can be programmed to be an active high or active low signal in software See Section 8 3 10 LCD Polarity Configuration Register for more information LACD The LCD Alternate Crystal Direction output signal is toggled to alternate the crystal polarization on the panel This signal can be programmed to toggle for a period of 1 to 16 frames The LACD signal will toggle after a preprogrammed number of FLM ...

Page 132: ...8 2 2 1 Format of the LCD Screen The screen width and height of the LCD panel are programmable through software Figure 8 3 on page 8 5 illustrates the relationship between the portion of a large graphics file displayed on the screen and the actual page The units in the figure are measured in pixel counts LD1 0 0 2 0 4 0 LD0 1 0 3 0 5 0 m 4 0 m 2 0 m 3 0 m 1 0 38 0 40 0 39 0 41 0 2 bit LCD data bus...

Page 133: ... shows the bottom of the page but it is not used by the LCD controller 8 2 2 2 Format of the Cursor To define the position of the hardware cursor the LCD controller maintains a vertical line counter YCNT to keep track of the current pixel s vertical position YCNT in conjunction with XCNT the horizontal pixel counter specifies the screen position of the pixel data being processed When the pixel fal...

Page 134: ...its per pixel mode circuitry inside the LCD controller generates intermediate grayscale tones on the LCD panel by adjusting the density of ones and zeroes that appear over the frames The LCD controller can generate 16 simultaneous grayscale levels out of a palette consisting of 16 shades The two levels between black and white can be selected using the information in Table 8 1 on page 8 7 Use the L...

Page 135: ...sixteenths and one This flexible mapping scheme allows optimizing the visual effect for the specific panel or application during a four level grayscale display mode NOTE The Controlling Frame Rate Modulation function available in previous versions of the DragonBall integrated processor is not available in the MC68VZ328 Table 8 1 Grey Palette Density Gray Code Hex Density Density in Decimal 0 0 0 1...

Page 136: ...rate of 50 Hz to 70 Hz the pixel bits in the memory will be read and transferred to the corresponding pixels on the screen To minimize bus obstruction a burst type and fly by transfer is required Each cycle is evenly distributed across the time frame Every time the internal line buffer needs data it asserts the BR signal to request the bus from the core Once the core grants the bus BG is asserted ...

Page 137: ...rnal RAM using the LP and FRM pulse 8 2 5 1 Entering Self Refresh Mode Setting the self refresh register bit 7 to 1 means that the LSCLK and LD will remain 0 when the end of the frame is reached The LP and FRM pulse continue as in normal mode but there are no pulses on either the LSCLK or LD 8 2 5 2 Canceling Self Refresh Mode Setting the self refresh register bit 7 to 0 means that the normal mode...

Page 138: ...S A20 SS A19 SS A18 SS A17 SSA 16 TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSA 15 SS A14 SS A13 SS A12 SS A11 SS A10 SS A9 SS A8 SS A7 SS A6 SS A5 SS A4 SS A3 SS A2 SS A1 TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 8 2 LCD Screen Starting Address R...

Page 139: ...VP8 VP7 VP6 VP5 VP4 VP3 VP2 VP1 TYPE rw rw rw rw rw rw rw rw RESET 1 1 1 1 1 1 1 1 0xFF Table 8 3 LCD Virtual Page Width Register Description Name Description Setting VPx Bits 7 0 Virtual Page Width 8 1 These bits specify the virtual page width of the LCD panel in terms of word count The virtual page width is the virtual width in pixels divided by 16 for a black and white display by 8 for a 4 gray...

Page 140: ... 4 3 2 1 BIT 0 YM8 YM7 YM6 YM5 YM4 YM3 YM2 YM1 YM0 TYPE rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0x01FF Table 8 5 LCD Screen Height Register Description Name Description Setting Reserved Bits 15 9 Reserved These bits are reserved and should be set to 0 YMx Bits 8 0 Maximum Height 8 0 These bits represent the height of the LCD panel in the number of pixels which is equal to ...

Page 141: ...horizontal starting position X in terms of pixel count from 0 to XMAX See description BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 CYP 8 CYP 7 CYP 6 CYP 5 CYP 4 CYP 3 CYP 2 CYP 1 CYP0 TYPE rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 8 7 LCD Cursor Y Position Register Description Name Description Setting Reserved Bits 15 9 Reserved These bits are reserved and shou...

Page 142: ...play The settings for the bits in the register are listed in Table 8 9 on page 8 15 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 CW4 CW3 CW2 CW1 CW0 CH4 CH3 CH2 CH1 CH0 TYPE rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0x0101 Table 8 8 LCD Cursor Width and Height Register Description Name Description Setting Reserved Bits 15 13 Reserved These bits are reserved and should be...

Page 143: ...t 7 Blink Enable This bit determines if the cursor will blink or remain steady 1 Blink is enabled 0 Blink is disabled default BDx Bits 6 0 Blink Divisor 6 0 These bits determine if the cursor will toggle once per a specified number of internal frame pulses plus one The half period may be as long as 2 seconds See description BIT 7 6 5 4 3 2 1 BIT 0 PBSIZ1 0 GS1 0 TYPE rw rw rw rw RESET 0 0 0 0 0 0 ...

Page 144: ... the register are listed in Table 8 12 on page 8 17 BIT 7 6 5 4 3 2 1 BIT 0 LCKPOL FLMPOL LPPOL PIXPOL TYPE rw rw rw rw RESET 0 0 0 0 0 0 0 0 0x00 Table 8 11 LCD Polarity Configuration Register Description Name Description Setting Reserved Bits 7 4 Reserved These bits are reserved and should be set to 0 LCKPOL Bit 3 LCD Shift Clock Polarity This bit controls the polarity of the active edge of the ...

Page 145: ...clock ACDx Bits 6 0 Alternate Crystal Direction Control 6 0 These bits represent the ACD toggle rate control code The LACD signal will toggle once every 1 to 128 FLM LP cycles based on the value specified in this register The actual number of FLM cycles is the value pro grammed plus one Shorter cycles tend to give better results See description BIT 7 6 5 4 3 2 1 BIT 0 PCD5 PCD4 PCD3 PCD2 PCD1 PCD0...

Page 146: ...egister display The settings for the bits in the register are listed in Table 8 15 LRRA LCD Refresh Rate Adjustment Register 0x FF FFFA28 BIT 7 6 5 4 3 2 1 BIT 0 LCDON Unused TYPE rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0x00 Table 8 14 LCD Clocking Control Register Description Name Description Setting LCDON Bit 7 LCD Control This bit enables the LCD controller Default is off 0 Disable the LC...

Page 147: ...date XMAX screen width in number of pixels RRA hexadecimal value stored in the LRRA register YMAX screen height in number of pixels PXCD hexadecimal value stored in the LPXCD register LCDCLK_PERIOD refer to Section 4 4 1 PLL Control Register on page 4 8 for setting LCDCLK period See descrip tion BIT 7 6 5 4 3 2 1 BIT 0 POS3 POS2 POS1 POS0 TYPE rw rw rw rw RESET 0 0 0 0 0 0 0 0 0x00 Table 8 16 LCD ...

Page 148: ...PWMR PWM Contrast Control Register 0x FF FFFA36 BIT 7 6 5 4 3 2 1 BIT 0 G23 G22 G21 G20 G13 G12 G11 G10 TYPE rw rw rw rw rw rw rw rw RESET 1 0 0 0 0 1 0 0 0x84 Table 8 17 LCD Gray Palette Mapping Register Description Name Description Setting G23 G20 Bits 7 4 Grayscale 23 20 These bits represent one of the two gray scale shading densities See description G13 G10 Bits 3 0 Grayscale 13 10 These bits ...

Page 149: ... 0 This bit controls the pulse width of the built in pulse width modulator which controls the contrast of the LCD screen See Chapter 15 Pulse Width Modulator 1 and 2 for more information See description BIT 7 6 5 4 3 2 1 BIT 0 REF_ON TYPE rw RESET 0 0 0 0 0 0 0 0 0x00 Table 8 19 Refresh Mode Control Register Description Name Description Setting REF_ON Bit 7 Self Refresh On Setting this bit enables...

Page 150: ...s starts at A80000 move w 240 FFFA08 LCD horizontal size is 240 move w 159 FFFA0A LCD vertical size is 160 move b 40 FFFA05 4 level gray and 320 pixels wide image move b 09 FFFA20 LCD panel data bus is 4 bits 4 level gray move b 3 FFFA25 pixel clock rate equal 1 4 of LCDCLK from PLL move b 10 FFFA29 refresh rate adjustment move b 03 FFFA2D shift picture by 3 pixels move b 82 FFFA27 switch on LCDC ...

Page 151: ...errupt level 6 Timer unit 1 level 6 Timer unit 2 configurable from level 1 to 6 Pulse width modulator unit 1 level 6 Pulse width modulator unit 2 configurable from level 1 to 6 IRQ5 external interrupt pen level 5 Serial peripheral interface unit 1 configurable from level 1 to 6 Serial peripheral interface unit 2 level 4 UART unit 1 level 4 UART unit 2 configurable from level 1 to 6 Software watchd...

Page 152: ...f the interrupt controller External devices must not respond to IACK cycles with a vector because the response is solely the responsibility of the interrupt controller On the MC68VZ328 steps 2 and 4 operate exactly as they would on other M68000 devices which are described in the M68000 User s Manual In step 2 the CPU s status register SR is available to mask interrupts globally to determine which ...

Page 153: ...n the MC68VZ328 and the vector numbers for user interrupts are configurable For additional information regarding exception processing see the M68000 Family Programmer s Reference Manual Table 9 1 Exception Vector Assignment Vector Number Address Number Space1 Assignment Hex Decimal Decimal Hex 0 0 0 000 SP Reset initial SSP2 1 1 4 004 SP Reset initial PC 2 2 8 008 SD Bus error 3 3 12 00C SD Addres...

Page 154: ...e should be programmed to contain the initial SSP and PC The initial SSP should point to a RAM space and the initial PC should point to the startup code within the EPROM ROM space so that the processor can execute the startup code to bring up the system 1A 26 104 068 SD Level 2 interrupt autovector 1B 27 108 06C SD Level 3 interrupt autovector 1C 28 112 070 SD Level 4 interrupt autovector 1D 29 11...

Page 155: ... pending interrupt is posted to the CPU Before the CPU responds to this interrupt the status register is copied internally and then the supervisor bit of the CPU status register is set placing the processor into supervisor mode The CPU then responds with an interrupt acknowledge cycle in which the lower 3 bits of the address bus reflect the priority level of the current interrupt The interrupt con...

Page 156: ... core You can program the upper 5 bits of the interrupt vector register IVR to allow the interrupt vector number to point to any address in the exception vector table However many of the vector addresses are assigned to the core s internal exceptions and cannot be reused This leaves only a small range of address space 0x100 to 0x400 to which you can configure the IVR to locate user interrupt vecto...

Page 157: ...interrupt acknowledge cycle the lower 3 bits encoded from the interrupt level are combined with the upper 5 bits to form an 8 bit vector number The CPU uses the vector number to generate a vector address During system startup this register should be configured so that the MC68VZ328 s external and internal interrupts can be handled properly by their software handlers If an interrupt occurs before t...

Page 158: ...t logic level high In edge triggered mode negative polarity produces an interrupt when the signal goes from logic level high to logic level low Positive polarity generates an interrupt when the signal goes from logic level low to logic level high 0 Negative polarity 1 Positive polarity POL3 Bit 13 Polarity Control 3 This bit controls interrupt polarity for the IRQ3 signal In level sensitive mode n...

Page 159: ...iggered mode a 1 must be written to the IRQ6 bit in the interrupt status register to clear this interrupt When this bit is low IRQ6 is a level sensitive interrupt In this case the external source of the interrupt must be cleared 0 Level sensitive interrupt 1 Edge sensitive interrupt POL5 Bit 7 Polarity Control 5 This bit controls interrupt polarity for the IRQ5 signal In level sensitive mode negat...

Page 160: ...iption Settings Reserved Bits 31 24 Reserved These bits are reserved and should be set to 0 MEMIQ Bit 23 Mask Emulator Interrupt When set this bit indicates that the EMUIRQ pin and in circuit emulation breakpoint interrupt functions are masked It is set to 1 after reset These inter rupts are level 7 interrupts to the CPU 0 Enable EMUIRQ interrupt 1 Mask EMUIRQ interrupt MRTI Bit 22 Timer for Real ...

Page 161: ...errupt It is set to 1 after reset 0 Enable INT0 interrupt 1 Mask INT0 interrupt MPWM1 Bit 7 Mask PWM 1 Interrupt Setting this bit masks the PWM 1 interrupt It is set to 1 after reset 0 Enable pulse width modulator 1 interrupt 1 Mask pulse width modulator 1 interrupt MKB Bit 6 Mask Keyboard Interrupt Setting this bit masks the key board interrupt It is set to 1 after reset 0 Enable keyboard interru...

Page 162: ...0C BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BIT 16 EMI Q RTI SPI 1 IRQ 5 1R Q6 IRQ 3 IRQ 2 IRQ 1 TYPE rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000000 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 PW M2 UA RT 2 INT 3 INT 2 INT 1 INT 0 PW M1 KB TM R2 RT C WD T UA RT 1 TM R1 SPI 2 TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0...

Page 163: ...IRQ3 sig nal is set to be a level sensitive interrupt the source of the interrupt must first be cleared If IRQ3 is set to be an edge triggered interrupt the interrupt must be cleared by writing a 1 to this bit Writing a 0 to this bit has no effect 0 No level 3 interrupt is pending 1 A level 3 interrupt is pending IRQ2 Bit 17 Interrupt Request Level 2 This bit when set indicates that an external de...

Page 164: ... page 10 16 for details 0 No INT1 interrupt is pending 1 An INT1 interrupt is pending INT0 Bit 8 External INT0 Interrupt This bit when set indicates that a level 4 interrupt has occurred It is usually for a keyboard interface When it is programmed as edge triggered it can only be cleared by writing a 1 to the port D register See Section 10 4 5 Port D Registers on page 10 16 for details 0 No INT0 i...

Page 165: ...needed TMR1 Bit 1 Timer 1 Interrupt Status This bit indicates that a timer 1 event has occurred This is a level 6 interrupt 0 No timer 1 event occurred 1 A timer 1 event has occurred SPI2 Bit 0 SPI Unit 2 Interrupt Status When set this bit indicates an inter rupt event from SPI unit 2 0 No SPI 2 interrupt is pending 1 An SPI 2 interrupt is pending Table 9 6 Interrupt Status Register Description Co...

Page 166: ...hese bits are reserved and should be set to 0 EMIQ Bit 23 Emulator Interrupt Pending When set this bit indicates that the in circuit emulation module or EMUIRQ pin is requesting an interrupt on level 7 This bit can be generated from three interrupt sources two breakpoint interrupts from the in circuit emulation module and an external interrupt from EMUIRQ which is an active low edge sensi tive int...

Page 167: ...rupt the interrupt must be cleared by writing a 1 to this bit Writing a 0 to this bit has no effect 0 No level 2 interrupt is pending 1 A level 2 interrupt is pending IRQ1 Bit 16 Interrupt Request Level 1 This bit when set indicates that an external device is requesting an interrupt on level 1 If the IRQ1 sig nal is set to be a level sensitive interrupt the source of the interrupt must first be cl...

Page 168: ...interrupt 1 A PWM 1 interrupt is pending KB Bit 6 Keyboard Interrupt Request This bit when set indicates that there is a level 4 interrupt event from a keyboard pending 0 No keyboard interrupt is pending 1 A keyboard interrupt is pending TMR2 Bit 5 Timer 2 Interrupt Pending This bit indicates that a timer 2 event has occurred This is a level 4 interrupt 0 No timer 2 event occurred 1 A timer 2 even...

Page 169: ...ing interrupt source to generate different interrupt levels After reset each of these four interrupts is set to the default level indicated TIMER2IRQ level 3 UART2IRQ level 5 PWM2IRQ level 3 SPI2IRQ level 6 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 SPI1_LEVEL UART2_LEVEL PWM2_LEVEL TMR2_LEVEL TYPE rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 1 0x6533 Table 9 8 Interr...

Page 170: ...ouch panel inputs In most of these systems the setup involves a touch panel connected to an analog to digital A D converter and the microprocessor To achieve low power consumption and system performance the A D is usually connected to an interrupt of the microprocessor When the touch panel is touched the CPU is activated through the interrupt and the A D starts collecting data On the MC68VZ328 IRQ...

Page 171: ...not be controlled A few exceptions to this rule are noted in the programming information about the specific ports 10 1 Port Configuration With the exception of Port A every port is multiplexed with at least one other dedicated I O function Several ports have pins that can be configured for one of several dedicated I O functions Table 10 1 on page 10 2 shows the I O functions available for each por...

Page 172: ...t default state is determined by the register reset values of the I O port registers Register reset values are found in Table 3 1 on page 3 2 and Table 3 2 on page 3 8 Ports B and M maintain their previous programmed states on reset assertion and retain their states during the Reset Assertion Time Length The previous states of Ports B and M before reset assertion are for the purposes of the figure...

Page 173: ... active during the system Reset Assertion Time Length This feature allows the DRAM controller to maintain the refresh cycles for DRAM during unpredictable reset time lengths thereby preserving DRAM data after reset negation More details appear in Chapter 7 DRAM Controller 10 2 2 Power up Reset The power up reset sequence of events is the same as for a warm reset except that the I O states of Port ...

Page 174: ...tatus During the Reset Assertion Time Length I O Ports Warm Reset Power up Reset A Resets to default state Resets to default state B Maintains previous state Unknown state C Resets to default state Resets to default state D Resets to default state Resets to default state E Resets to default state Resets to default state F Resets to default state Resets to default state G Resets to default state Re...

Page 175: ...w to the I O module is the D1 bit of Port E This signal s function is the SPI s RXD SPIRXD signal In this case SPIRXD is input only thus the chip negates the output enable from module line and the data from module line is not disabled see Figure 10 2 The data to module signal is connected to the SPIRXD input of the SPI 10 3 3 Operating a Port as GPIO While the SELx bit is set if the DIRx bit of th...

Page 176: ...registers are general purpose 8 bit I O registers They consist of the following Port A direction register PADIR Port A data register PADATA Port A pull up enable register PAPUEN Port A functions either as a GPIO PA 7 0 or the lower data byte of the data bus D 7 0 Port A can be used as PA 7 0 only when the MC68VZ328 is operating as an 8 bit system by setting the WDTH8 bit in the system control regi...

Page 177: ...these bits are read regardless of whether they are configured as input or output The settings for the bit positions are shown in Table 10 5 PADATA Port A Data Register 0x FF FFF401 BIT 7 6 5 4 3 2 1 BIT 0 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 TYPE rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0x00 Table 10 4 Port A Direction Register Description Name Description Setting DIRx Bits 7 0 Direction T...

Page 178: ...al line connects to an external pin Each bit on Port B is individually configured 10 4 2 1 Port B Direction Register The Port B direction register controls the direction input or output of the line associated with the PBDATA bit position When the data bit is assigned to a dedicated I O function the direction bits are ignored The settings for the bit positions are shown in Table 10 7 on page 10 9 B...

Page 179: ...on the pin is reported when these bits are read regardless of whether they are configured as input or output BIT 7 6 5 4 3 2 1 BIT 0 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 TYPE rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0x00 Table 10 7 Port B Direction Register Description Name Description Setting DIRx Bits 7 0 Direction These bits control the direction of the pins They reset to 0 With the exc...

Page 180: ...he Port B register even though the pin is assigned to the GP timers Refer to Section 12 1 4 TOUT TIN PB6 Pin on page 12 3 for details about the operation and programming of the pin The PWMO1 signal is an output signal resulting from the logical operation AND or OR of both the PWM 1 and PWM 2 modules Bits 3 2 P 1 0 of the peripheral control register PCR select the logic used for combining the modul...

Page 181: ...ister connects to an external pin As with the other ports each bit on Port C is individually configured BIT 7 6 5 4 3 2 1 BIT 0 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 TYPE rw rw rw rw rw rw rw rw RESET 1 1 1 1 1 1 1 1 0xFF Table 10 10 Port B Pull up Enable Register Description Name Description Setting PUx Bits 7 0 Pull up These bits enable the pull up resis tors on the port 0 Pull up resistors are disabl...

Page 182: ...Lx bits are high While the DIRx bits are high output the Dx bits control the pins While the DIRx bits are low input the Dx bits report the signal driving the pins The Dx bits can be written at any time Bits that are configured as inputs will BIT 7 6 5 4 3 2 1 BIT 0 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 TYPE rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0x00 Table 10 12 Port C Direction Register ...

Page 183: ...ntrols the pull down resistors for each line in Port C The settings for the bit positions are shown in Table 10 15 PCPDEN Port C Pull down Enable Register 0x FF FFF412 Table 10 14 Port C Dedicated Function Assignments Bit GPIO Function Dedicated I O Function 0 Data bit 0 LD0 1 Data bit 1 LD1 2 Data bit 2 LD2 3 Data bit 3 LD3 4 Data bit 4 LFLM 5 Data bit 5 LLP 6 Data bit 6 LCLK 7 Data bit 7 LACD BI...

Page 184: ... are shown in Table 10 16 PCSEL Port C Select Register 0x FF FFF413 BIT 7 6 5 4 3 2 1 BIT 0 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 TYPE rw rw rw rw rw rw rw rw RESET 1 1 1 1 1 1 1 1 0xFF Table 10 16 Port C Select Register Description Name Description Setting SELx Bits 7 0 Select These bits select whether the internal chip function or I O port signals are connected to the pins 0 The dedicated func...

Page 185: ...ort D generates nine interrupt signals Eight of these interrupts are generated by the bits of each port One bit is the logical OR result of all eight bits which is applied to the MC68VZ328 interrupt controller as a level 4 keyboard interrupt KB in the interrupt status register See Section 9 6 4 Interrupt Status Register on page 9 12 for more details Pad Data Register Pull up Enable Register Pad Bu...

Page 186: ... 10 4 5 1 Port D Direction Register The Port D direction register controls the direction input or output of the line associated with the PDDATA bit position When the data bit is assigned to a dedicated I O function by the PDSEL register the DIR bits are ignored The settings for the PDDIR bit positions are shown in Table 10 17 PDDIR Port D Direction Register 0x FF FFF418 BIT 7 6 5 4 3 2 1 BIT 0 DIR...

Page 187: ...data written to each cannot be accessed until the corresponding pin is configured as an output The actual value on the pin is reported when these bits are read regardless of whether they are configured as input or output BIT 7 6 5 4 3 2 1 BIT 0 D7 D6 D5 D4 D3 D2 D1 D0 TYPE rw rw rw rw rw rw rw rw RESET 1 1 1 1 1 1 1 1 0xFF Actual bit value depends on external circuits connected to pin Table 10 18 ...

Page 188: ...y the POLx bits of the PDPOL register All of the interrupt signals in the table can be used as system wake up interrupts except for the edge interrupt on INT 3 0 Edge interrupts on INT 3 0 can only interrupt the CPU when the system is awake The INT 3 0 signals are all level 4 interrupts but IRQx has its own level Any combination of Port D signals and OR negative logic can be selected to generate k...

Page 189: ...rt D Polarity Register 0x FF FFF41C BIT 7 6 5 4 3 2 1 BIT 0 SEL7 SEL6 SEL5 SEL4 TYPE rw rw rw rw RESET 1 1 1 1 0 0 0 0 0xF0 Table 10 21 Port D Select Register Description Name Description Setting SELx Bits 7 4 Select These bits select whether the internal chip function or I O port signals are connected to the pins 0 The dedicated function pins are connected 1 The I O port function pins are connect...

Page 190: ...Interrupt Request Edge Register The polarity of the rising or falling edge is selected by the POLx bits It should be noted that the edge level interrupt for INT 3 0 cannot be used for system wake up The level sensitive interrupt should be used The settings for the bit positions of PDIRQEG are shown in Table 10 25 on page 10 21 BIT 7 6 5 4 3 2 1 BIT 0 IQEN3 IQEN2 IQEN1 IQEN0 TYPE rw rw rw rw RESET ...

Page 191: ...ction by the PESEL register the DIR bits are ignored The settings for the bit positions of the PEDIR register are shown in Table 10 26 PEDIR Port E Direction Register 0x FF FFF420 BIT 7 6 5 4 3 2 1 BIT 0 IQEG3 IQEG2 IQEG1 IQEG0 TYPE rw rw rw rw RESET 0 0 0 0 0 0 0 0 0x00 Table 10 25 Port D Interrupt Request Edge Register Description Name Description Setting Reserved Bits 7 4 Reserved These bits ar...

Page 192: ...sed until the corresponding pin is configured as an output The actual value on the pin is reported when these bits are read regardless of whether they are configured as input or output 10 4 6 3 Port E Dedicated I O Functions The eight PEDATA lines are multiplexed with the SPI and UART dedicated I O signals whose assignments are shown in Table 10 28 BIT 7 6 5 4 3 2 1 BIT 0 D7 D6 D5 D4 D3 D2 D1 D0 T...

Page 193: ...t 7 CTS1 BIT 7 6 5 4 3 2 1 BIT 0 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 TYPE rw rw rw rw rw rw rw rw RESET 1 1 1 1 1 1 1 1 0xFF Table 10 29 Port E Pull up Enable Register Description Name Description Setting PUx Bits 7 0 Pull up These bits enable the pull up resis tors on the port 0 Pull up resistors are disabled 1 Pull up resistors are enabled BIT 7 6 5 4 3 2 1 BIT 0 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 S...

Page 194: ...t F direction register controls the direction input or output of the line associated with the PFDATA bit position When the data bit is assigned to a dedicated I O function by the PFSEL register the DIR bits are ignored The settings for the PFDIR bit positions are shown in Table 10 31 PFDIR Port F Direction Register 0x FF FFF428 BIT 7 6 5 4 3 2 1 BIT 0 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 TYPE r...

Page 195: ...ten at any time Bits that are configured as inputs will accept the data but the data written to each cannot be accessed until the corresponding pin is configured as an output The actual value on the pin is reported when these bits are read regardless of whether they are configured as input or output BIT 7 6 5 4 3 2 1 BIT 0 D7 D6 D5 D4 D3 D2 D1 D0 TYPE rw rw rw rw rw rw rw rw RESET 1 1 1 1 1 1 1 1 ...

Page 196: ...LK clock output of the internal CGM This signal is provided for external reference The output can be disabled to reduce power consumption and electromagnetic emission This signal defaults to a PF2 input signal See Section 4 2 CGM Operational Overview on page 4 3 for more information about this signal Bit 7 is used for the chip select signal CSA1 See Section 6 2 Chip Select Operation on page 6 2 fo...

Page 197: ...1 0xFF Table 10 34 Port F Pull up Pull down Enable Register Description Name Description Setting PU7 Bit 7 Pull up This bit enables the pull up resistor on the port 0 Pull up resistor is disabled 1 Pull up resistor is enabled PDx Bits 6 3 Pull down These bits enable the pull down resistors on the port 0 Pull down resistors are disabled 1 Pull down resistors are enabled PUx Bits 2 0 Pull up These b...

Page 198: ...or output of the line associated with the PGDATA bit position When the data bit is assigned to a dedicated I O function by the PGSEL register the DIR bits are ignored The settings for the PGDIR bit positions are shown in Table 10 36 PGDIR Port G Direction Register 0x FF FFF430 10 4 8 2 Port G Data Register The settings for the bit positions of the PGDATA register are shown in Table 10 37 on page 1...

Page 199: ...on page 10 28 for information about setting the bits in the PGDIR register 10 4 8 3 Port G Dedicated I O Functions The six PGDATA lines are multiplexed with the dedicated I O signals whose assignments are shown in Table 10 38 BIT 7 6 5 4 3 2 1 BIT 0 D5 D4 D3 D2 D1 D0 TYPE rw rw rw rw rw rw RESET 0 0 1 1 1 1 1 1 0x3F Actual bit value depends on external circuits connected to pin Table 10 37 Port G ...

Page 200: ...pins default to the dedicated function except bit 3 which has an I O function To ensure normal operation the EMUIRQ and EMUBRK pins must stay high or not be connected during system reset Otherwise the chip will enter emulation mode When bits 2 5 are used as I O the emulation mode cannot be used during development and debugging Once development is complete bits 2 5 can be used as I O in the final s...

Page 201: ...red The settings for the bit positions are shown in Table 10 41 PJDIR Port J Direction Register 0x FF FFF438 BIT 7 6 5 4 3 2 1 BIT 0 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 TYPE rw rw rw rw rw rw RESET 0 0 0 0 1 0 0 0 0x08 Table 10 40 Port G Select Register Description Name Description Setting Reserved Bits 7 6 Reserved These bits are reserved and should be set to 0 SELx Bits 5 0 Select These bits select wh...

Page 202: ...e pin is reported when these bits are read regardless of whether they are configured as input or output 10 4 9 3 Port J Dedicated I O Functions The eight PJDATA lines are multiplexed with the dedicated I O signals whose assignments are shown in Table 10 43 BIT 7 6 5 4 3 2 1 BIT 0 D7 D6 D5 D4 D3 D2 D1 D0 TYPE rw rw rw rw rw rw rw rw RESET 1 1 1 1 1 1 1 1 0xFF Actual bit value depends on external ci...

Page 203: ...SEL register are shown in Table 10 45 PJSEL Port J Select Register 0x FF FFF43B 7 Data bit 7 CTS2 BIT 7 6 5 4 3 2 1 BIT 0 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 TYPE rw rw rw rw rw rw rw rw RESET 1 1 1 1 1 1 1 1 0xFF Table 10 44 Port J Pull up Enable Register Description Name Description Setting PUx Bits 7 0 Pull up These bits enable the pull up resis tors on the port 0 Pull up resistors are disabled 1 P...

Page 204: ...iated with the PKDATA bit position When the data bit is assigned to a dedicated I O function by the PKSEL register the DIR bits are ignored The settings for the PKDIR register bit positions are shown in Table 10 46 PKDIR Port K Direction Register 0x FF FFF440 10 4 10 2 Port K Data Register The settings for the PKDATA register bit positions are shown in Table 10 47 on page 10 35 BIT 7 6 5 4 3 2 1 B...

Page 205: ...onfigured as input or output 10 4 10 3 Port K Dedicated I O Functions The eight PKDATA lines are multiplexed with the dedicated I O signals whose assignments are shown in Table 10 48 BIT 7 6 5 4 3 2 1 BIT 0 D7 D6 D5 D4 D3 D2 D1 D0 TYPE rw rw rw rw rw rw rw rw RESET 0 0 0 0 1 1 1 1 0x0F Actual bit value depends on external circuits connected to pin Table 10 47 Port K Data Register Description Name ...

Page 206: ... up Pull down Enable Register 0x FF FFF442 10 4 10 5 Port K Select Register The select register PKSEL determines if a bit position in the data register PKDATA is assigned as a GPIO or to a dedicated I O function The settings for the PKSEL register bit positions are shown in Table 10 50 PKSEL Port K Select Register 0x FF FFF443 BIT 7 6 5 4 3 2 1 BIT 0 PD7 PD6 PD5 PD4 PU3 PU2 PU1 PU0 TYPE rw rw rw r...

Page 207: ...output of the line associated with the PMDATA bit position When the data bit is assigned to a dedicated I O function by the PMSEL register the DIR bits are ignored The settings for the PMDIR register bit positions are shown in Table 10 51 PMDIR Port M Direction Register 0x FF FFF448 BIT 7 6 5 4 3 2 1 BIT 0 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 TYPE rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0x00 Table 10 51 ...

Page 208: ...ill accept the data but the data written to each cannot be accessed until the corresponding pin is configured as an output The actual value on the pin is reported when these bits are read regardless of whether they are configured as input or output BIT 7 6 5 4 3 2 1 BIT 0 D5 D4 D3 D2 D1 D0 TYPE rw rw rw rw rw rw RESET 0 0 1 0 0 0 0 0 0x20 Actual bit value depends on external circuits connected to ...

Page 209: ...wn in Table 10 54 PMPUEN Port M Pull up Pull down Enable Register 0x FF FFF44A Table 10 53 Port M Dedicated I O Function Assignments Bit GPIO Function Dedicated I O Function 0 Data bit 0 SDCLK 1 Data bit 1 SDCE 2 Data bit 2 DQMH 3 Data bit 3 DQML 4 Data bit 4 SDA10 5 Data bit 5 DMOE 6 7 BIT 7 6 5 4 3 2 1 BIT 0 PU5 PD4 PD3 PD2 PD1 PD0 TYPE rw rw rw rw rw rw RESET 0 0 1 1 1 1 1 1 0x3F Table 10 54 Po...

Page 210: ...SEL Port M Select Register 0x FF FFF44B BIT 7 6 5 4 3 2 1 BIT 0 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 TYPE rw rw rw rw rw rw RESET 0 0 1 1 1 1 1 1 0x3F Table 10 55 Port M Select Register Description Name Description Setting Reserved Bits 7 6 Reserved These bits are reserved and should be set to 0 SELx Bits 5 0 Select These bits select whether the internal chip function or I O port signals are connected to...

Page 211: ... interrupts to the interrupt controller The RTC can also generate a watchdog system reset The following sections describe how each block operates and interacts with other modules in both the RTC and the MC68VZ328 Figure 11 1 Real Time Clock Module Simplified Block Diagram Real Time Interrupt Real Time Interrupt Prescaler Control Registers RTC Interrupt Watchdog Interrupt Watchdog Reset 1 Pulse per...

Page 212: ...d the entire RTC can also be enabled and disabled In the following descriptions it is assumed that the real time clock enable RTCEN bit in the real time control register is set default enabling the RTC 11 1 1 Prescaler The prescaler divides the CLK32 reference clock down to 1 pulse per second resulting in a signal labeled 1HZ After an initial power up the CLK32 signal is always available even when...

Page 213: ...utes counters When incremented the hours counter will return to zero It is the responsibility of the user to ensure the range validity of data in the TOD clock Each of the four counters may be enabled to produce an interrupt when it rolls over Upon reaching 59 the seconds and minutes counters each produce an MIN or HR interrupt if enabled the next time they are incremented Both counters reset to 0...

Page 214: ...The frequencies of the real time interrupts are shown in Table 11 9 on page 11 12 Bits RTE0 RTE7 in the RTC interrupt enable register RTCIENR enable each of the eight different predefined rates When the real time interrupt occurs it applies a level 4 interrupt to the MC68VZ328 interrupt controller The real time clock RTCEN bit in the RTCCTL or the watchdog timer EN bit in the watchdog register mus...

Page 215: ...8 17 BIT 16 HOURS MINUTES TYPE rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 X X X X X 0 0 X X X X X X 0xXXXX BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 SECONDS TYPE rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 X X X X X X 0x00XX Table 11 2 RTC Hours Minutes and Seconds Register Description Name Description Setting Reserved Bits 31 29 Reserved These bits are reserved and should be set to 0 HOURS ...

Page 216: ...rent day assumes the new value This register cannot be reset since it is used to keep the time The settings for the DAYR register are described in Table 11 3 DAYR RTC Day Counter Register 0x ff FFFB1A BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 DAYS TYPE rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0x0XXX Table 11 3 RTC Day Counter Register Description Name Description Setting Reserved Bits 15...

Page 217: ...0x00000000 Table 11 4 RTC Alarm Register Description Name Description Setting Reserved Bits 31 29 Reserved These bits are reserved and should be set to 0 HOURS Bits 28 24 Hours These bits indicate the value of the hours field in the current alarm setting This field can be set to any value between 0 and 23 Default is value 0 Reserved Bits 23 22 Reserved These bits are reserved and should be set to ...

Page 218: ...gister are described in Table 11 5 DAYALRM RTC Day Alarm Register 0x ff FFFB1C BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 DAYSAL TYPE rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 11 5 RTC Day Alarm Register Description Name Description Setting Reserved Bits 15 9 Reserved These bits are reserved and should be set to 0 DAYSAL Bits 8 0 Days Alarm This field indicat...

Page 219: ...unts up in 1 second increments When the watchdog counter counts to 10 it generates a watchdog interrupt Note Because the watchdog counter is incremented by a 1 Hz signal from the real time clock the average tolerance of the counter is 0 5 seconds Greater accuracy is obtained by polling the 1 Hz flag of the RTCISR Writing any value to these bits will reset the counter to 00 default INTF Bit 7 Inter...

Page 220: ...settings for the RTCISR register are described in Table 11 8 on page 11 11 For more information about the frequency of the RTC interrupts refer to Table 11 9 on page 11 12 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 RTCEN REFREQ TYPE rw rw RESET 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0x0080 Table 11 7 RTC Control Register Description Name Description Setting Reserved Bits 15 8 Reserved These bits are r...

Page 221: ...us Bit 2 This bit shows the status of real time interrupt 2 0 No RIS2 interrupt occurred 1 RIS2 interrupt occurred RIS1 Bit 9 Real Time Interrupt Status Bit 1 This bit shows the status of real time interrupt 1 0 No RIS1 interrupt occurred 1 RIS1 interrupt occurred RIS0 Bit 8 Real Time Interrupt Status Bit 0 This bit shows the status of real time interrupt 0 0 No RIS0 interrupt occurred 1 RIS0 inte...

Page 222: ...e interrupt has occurred SW Bit 0 Stopwatch Flag If enabled the stopwatch flag is set when the stopwatch minute count down times out 0 The stopwatch did not time out 1 The stopwatch timed out Table 11 9 Real Time Interrupt Frequency Settings Real Time Interrupt Frequency 32 768 kHz Reference Clock 38 4 kHz Reference Clock RFE7 512 Hz 1 9531 ms 600 Hz 1 6666 ms RFE6 256 Hz 3 9062 ms 300 Hz 3 3333 m...

Page 223: ...upt is enabled RIE3 Bit 11 Real Time Interrupt Enable Bit 3 This bit enables the real time interrupt 3 The frequency of this interrupt is shown in Table 11 9 on page 11 12 0 RIE3 interrupt is disabled 1 RIE3 interrupt is enabled RIE2 Bit 10 Real Time Interrupt Enable Bit 2 This bit enables the real time interrupt 2 The frequency of this interrupt is shown in Table 11 9 on page 11 12 0 RIE2 interru...

Page 224: ... minute interrupt is disabled 1 1 minute interrupt is enabled SW Bit 0 Stopwatch Interrupt Enable This bit enables the stopwatch interrupt Note The stopwatch counts down and remains at decimal 1 until it is reprogrammed If this bit is enabled with 1 decimal in the STPWCH register an interrupt will be posted on the next minute tick 0 1 minute interrupt is disabled 1 1 minute interrupt is enabled BI...

Page 225: ...imer has an 8 bit prescaler providing a programmable clock frequency derived from SYSCLK The two timers may also be cascaded together to operate as a single 32 bit timer 12 1 GP Timer Overview The two 16 bit timers Timer 1 and Timer 2 that make up the general purpose timers are identical Figure 12 1 illustrates the general purpose timer block diagram The following sections describe the operation o...

Page 226: ...rescaler setting 12 1 2 Timer Events and Modes of Operation There are two types of events that produce interrupts compare events and capture events Compare events occur when the value in the counter matches the contents of the compare register Capture events occur when a defined transition of the TOUT TIN pin is detected The counter can be programmed to run in one of two modes restart or free runn...

Page 227: ...12 1 4 TOUT TIN PB6 Pin The TOUT TIN pins are multiplexed with bit 6 of the Port B registers The Port B registers determine if the pin is assigned to the GP timers or to pin 6 of Port B the default setting as described in Section 10 4 2 3 Port B Dedicated I O Functions on page 10 10 Because the TOUT TIN PB6 is a bidirectional pin the direction of the pin is also controlled in the Port B registers ...

Page 228: ... and Timer 1 is the LSW If the direction of the pin is in DIR6 0 the TIN signal is applied to Timer 1 If the direction is out DIR6 1 the TOUT is connected to Timer 2 12 1 5 1 Compare and Capture Using Cascaded Timers When the timers are cascaded the associated compare and capture registers are not The flow diagram in Figure 12 2 on page 12 5 suggests one method for 32 bit compares using a cascaded...

Page 229: ...GP Timer Overview General Purpose Timers 12 5 Figure 12 2 Compare Routine for 32 Bit Cascaded Timers Wait on MSW MSW status bit set No LSW status bit set Set flag Yes 32 bit compare No Yes ...

Page 230: ...he compare event interrupt Selecting the prescaler clock source Enabling and disabling the GP Timer TCTL1 Timer Control Register 1 0x FF FFF600 TCTL2 Timer Control Register 2 0x FF FFF610 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 FRR CAP OM IRQEN CLKSOURCE TEN TYPE rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 FRR CAP OM I...

Page 231: ...oggle output IRQEN Bit 4 Interrupt Request Enable This bit enables an interrupt on a compare event 00 Disable the compare interrupt default 01 Enable the compare interrupt CLKSOURCE Bit 3 1 Clock Source This field controls the clock source to the prescaler The stop count freezes the counter at its current value Note To use TIN TOUT as a TIN input ensure that the SEL6 bit in the Port B select regis...

Page 232: ... rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 Not Used Prescaler TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 12 3 Timer Prescaler Register Description Name Description Setting Not used Bits 15 8 These bits are not used PRESCALER Bits 7 0 Prescaler This...

Page 233: ...FF FFF604 TCMP2 Timer Compare Register 2 0x FF FFF614 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 COMPARE TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0xFFFF BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 COMPARE TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0xFFFF Table 12 4 Timer Compare Register Descript...

Page 234: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 CAPTURE TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 CAPTURE TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 12 5 Timer Capture Register Description Name Description Setting CAPTURE Bits 15 0 Capture Value ...

Page 235: ...FFF608 TCN2 Timer Counter Register 2 0x FF FFF618 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 COUNT TYPE r r r r r r r r r r r r r r r r RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 COUNT TYPE r r r r r r r r r r r r r r r r RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 12 6 Timer Counter Register Description Name Description Setting COUNT Bits ...

Page 236: ...Register 1 0x FF FFF60A TSTAT2 Timer Status Register 2 0x FF FFF61A BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 Not Used CAPT COMP TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 Not Used CAPT COMP TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table ...

Page 237: ...figurable SPI interface module allowing the MC68VZ328 to interface with either an external SPI master or an SPI slave device 13 1 SPI 1 Overview This section discusses how SPI 1 may be used to communicate with external devices SPI 1 contains an 8 16 data in FIFO and an 8 16 data out FIFO Incorporating the DATA_READY and SS control signals enables faster data communication with fewer software inter...

Page 238: ...ternal device is a transmit only device the SPI master s output port can be ignored and used for other purposes In order to utilize the internal TxD and RxD data FIFOs two auxiliary output signals SS and DATA_READY are used for data transfer rate control The user may also program the sample period control register to a fixed data transfer rate 13 2 2 Using SPI 1 as Slave If SPI 1 is configured as ...

Page 239: ...SPI 1 This flexibility allows it to operate with most serial peripheral devices available in the marketplace 13 2 4 SPI 1 Signals The following signals are used to control SPI 1 MOSI Master Out Slave In bidirectional signal which is multiplexed with PJ0 is the TxD output signal from the data shift register when in master mode In slave mode it is the RxD input to the data shift register MISO Master...

Page 240: ...he bit position assignments for this register are shown in the following register display The settings for this register are described in Table 13 1 SPIRXD SPI 1 Receive Data Register 0x FF FFF700 BIT 7 6 5 4 3 2 1 BIT 0 DATA TYPE r r r r r r r r RESET 0 0 0 0 0 0 0 0 0x0000 Table 13 1 SPI 1 Receive Data Register Description Name Description Setting DATA Bits 7 0 Data Top of SPI 1 s RxFIFO 8 16 Th...

Page 241: ...arded and may be written with any value For example to transfer 10 bit data a 16 bit word is written to the SPITXD register and the 6 MSBs are treated as don t care and will not be shifted out In slave mode if no data is loaded to the TxFIFO zeros are shifted out serially as the TxD signal Writes to this register are ignored while the SPIEN bit in the SPI 1 control status register is clear The bit...

Page 242: ...vide SYSCLK by 256 111 Divide SYSCLK by 512 DRCTL Bits 12 11 DATA_READY Control In master mode these 2 bits select the waveform of the DATA_READY input signal In slave mode they have no effect 00 Don t care DATA_READY 01 Falling edge trigger input 10 Active low level trigger input 11 RSV MODE Bit 10 SPI 1 Mode Select This bit selects the mode of SPI 1 0 SPI 1 is slave mode 1 SPI 1 is master mode S...

Page 243: ...arity of the SCLK signal 0 Active high polarity 0 idle 1 Active low polarity 1 idle BIT COUNT Bits 3 0 Bit Count This field selects the length of the transfer A maximum of 16 bits can be trans ferred In master mode a 16 bit data word is loaded from TxFIFO to the shift register and only the least significant n bits n BIT COUNT are shifted out The next 16 bit word is then loaded to the shift registe...

Page 244: ...n of the RO bit 6 for details 0 Disable RxFIFO overflow interrupt 1 Enable RxFIFO overflow interrupt RFEN Bit 13 RxFIFO Full Interrupt Enable This bit when set allows an interrupt to be generated when there are 8 data words in the RxFIFO See the description of the RF bit 5 for details 0 Disable RxFIFO full interrupt enable 1 Enable RxFIFO full interrupt enable RHEN Bit 12 RxFIFO Half Interrupt Ena...

Page 245: ...ta words in RxFIFO 0 Less than 8 data words in RxFIFO 1 8 data words in RxFIFO RH Bit 4 RxFIFO Half Status This bit when set indi cates the contents of the RxFIFO is more than or equal to 4 data words 0 Contents of RxFIFO is less than 4 data words 1 Contents of RxFIFO is greater than or equal to 4 data words RR Bit 3 RxFIFO Data Ready Status This bit when set indicates that at least 1 data word is...

Page 246: ...3 11 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 SSTATUS RXCNT TXCNT TYPE rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 13 5 SPI 1 Test Register Description Name Description Setting Reserved Bits 15 12 Reserved These bits are reserved and should be set to 0 SSTATUS Bits 11 8 State Machine Status This field indicates the state machine status These bits are...

Page 247: ...orola s 68HC05 and 68HC11 microprocessors Figure 13 3 shows the SPI 2 block diagram Figure 13 3 SPI 2 Block Diagram BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 CSRC WAIT TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 13 6 SPI 1 Sample Period Control Register Description Name Description Setting CSRC Bit 15 Counter Clock Source This bit sel...

Page 248: ...ransfer set the ENABLE bit then in a separate write cycle set the appropriate control bits The SPI 2 module is then ready to accept data into the SPIDATA2 register which cannot be written while the SPI 2 module is disabled or busy Once the data is loaded the XCH bit is set in the SPICONT2 register which triggers an exchange The XCH bit remains set until the transfer is complete If you clear the MS...

Page 249: ... are internal to the SPI 2 module This flexibility allows it to operate with most serial peripheral devices on the market 13 5 2 SPI 2 Signals The following signals are used to control the SPI 2 module SPITXD The Transmit Data pin which is multiplexed with PE0 is the output of the shift register A new data bit is presented but it depends on whether you have selected phase or polarity SPIRXD The Re...

Page 250: ...s presented on the first SPICLK2 edge At the end of the exchange data from the peripheral is present in this register and bit 0 is the least significant bit As data is shifted MSB first outgoing data is automatically MSB justified For example if the exchange length is 10 bits the first bit presented to the external device will be bit 9 followed by the remaining bits NOTE Writes to this field are i...

Page 251: ...K by 32 100 Divide SYSCLK by 64 101 Divide SYSCLK by 128 110 Divide SYSCLK by 256 111 Divide SYSCLK by 512 Reserved Bits 12 10 Reserved These bits are reserved and should be set to 0 ENABLE Bit 9 Enable This bit enables the SPI 2 module This bit must be asserted before initiating an exchange and should be deasserted after the exchange is complete 0 The SPI 2 module is disabled 1 The SPI 2 module i...

Page 252: ...SCLK signal 0 Active high polarity 0 idle 1 Active low polarity 1 idle BIT COUNT Bits 3 0 Bit Count This field selects the length of the transfer A maximum of 16 bits can be trans ferred In master mode a 16 bit data word is loaded from the TxFIFO to the shift register and only the least significant n bits n BIT COUNT are shifted out The next 16 bit word is then loaded to the shift register In slav...

Page 253: ...ngly to compensate for the increased clock speed Because the two UART modules are nearly identical the signal nomenclature throughout this chapter uses an x suffix to represent either 1 or 2 For example TXDx represents either TXD1 or TXD2 depending on which UART is being used 14 1 Introduction to the UARTs This section describes how data is transported in character blocks using the standard start ...

Page 254: ...tions that need other bit rates a 1x clock mode is available providing a data bit clock Figure 14 1 illustrates a high level block diagram of both UART modules Figure 14 1 UART Simplified Block Diagram 14 2 Serial Operation The UART modules have two modes of operation NRZ and IrDA Section 14 2 1 NRZ Mode and Section 14 2 2 IrDA Mode describe these two modes of operation 14 2 1 NRZ Mode The nonretu...

Page 255: ...ts to standard RS 232 or infrared transceiver modules While the UART is in NRZ mode normal data is output with marks transmitted as logic high and spaces transmitted as logic low In IrDA mode this pin which is a configurable narrow pulse is output for each zero bit that is transmitted CTS1 CTS2 The Clear to Send signal which is multiplexed with PE7 PJ7 in UART 2 is an active low input used for tra...

Page 256: ...ate for synchronous operation The external UCLK pin connects to the UCLK of both UART 1 and UART 2 For UCLK output only one UART at a time is selected to drive this signal Please refer to Section 5 2 2 Peripheral Control Register on page 5 4 for more details 14 3 UART Operation Both UART modules consist of three sub blocks Transmitter Receiver Baud rate generator Section 14 3 1 Transmitter Operati...

Page 257: ...ORCE PERR bit in the corresponding UMISC register The SEND BREAK bit of the corresponding UTX register is used to generate a Break character continuous zeros Use the following procedure to send the minimum number of valid Break characters 1 Make sure the BUSY bit in the UTX register is set 2 Wait until the BUSY bit goes low 3 Clear the TXEN bit in the USTCNT register which flushes the FIFO 4 Wait ...

Page 258: ...t in the URX register can be enabled The FIFO has no remaining space available when this interrupt is generated If the DATA READY bit in the URX register indicates that more data is remaining in the FIFO the FIFO can then be emptied byte by byte If the software has a longer latency time the FIFO HALF interrupt of the URX register can be used This interrupt is generated when no more than 4 empty by...

Page 259: ...of the USTCNT register is high CLK1 is directly sourced by the CLK16 signal 14 3 3 2 Non Integer Prescaler The non integer prescaler is used to generate special nonstandard baud frequencies When IrDA mode is enabled zeros are transmitted as three sixteenth bit time pulses NOTE If the integer prescaler is used in IrDA operation the baud rate will be determined by the integer prescaler The non integ...

Page 260: ... 16 step size Table 14 2 contains the values to program into the non integer prescaler register for IrDA operation Table 14 1 Non Integer Prescaler Values Select Binary Minimum Divisor Maximum Divisor Step Size 000 2 3 127 128 1 128 001 4 7 63 64 1 64 010 8 15 31 32 1 32 011 16 31 15 16 1 16 100 32 63 7 8 1 8 101 64 127 3 4 1 4 110 128 255 1 2 1 2 111 Table 14 2 Non Integer Prescaler Settings Mode...

Page 261: ...system clock frequencies Table 14 3 contains the values that should be used in the UBAUD register for a default 33 16 MHz system clock frequency Table 14 3 Selected Baud Rate Settings Baud Rate Divider Prescaler Hex 230400 0 0x38 115200 1 0x38 57600 2 0x38 28800 3 0x38 14400 4 0x38 38400 1 0x26 19200 2 0x26 9600 3 0x26 4800 4 0x26 2400 5 0x26 1200 6 0x26 600 7 0x26 ...

Page 262: ...the UEN and RXEN bits and perform a word read operation on the URX register to initialize the FIFO and character status bits 0 UART 1 module is disabled 1 UART 1 module is enabled RXEN Bit 14 Receiver Enable This bit enables the receiver block This bit resets to 0 0 Receiver is disabled and the receive FIFO is flushed 1 Receiver is enabled TXEN Bit 13 Transmitter Enable This bit enables the transm...

Page 263: ...o 0 0 RX FULL interrupt is disabled 1 RX FULL interrupt is enabled RXHE Bit 4 Receiver Half Enable When this bit is high it enables an interrupt when the receiver FIFO is more than half full This bit resets to 0 0 RX HALF interrupt is disabled 1 RX HALF interrupt is enabled RXRE Bit 3 Receiver Ready Enable When this bit is high it enables an interrupt when the receiver has at least 1 data byte in ...

Page 264: ...low the sig nal is an input and when it is high it is an output However the SELx bit in the Port E registers must be 0 See Section 10 4 6 Port E Regis ters on page 10 21 for more information 0 UCLK is an input 1 UCLK is an output Reserved Bit 12 Reserved This bit is reserved and should be set to 0 BAUD SRC Bit 11 Baud Source This bit controls the clock source to the baud rate generator 0 Baud rate...

Page 265: ... is full FIFO HALF Bit 14 FIFO Half FIFO Status This read only bit indicates that the receiver FIFO has four or fewer slots remaining in the FIFO This bit generates a maskable interrupt 0 Receiver FIFO has more than four slots remaining 1 Receiver FIFO has four or fewer slots remaining DATA READY Bit 13 Data Ready FIFO Status This read only bit indicates that at least 1 byte is present in the rece...

Page 266: ...racter is not a break character 1 Character is a break character PARITY ERROR Bit 8 Parity Error Character Status This read only bit indicates that the current character was detected with a parity error which indicates that there may be corrupted data This bit is updated and valid with each character read from the FIFO While parity is disabled this bit always reads 0 See description RX DATA Bits 7...

Page 267: ...t the transmitter is busy sending a character This bit is asserted while the transmitter state machine is not idle or the FIFO has data in it 0 Transmitter is not sending a character 1 Transmitter is sending a character CTS1 STAT Bit 9 CTS1 Status CTS1 Bit This bit indicates the current status of the CTS1 signal A snapshot of the pin is taken immedi ately before this bit is presented to the data b...

Page 268: ...for transmission and reception When this bit is high the bit clock is derived directly from the UCLK pin it must be config ured as an input When it is low normal the bit clock is sup plied by the baud rate generator This bit allows high speed synchronous applications in which a clock is provided by the external system 0 Bit clock is generated by the baud rate generator 1 Bit clock is supplied by t...

Page 269: ...eration 1 IrDA operation IRDA LOOP Bit 4 Loop Infrared This bit controls the loopback from the trans mitter to the receiver in the IrDA interface This bit is used for system testing purposes 0 No infrared loop 1 Connect the infrared transmitter to an infrared receiver RXPOL Bit 3 Receive Polarity This bit controls the polarity of the received data 0 Normal polarity 1 idle 1 Inverted polarity 0 idl...

Page 270: ... to the baud rate generator divider Refer to Figure 14 4 on page 14 7 for information about select ing the prescaler 0 Divider source is from the integer prescaler 1 Divider source is from the non integer prescaler Reserved Bits 14 11 Reserved These bits are reserved and should be set to 0 SELECT Bits 10 8 Tap Selection This field selects a tap from the non integer divider 000 Divide range is 2 to...

Page 271: ... 1 on page 14 8 indicates that the SELECT field is 001 The divisor step size for the selected range is one sixty fourth 3 Find the number of steps to program into the STEP VALUE field by subtracting the minimum divisor from the divisor 5 397333 4 1 397333 and dividing this value by the step size which is one sixty fourth or 0 015625 1 397333 0 015625 89 42 The result should be rounded to the neare...

Page 272: ...ables the transmitter block This bit resets to 0 0 Transmitter is disabled and the transmit FIFO is flushed 1 Transmitter is enabled CLKM Bit 12 Clock Mode Selection This bit selects the receiver s operat ing mode When this bit is low the receiver is in 16x mode in which it synchronizes to the incoming datastream and samples at the perceived center of each bit period When this bit is high the rece...

Page 273: ... is enabled RXRE Bit 3 Receiver Ready Enable When this bit is high it enables an interrupt when the receiver has at least 1 data byte in the FIFO When it is low this interrupt is disabled 0 RX interrupt is disabled 1 RX interrupt is enabled TXEE Bit 2 Transmitter Empty Enable When this bit is high it enables an interrupt when the transmitter FIFO is empty and needs data When it is low this interru...

Page 274: ...ow the signal is an input and when it is high it is an output However the SELx bit in the Port E registers must be 0 See Section 10 4 6 Port E Registers on page 10 21 for more information 0 UCLK is an input 1 UCLK is an output Reserved Bit 12 Reserved This bit is reserved and should be set to 0 BAUD SRC Bit 11 Baud Source This bit controls the clock source to the baud rate generator 0 Baud rate ge...

Page 275: ...FIFO is full FIFO HALF Bit 14 FIFO Half FIFO Status This read only bit indicates that the receiver FIFO has four or fewer slots remaining in the FIFO This bit generates a maskable interrupt 0 Receiver FIFO has more than four slots remaining 1 Receiver FIFO has four or fewer slots remaining DATA READY Bit 13 Data Ready FIFO Status This read only bit indicates that at least 1 byte is present in the ...

Page 276: ...acter is not a break character 1 Character is a break character PARITY ERROR Bit 8 Parity Error Character Status This read only bit indicates that the current character was detected with a parity error which indicates that there may be corrupted data This bit is updated and valid with each character read from the FIFO While parity is disabled this bit always reads 0 See description RX DATA Bits 7 ...

Page 277: ... that the transmitter is busy sending a character This bit is asserted while the transmitter state machine is not idle or the FIFO has data in it 0 Transmitter is not sending a character 1 Transmitter is sending a character CTS2 STAT Bit 9 CTS2 Status CTS2 Bit This bit indicates the current status of the CTS2 signal A snapshot of the pin is taken immedi ately before this bit is presented to the da...

Page 278: ...ock for transmission and reception When this bit is high the bit clock is derived directly from the UCLK pin it must be config ured as an input When it is low normal the bit clock is sup plied by the baud rate generator This bit allows high speed synchronous applications in which a clock is provided by the external system 0 Bit clock is generated by the baud rate generator 1 Bit clock is supplied ...

Page 279: ...ration 1 IrDA operation IRDA LOOP Bit 4 Loop Infrared This bit controls the loopback from the trans mitter to the receiver in the IrDA interface This bit is used for system testing purposes 0 No infrared loop 1 Connect the infrared transmitter to an infrared receiver RXPOL Bit 3 Receive Polarity This bit controls the polarity of the received data 0 Normal polarity 1 idle 1 Inverted polarity 0 idle...

Page 280: ...t to the baud rate generator divider Refer to Figure 14 4 on page 14 7 for infor mation about selecting the prescaler 0 Divider source is from the integer prescaler 1 Divider source is from the non integer prescaler Reserved Bits 14 11 Reserved These bits are reserved and should be set to 0 SELECT Bits 10 8 Tap Selection This field selects a tap from the non integer divider 000 Divide range is 2 t...

Page 281: ...el Marker Interrupt Register Description Name Description Setting Reserved Bits 15 12 Reserved These bits are reserved and should be set to 0 TXFIFO LEVEL MARKER Bits 11 8 TxFIFO Level Marker This field defines the level at which the TxFIFO marker is set When the TxFIFO status matches the level marker selected here the TxFIFO half status bit is set and the TXFIFO HALF interrupt is generated if it ...

Page 282: ...Slots Empty Rx FIFO Level Marker Number of Bytes Received 0000 Disable 0000 Disable 0001 4 0001 4 0010 8 0010 8 0011 12 0011 12 0100 16 0100 16 0101 20 0101 20 0110 24 0110 24 0111 28 0111 28 1000 32 1000 32 1001 36 1001 36 1010 40 1010 40 1011 44 1011 44 1100 48 1100 48 1101 52 1101 52 1110 56 1110 56 1111 60 1111 60 ...

Page 283: ...Z328 DragonBall EZ PWM 2 uses 16 bit resolution which is compatible with the MC68328 the original DragonBall The output PWMO1 is generated by logically combining the output of both PWMs The output is available at the PWMO1 external pin The PWMO2 output is generated solely by PWM 2 and is brought to the PWMO2 external pin See Figure 15 1 Figure 15 1 PWM 1 and PWM 2 System Configuration Diagram The ...

Page 284: ...L is equal to 11 divide by 16 In both cases the following assumptions apply SYSCLK 16 58 MHz Prescaler 0 Period default value The 7 bit prescaler may be adjusted to achieve lower sampling rates by programming the prescaler field in the PWM 1 control register with any number between 0 and 127 which scales down the incoming clock source by a factor from 1 to 128 respectively 15 2 PWM 1 PWM 1 is an 8...

Page 285: ...register is at its maximum value for 16 kHz sampling PCLK is 4 096 MHz For human voice quality sound the sampling frequency is either 8 kHz or 16 kHz Figure 15 3 illustrates how variable width pulses affect an audio waveform Figure 15 3 Audio Waveform Generation Digital sample values can be loaded into the pulse width modulator either as packed 2 sample 16 bit words big endian format or as individ...

Page 286: ...stal If a 38 4 kHz crystal is used 38 4 kHz is selected PRESCALER Bits 14 8 Prescaler This field is used to scale down the incoming clock to divide by the prescaler 1 The prescaler is normally used to generate a low single tone PWMO signal For voice modulation these bits are set to 0 divide by 1 The default value is 0 Any value between 0 and 127 IRQ Bit 7 Interrupt Request This bit indicates that ...

Page 287: ...his method shifts the carrier from an audible 8 kHz to a less sensitive 16 kHz fre quency range thus providing better sound quality output 00 No samples are repeated play sample once This is the default 01 Repeat one time play sample twice 10 Repeat three times play sample four times 11 Repeat seven times play sample eight times CLKSEL Bits 1 0 Clock Selection This field selects the output of the ...

Page 288: ... output will never be reset which results in a 100 percent duty cycle The register bit assignments are shown in the following register display The register settings are described in Table 15 2 PWMS1 PWM 1 Sample Register 0x FF FFF502 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 SAMPLE0 SAMPLE1 TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET X X X X X X X X X X X X X X X X 0xXXXX Table ...

Page 289: ...ter This register contains the current count value and can be read at any time without disturbing the counter The register bit assignments are shown in the following register display The register settings are described in Table 15 4 PWMCNT1 PWM 1 Counter Register 0x FF FFF505 BIT 7 6 5 4 3 2 1 BIT 0 PERIOD TYPE rw rw rw rw rw rw rw rw RESET 1 1 1 1 1 1 1 0 0xFE Table 15 3 PWM 1 Period Register Des...

Page 290: ...PWMIRQ IRQEN LOAD PIN POL PWMEN CLKSEL TYPE rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 15 5 PWM 2 Control Register Description Name Description Setting PWMIRQ Bit 15 PWM Interrupt This bit indicates that a period compare posted an interrupt This bit may also be set to immediately post a PWM interrupt for debugging purposes This bit is cleared after it is read whi...

Page 291: ... and should be set to 0 POL Bit 5 Output Polarity This bit controls the PWM output polarity 0 Normal polarity 1 Inverted polarity PWMEN Bit 4 PWM Enable This bit enables PWM 2 0 PWM 2 disabled 1 PWM 2 enabled Reserved Bit 3 Reserved This bit is reserved and should be set to 0 CLKSEL Bits 2 0 Clock Selection These bits select the output of the divider chain 000 Divide by 4 001 Divide by 8 010 Divid...

Page 292: ...hown in the following register display The register settings are described in Table 15 8 PWMCNT2 PWM 2 Counter Register 0x FF FFF516 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 WIDTH TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 15 7 PWM 2 Pulse Width Control Register Description Name Description Setting WIDTH Bits 15 0 Width When the cou...

Page 293: ...ation module are as follows Dedicated chip select for emulator debug monitor using the EMUCS signal Dedicated level 7 interrupt for in circuit emulation One address signal comparator and one control signal comparator with masking to support single or multiple hardware execution and bus breakpoints One breakpoint instruction insertion unit Figure 16 1 illustrates the block diagram of the in circuit...

Page 294: ...which EMUBRK is an output the generation of the EMUBRK signal is internally qualified by the AS signal The active time for this signal will vary depending on the setting and width wait state of the bus cycle The EMUBRK signal is asserted throughout the address matched cycle When the in circuit emulation module is in multiple breakpoint mode EMUBRK is an input that is asserted by the external addre...

Page 295: ...cs of the current cycle A 0 indicates a data access cycle FC 2 0 x01 and a 1 indicates a program access FC 2 0 x10 The emulator uses this signal to disassemble assembly code during trace 16 1 4 Using the Interrupt Gate Module There are three level 7 interrupt sources two are internal and one is external An internal level 7 interrupt is generated if it is enabled when a program or bus breakpoint is...

Page 296: ... address mask register ICEMAMR is used to mask the corresponding address bit in the ICEMACR The in circuit emulation module s address comparator will compare the address bus value together with the control bus value to generate the EMUBRK signal A range can be set by using the address mask bits to break in a range of memory so that the external address comparator can take action if extra hardware ...

Page 297: ...2 0 A M1 9 A M1 8 A M1 7 AM1 6 TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 AM1 5 AM 14 AM1 3 AM1 2 AM1 1 AM1 0 A M9 A M8 A M7 A M6 A M5 A M4 A M3 A M2 A M1 AM0 TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 16 1 ICE Module Address Compare and ...

Page 298: ... The settings for the bits are described in Table 16 2 and Table 16 3 ICEMCCR ICE Module Control Compare Register 0x FF FFFFFD08 ICEMCMR ICE Control Mask Register 0x FF FFFFFD0A BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 RW PD TYPE rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 16 2 ICE Module Control Compare Register Description Name Description Setting Reserved Bits 15 2 Reserved Th...

Page 299: ...gainst the RW bit 1 Force a true comparison don t care on the corresponding bit PDM Bit 0 Program or Data Cycle Mask This bit masks the PD bit of the ICEMCCR 0 Enable the comparator to compare itself against the PD bit 1 Force a true comparison don t care on the corresponding bit Table 16 3 ICE Control Mask Register Description Continued Name Description Setting ...

Page 300: ...7 interrupt generation on a bus breakpoint 1 Enable level 7 interrupt generation on a bus breakpoint HMDIS Bit 3 Hard Map Disable In emulation mode this bit activates the internal hard map operation When this bit is clear some memory locations are hard coded to the specific values shown in Table 16 5 on page 16 9 If this bit is set or in nor mal mode memory reads to these locations refer to the ex...

Page 301: ...fore setting this bit to valid 0 Disable the breakpoint comparison logic 1 Enable the breakpoint comparison logic Table 16 5 Emulation Mode Hard Coded Memory Locations Address Hard Code 0x0 0xFFFC 0x2 0xFFFC 0x4 0xFFFC 0x6 0x0020 0x28 0xFFFC 0x2A 0x0010 IRQ7 vector upper word 0xFFFC IRQ7 vector lower word 0x0010 Table 16 4 ICE Module Control Register Description Continued Name Description Setting ...

Page 302: ...C68VZ328 pin out extension to connect to the solder on emulator pod The entire MC68VZ328 bus should be buffered using level shifting buffers when the emulator is designed in 5 V and the processor is running at 3 3 V BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 EMUEN BBIRQ BRKIRQ EMIRQ TYPE rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Table 16 6 ICE Module Status Register Description N...

Page 303: ...eakpoint is matched the CPU must report its status and grab the necessary contents such as internal registers in the system This information is then transmitted to the host control processor to be translated before it is passed to the interface on the PC The monitor program is located in ROM at 0xFFFC0000 0xFFFCFFFF and is enabled or disabled by the EMUCS signal Host Control PC Address Comparator ...

Page 304: ... Detecting Breakpoints in multiple breakpoint mode the external FPGA address comparator compares the lower address the internal comparator compares the upper hidden address line and then a EMUIRQ signal is generated to tell the in circuit emulation module to generate a breakpoint 16 3 5 Optional Trace Module A trace module may also be added to enhance the function of the emulator Trace captures th...

Page 305: ...module is buffered with 3 3 V to 5 0 V buffers so that it can communicate with the PC without causing any problems The entire emulation module only uses 29 pins including a ground signal A very low cost cable can be built to ship with the software debugger package These pins can remain on the production version of the system board for production testing as well as diagnostic and failure analysis H...

Page 306: ...set switch and one abort switch The abort switch is debounced and connected to the EMUIRQ signal The RESET signal is generated by the MC1455 monostable timer The host interface port is selected by the PAL decoding the EMUCS A13 and A14 signals The board also provides optional SRAM and ROM plug in sockets for expansion Host Interface RS 232 On Board Memory Debug EMUCS D 15 0 MC68VZ328 CPU CSxx ROM ...

Page 307: ...ownload The first character received is used to instruct the MC68VZ328 whether the PLL input clock is 32 768 kHz or 38 4 kHz crystal as well as to determine which UART port is being used for bootstrapping The first character can be any value and is not part of the program or data being downloaded Downloading the data or program requires the user convert the code to a bootstrap format file which is...

Page 308: ...e transferred The 4 byte address field indicates where the data will be stored and this address could be any MC68VZ328 internal register location The count field of the record contains the number of data bytes to be transferred The data field contains the data to be transferred 17 1 2 2 Execution B Record Format The execution b record tells the bootloader to run a program starting at the location ...

Page 309: ...e may be changed after 19 200 bps is initially used to set up the RS 232 terminal Simply issue a b record to reinitialize the baud control register of the UART controller which is described in Section 14 4 2 UART 1 Baud Control Register on page 14 12 For example if the system uses a 32 768 kHz external crystal the baud control register is initialized to 0x0126 after 19 200 bps is set up assuming t...

Page 310: ...80130 emucs init FFFFF000011C SCR init FFFFFB0A0100 Disable WD FFFFF42B0183 enable clko FFFFF40B0100 enable chip select FFFFFD0D0108 disable hardmap FFFFFD0E0107 clear level 7 interrupt FFFFF100020100 CSA 2M 4M FFFFF1100201A7 FFFFF102020000 CSB 0 256K FFFFF112020091 FFFFFC00028F00 DRAM Config FFFFFC02029667 DRAM Control FFFFF106020200 CSD init RAS0 4M 6M RAS1 6M 8M FFFFF11602029D enable DRAM cs FF...

Page 311: ...un the DOS program STOB EXE to convert the preceding s records to bootstrap format 0000400010428142423C30200032C6548154420C42 000040101000106DF04242B2806DEA4280D098B3C8 00004020066AFA4E714E75 Download the preceding b record file to the target system using the UART port in bootstrap mode Since this b record file will be loaded into system RAM initialize the system by downloading an init b record fi...

Page 312: ...in the following lines where FFFFFFC0 is the IBUFF address location FFFFFFC00C303C00554E714E714E714E71 FFFFFFC000 The first b record loads the instruction buffer The second b record tells the bootloader to run the instruction in the instruction buffer When the execution is complete it accepts new b record transfers The CPU registers D0 D6 and A0 are used by the bootloader program Writing to these ...

Page 313: ...de 17 7 Figure 17 2 Bootloader Program Operation Start Test receive FIFO Initialize appropriate UART Receive a bootstrap CNT 0 ADDR IBUFF Run program starting at ADDR Store DATA to ADDR Execute instruction in IBUFF NO YES NO YES record ...

Page 314: ...e exclamation point quotation mark number sign dollar sign percentage symbol ampersand opening parenthesis closing parenthesis asterisk plus sign minus sign period forward slash The bootloader program echoes all characters being received but only those having an ASCII code value greater than or equal to 0x30 are kept for b record assembling Sending a character that is not a b record ASCII code val...

Page 315: ...ble contact the local Motorola sales office 18 1 2 8 Bit Bus Width Issues To ensure maximum flexibility the MC68VZ328 supports both 8 and 16 bit data bus modes Except the chip select group A which carries the boot chip select signal CSA0 and is normally connected to boot ROM all the chip select signals are programmable to 8 bit or 16 bit mode after reset The data bus width for the CSA0 and CSA1 si...

Page 316: ...ons can lead to problems Do not leave unused input pins floating Unused inputs should be tied high or low but not left floating Unused inputs can be tied directly to VSS or VDD or through pull ups or pull downs to VSS or VDD Use the port pins efficiently When port pins are not used they should be configured as inputs with pull up enabled or as an output with pull up disabled to reduce power consum...

Page 317: ...istics of the MC68VZ328 Section 19 3 AC Electrical Characteristics consists of output delays input setup and hold times and signal skew times It also contains timing information for working with RAM DRAM and other memory related modules and peripherals 19 1 Maximum Ratings Table 19 1 provides information on maximum ratings Table 19 1 Maximum Ratings Rating Symbol Value Unit Supply voltage VDD 0 3 ...

Page 318: ...at WS is the number of wait states in the current memory access cycle The signal values and units of measure for this figure are found in Table 19 3 on page 19 3 For detailed information about the individual signals see Chapter 6 Chip Select Logic Table 19 2 Maximum and Minimum DC Characteristics Number or Symbol Characteristic 3 0 0 3 V Unit Minimum Typical Maximum 1 Full running operating curren...

Page 319: ...re found in Table 19 4 on page 19 4 For detailed information about the individual signals see Chapter 6 Chip Select Logic Table 19 3 CLKO Reference to Chip Select Signals Timing Parameters Number Characteristic 3 0 0 3 V Unit Minimum Maximum 1 CLKO high to CSx asserted 10 ns 2 CLKO low to CSx negated 12 ns 3 CLKO high to RASx asserted 10 ns 4 CLKO high to RASx negated 12 ns 5 CLKO high to CASx ass...

Page 320: ...negated before row address valid 0 ns 3 CSx asserted to OE asserted 0 ns 4 Data in valid from CSx asserted 35 nT ns 5 External DTACK input setup from CSx asserted 20 nT ns 6 CSx pulse width bit ECDS 0 bit ECDS 1 60 nT 60 T 2 nT ns 7 External DTACK input hold after CSx is negated 0 ns 8 Data in hold after CSx is negated 0 ns 9 OE negated after CSx is negated 0 10 ns 10 UB LB asserted to CSx asserte...

Page 321: ...ming Diagram 11 CSx negated to UB LB negated 16 bit SRAM 10 ns Note n is the number of wait states in the current memory access cycle T is the system clock period The external DTACK input requirement is eliminated when CSx is programmed to use internal DTACK CSx stands for CSA0 CSA1 CSB0 CSB1 CSC0 CSC1 CSD0 or CSD1 A value in parentheses is used when early cycle detection is turned on Table 19 4 C...

Page 322: ...4 ns 3 CSx asserted to data out valid 30 ns 4 External DTACK input setup from CSx asserted 20 nT ns 5 CSx pulse width bit ECDS 0 bit ECDS 1 60 nT 60 T 2 nT ns 6 UWE LWE negated before CSx is negated 10 20 ns 7 External DTACK input hold after CSx is negated 0 ns 8 Data out hold after CSx is negated 8 ns 9 CSx negated to data out in Hi Z 18 ns 10 CSx asserted to WE asserted 16 bit SRAM 0 4 ns 11 WE ...

Page 323: ... 20 nT ns 5 CSx pulse width bit ECDS 0 bit ECDS 1 60 nT 60 T 2 nT ns 6 UWE LWE negated before CSx is negated 10 20 ns 7 External DTACK input hold after CSx is negated 0 ns 8 Data out hold after CSx is negated 8 ns 9 CSx negated to data out in Hi Z 18 ns Note n is the number of wait states in the current memory access cycle T is the system clock period The external DTACK input requirement is elimin...

Page 324: ...DRAM read cycle timing diagram for 16 bit access CPU bus master The signal values and units of measure for this figure are found in Table 19 8 on page 19 9 Detailed information about the operation of individual signals can be found in Chapter 7 DRAM Controller and Chapter 6 Chip Select Logic Table 19 7 Chip Select Timing Trim Timing Parameters Number Characteristic 3 0 0 3 V Unit Minimum Maximum 1...

Page 325: ...efore RASx is asserted 0 ns 4 RASx asserted before row address invalid MSW 0 1 12 27 ns 5 Column address valid to CASx asserted MSW 0 1 10 25 ns 6 RASx asserted to CASx asserted MSW 0 1 28 58 32 ns 7 RASx pulse width SLW 0 1 90 120 ns 8 CASx pulse width BC 1 0 00 01 10 11 28 58 88 118 ns 9 CASx asserted to data in valid BC 1 0 00 01 10 11 for FPM 15 45 75 105 FPM 20 EDO ns 10 Data in hold after CA...

Page 326: ... Access CPU Bus Master Timing Diagram 12 CASx asserted before column address invalid 50 ns 13 RASx negated after CASx is negated 28 ns 14 RASx precharge time SLW 0 1 58 118 ns Note RASx stands for RAS0 and RAS1 CASx stands for CAS0 and CAS1 Note MSW is bit 5 SLW is bit 3 and BC 1 0 comprises bits 13 12 in the DRAMC register When the table identifies these bits the sequence of their listed values c...

Page 327: ...ated before RASx asserted 0 ns 4 RASx asserted before row address invalid MSW 0 1 12 27 ns 5 Column address valid to CASx asserted MSW 0 1 10 25 ns 6 RASx asserted to CASx asserted MSW 0 1 28 58 ns 7 RASx pulse width SLW 0 1 90 120 ns 8 CASx pulse width BC 1 0 00 01 10 11 28 58 88 118 ns 9 Data out valid before CASx asserted 25 ns 10 Data out hold after CASx negated 25 ns 11 DWE negated after CASx...

Page 328: ...tion of individual signals can be found in Chapter 7 DRAM Controller Figure 19 9 DRAM Hidden Refresh Cycle Low Power Mode Timing Diagram Table 19 10 DRAM Hidden Refresh Cycle Normal Mode Timing Parameters Number Characteristic 3 0 0 3 V Unit Minimum Maximum 1 CASx pulse width 88 ns 2 RASx pulse width 88 ns 3 CASx asserted to RASx asserted 28 32 ns 4 RASx negated to CASx negated 28 ns 5 CASx negate...

Page 329: ...in Chapter 7 DRAM Controller and Chapter 8 LCD Controller Figure 19 10 LCD SRAM ROM DMA Cycle 16 Bit Mode Access Timing Diagram Table 19 11 DRAM Hidden Refresh Cycle Low Power Mode Timing Parameters Number Characteristic 3 0 0 3 V Unit Minimum Maximum 1 CASx pulse width 120 ns 2 RASx pulse width 120 ns 3 CASx asserted to RASx asserted 30 ns 4 CASx negated to RASx negated 30 ns 5 Refresh cycle usin...

Page 330: ...t the operation of individual signals can be found in Chapter 7 DRAM Controller and Chapter 8 LCD Controller Figure 19 11 LCD DRAM DMA Cycle 16 Bit EDO RAM Mode Access LCD Bus Master Timing Diagram Table 19 12 LCD SRAM ROM DMA Cycle 16 Bit Mode Access Timing Parameters Number Characteristic 3 0 0 3 V Unit Minimum Maximum 1 Address valid to CSx asserted 20 ns 2 UWE LWE to CSx asserted 28 ns 3 Data ...

Page 331: ...1 10 25 ns 6 RASx asserted to CASx asserted MSW 0 1 28 58 ns 7 CASx asserted to data in valid 20 ns 8 CASx asserted before column address invalid 20 ns 9 RASX pulse width 2N 1 T ns 10 CASx pulse width 28 ns 11 CASx precharge time 26 ns 12 RASx negated to CASx negated 28 ns 13 Data in hold after CASx negated 30 ns 14 OE negated after CASx negated 28 32 ns Note N is the number of words in one DMA tr...

Page 332: ... DMA Cycle 16 Bit Fast Page Mode Access LCD Bus Master Timing Diagram Table 19 14 LCD DRAM DMA Cycle 16 Bit Fast Page Mode Access LCD Bus Master Timing Parameters Number Characteristic 3 0 0 3 V Unit Minimum Maximum 1 Row address valid to RASx asserted 45 ns 2 DWE negated before row address valid 0 ns 3 OE asserted before RASx asserted 0 ns 4 RASx asserted before row address invalid MSW 0 1 12 27 ...

Page 333: ... width 2N 1 T ns 10 CASx pulse width BC 1 0 00 01 10 11 in FPM 28 58 88 118 ns 11 CASx precharge time 26 ns 12 RASx negated to CASx negated 28 ns 13 Data in hold after CASx negated 0 ns 14 OE negated after CASx negated 0 2 ns Note N is the number of words in one DMA transfer T is the system clock period RASx stands for RAS0 and RAS1 CASx stands for CAS0 and CAS1 MSW is bit 5 and BC 1 0 comprises b...

Page 334: ...ft clock to line pulse 2 pixclk 2 2 pixclk 2 ns Note The preceding data is measured by summing the polarity bits LFLM LLP and LCLK in the POLCF register The variable pixclk LCD_CLK pcd 1 The self refresh mode timing between LFRM LSCLK LD and LLP are the same as in normal mode The self refresh mode is entered and exited on the positive edge of LFRM In self refresh mode the LFRM and LLP waveforms ar...

Page 335: ...gure are found in Table 19 16 on page 19 31 Detailed information about the operation of individual signals can be found in both Chapter 8 LCD Controller and Chapter 7 DRAM Controller Figure 19 15 Page Miss SDRAM CPU Read Cycle Timing Diagram 1 S0 5 16 2 S2 S4 S4 S4 S4 S0 S6 S4 S2 S3 S1 S7 S5 S4 S4 S4 S3 S1 SDCLK RAS SCKEN D 15 0 CAS A 16 1 MD 15 0 SDA10 CS WE DQM DTACK 3 Active Command Precharge C...

Page 336: ...nal values and units of measure for this figure are found in Table 19 16 on page 19 31 Detailed information about the operation of individual signals can be found in both Chapter 8 LCD Controller and Chapter 7 DRAM Controller Figure 19 16 Page Hit SDRAM CPU Read Cycle Timing Diagram S0 S2 S4 S4 S6 S7 S5 S4 S3 S1 SDCLK RAS SCKEN D 15 0 CAS A 16 1 MD 15 0 SDA10 CS WE DQM DTACK Read Command Col 6 ...

Page 337: ...lues and units of measure for this figure are found in Table 19 16 on page 19 31 Detailed information about the operation of individual signals can be found in both Chapter 8 LCD Controller and Chapter 7 DRAM Controller Figure 19 17 Page Hit CPU Read Cycle for 8 Bit SDRAM Timing Diagram S0 S2 S4 S4 S4 S5 S4 S4 S3 S1 SDCLK RAS SCKEN D 15 0 CAS A 16 1 MD 15 0 SDA10 CS WE DQM DTACK Read Command Col U...

Page 338: ...f measure for this figure are found in Table 19 16 on page 19 31 Detailed information about the operation of individual signals can be found in both Chapter 8 LCD Controller and Chapter 7 DRAM Controller Figure 19 18 Page Miss SDRAM CPU Write Cycle Timing Diagram S0 17 S2 S4 S4 S6 S7 S5 S4 S3 S1 SDCLK RAS SCKEN D 15 0 CAS A 16 1 MD 15 0 SDA10 CS WE DQM DTACK Active Command Precharge Command Write ...

Page 339: ...RAM The signal values and units of measure for this figure are found in Table 19 16 on page 19 31 Detailed information about the operation of individual signals can be found in both Chapter 8 LCD Controller and Chapter 7 DRAM Controller Figure 19 19 Page Hit SDRAM CPU Write Cycle Timing Diagram S0 S2 S4 S6 S7 S5 S3 S1 SDCLK RAS SCKEN D 15 0 CAS A 16 1 MD 15 0 SDA10 CS WE DQM DTACK Write Command Co...

Page 340: ...gnal values and units of measure for this figure are found in Table 19 16 on page 19 31 Detailed information about the operation of individual signals can be found in both Chapter 8 LCD Controller and Chapter 7 DRAM Controller Figure 19 20 Page Hit CPU Byte Write Cycle for 8 Bit SDRAM Timing Diagram S0 S2 S4 S6 S7 S5 S3 S1 SDCLK RAS SCKEN D 15 0 CAS A 16 1 MD 15 0 SDA10 CS WE DQM DTACK Write Comma...

Page 341: ...ower down mode The signal values and units of measure for this figure are found in Table 19 16 on page 19 31 Detailed information about the operation of individual signals can be found in both Chapter 8 LCD Controller and Chapter 7 DRAM Controller Figure 19 21 Page Hit CPU Read Cycle in Power down Mode Timing Diagram S0 S2 S4 S4 S4 S4 S4 S4 S3 S1 SDCLK RAS SCKEN D 15 0 CAS A 16 1 MD 15 0 SDA10 CS ...

Page 342: ...nal values and units of measure for this figure are found in Table 19 16 on page 19 31 Detailed information about the operation of individual signals can be found in both Chapter 8 LCD Controller and Chapter 7 DRAM Controller Figure 19 22 Exit Self Refresh Due to CPU Read Cycle Timing Diagram S2 S4 S4 S4 S4 S4 S4 S4 S4 S3 SDCLK RAS SCKEN D 15 0 CAS A 16 1 MD 15 0 SDA10 CS WE DQM DTACK S4 S4 S4 S4 ...

Page 343: ...esh due to no activity The signal values and units of measure for this figure are found in Table 19 16 on page 19 31 Detailed information about the operation of individual signals can be found in both Chapter 8 LCD Controller and Chapter 7 DRAM Controller Figure 19 23 Enter Self Refresh Due to No Activity Timing Diagram SDCLK RAS SCKEN CAS A 16 1 MD 15 0 SDA10 CS WE Precharge Command Auto Refresh ...

Page 344: ... found in Table 19 16 on page 19 31 Detailed information about the operation of individual signals can be found in both Chapter 8 LCD Controller and Chapter 7 DRAM Controller Figure 19 24 Page Miss at Starting of LCD DMA for SDRAM Timing Diagram SDCLK RAS SCKEN D 15 0 CAS A 16 1 MD 15 0 SDA10 CS WE DQM DTACK Active Command Precharge Command Read Command Read Command Read Command Read Command Bank ...

Page 345: ...19 16 on page 19 31 Detailed information about the operation of individual signals can be found in both Chapter 8 LCD Controller and Chapter 7 DRAM Controller Figure 19 25 Page Miss at Start and in Middle of LCD DMA Timing Diagram SDCLK RAS SCKEN D 15 0 CAS A 16 1 MD 15 0 SDA10 CS WE DQM DTACK Active Command Precharge Command Read Command Precharge Command Active Command Read Command Read Command ...

Page 346: ...for this figure are found in Table 19 16 on page 19 31 Detailed information about the operation of individual signals can be found in both Chapter 8 LCD Controller and Chapter 7 DRAM Controller Figure 19 26 Page Hit LCD DMA Cycle for SDRAM Timing Diagram SDCLK RAS SCKEN D 15 0 CAS A 16 1 MD 15 0 SDA10 CS WE DQM DTACK Read Command Read Command Read Command Read Command Col n Col n 1 Col n 2 Col n 3...

Page 347: ...CKEN asserted 8 12 ns 8 Clock high to RAS asserted 3 12 ns 9 Self refresh exit to active command asserted 4 7 CLK 10 Clock high to WE asserted 3 12 ns 11 Precharge command to active command 1 2 CLK 12 Clock high to DQM asserted 3 12 ns 13 DQM width asserted 28 ns 14 Clock high to DTACK asserted 10 ns 15 Active command to read write command 1 2 CLK 16 Data setup time 13 ns 17 Data valid to clock hi...

Page 348: ... 3 27 SPI 1 Master Using DATA_READY Edge Trigger Figure 19 28 shows the timing diagram for the SPI 1 master using the DATA_READY edge trigger The signal values and units of measure for Figure 19 27 through Figure 19 32 are found in Table 19 17 on page 19 34 Detailed information about the operation of individual signals can be found in Chapter 13 Serial Peripheral Interface 1 and 2 Figure 19 28 SPI...

Page 349: ...n t care The signal values and units of measure for Figure 19 27 through Figure 19 32 are found in Table 19 17 on page 19 34 Detailed information about the operation of individual signals can be found in Chapter 13 Serial Peripheral Interface 1 and 2 Figure 19 30 SPI 1 Master Don t Care DATA_READY Timing Diagram 19 3 30 SPI 1 Slave FIFO Advanced by Bit Count Figure 19 31 shows the timing diagram f...

Page 350: ...e Timing Diagram Table 19 17 Timing Parameters for Figure 19 27 Through Figure 19 32 Number Characteristic 3 0 0 3 V Unit Minimum Maximum 1 Clock edge to TxD data ready 0 25T ns 2 RxD data ready to clock edge 0 25T ns 3 Clock edge to RxD data hold time 0 25T ns 4 DATA_READY to SS output low 2T ns 5 SS output low to first SCLK edge 2T ns 6 Last SCLK edge to SS output high T ns 7 SS output high to D...

Page 351: ...through Figure 19 35 are found in Table 19 18 on page 19 36 Figure 19 33 Normal Mode Timing Diagram 19 3 33 Emulation Mode Timing Figure 19 34 shows the timing diagram for emulation mode timing of the MC68VZ328 The signal values and units of measure for Figure 19 33 through Figure 19 35 are found in Table 19 18 on page 19 36 Figure 19 34 Emulation Mode Timing Diagram RESET EMUIRQ EMUBRK HIZ 2 1 RE...

Page 352: ...he signal values and units of measure for Figure 19 33 through Figure 19 35 are found in Table 19 18 Figure 19 35 Bootstrap Mode Timing Diagram Table 19 18 Timing Parameters for Figure 19 33 Through Figure 19 35 Number Characteristic 3 0 0 3 V Unit Minimum Maximum 1 EMUIRQ EMUBRK and HIZ setup time 10 ns 2 EMUIRQ EMUBRK and HIZ hold time 20 ns RESET EMUIRQ EMUBRK HIZ 2 1 ...

Page 353: ...nformation for the two package types the 144 lead plastic thin quad flat package TQFP and the 144 lead mold array process ball grid array MAPBGA package Table 20 1 MC68VZ328 Ordering Information Package Type Frequency MHz Temperature Order Number 144 lead TQFP 33 0 O C to 70 O C MC68VZ328PV33V 144 lead MAPBGA 33 0 O C to 70 O C MC68VZ328VF33V 144 lead TQFP 33 40 O C to 85 O C MC68VZ328CPV33V 144 l...

Page 354: ...LD0 PC1 LD1 PC2 LD2 PC3 LD3 PC4 LFRM PC5 LLP V DD LV DD PC6 LCLK PC7 LACD PF0 CONTRAST PD0 INT0 PD1 INT1 PD2 INT2 PD3 INT3 PD4 IRQ1 V SS V SS PD5 IRQ2 PD6 IRQ3 PD7 IRQ6 PF1 IRQ5 PF2 CLKO PJ0 MOSI PJ1 MISO PJ2 SPICLK1 PJ3 SS NC V DD V DD 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 35 107 108 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 9...

Page 355: ...00B SC B 20 00B SC B1 10 00B SC C 1 40 1 60 C1 0 05 0 15 C2 1 35 1 45 D 0 17 0 27 E 0 45 0 75 F 0 17 0 23 G 0 50BSC J 0 09 0 20 K 0 50R EF P 0 25B SC R1 0 13 0 20 R2 0 13 0 20 S 22 00B SC S1 11 00B SC V 22 00B SC V1 11 00B SC Y 0 25R EF Z 1 00R EF AA 0 09 0 16 θ 0 θ 0 7 θ 11 13 1 2 NOTES 1 DIMENSIONS AND TOLERANCING PER ASME Y14 5M 1994 2 DIMENSIONS IN MILLIMETERS 3 DATUMSL M NTOBEDETERMINEDATTHE ...

Page 356: ...2 PE5 TXD1 PJ2 SPICLK1 PJ3 SS PE4 RXD1 PK3 UDS PJ1 MISO PE6 RTS1 PE7 CTS1 PG2 EMUIRQ PF7 CSA1 PC0 LD0 PK2 LDS PK0 DATA_READY PB0 CSB0 PK1 RW PC3 LD3 PC5 LLP PB7 PWMO PC2 LD2 PC4 LFRM PC7 LACD PD3 INT3 PC1 LD1 PC6 LCLK PF0 CONTRAST PD1 INT1 PD4 IRQ1 PF1 IRQ5 1 A 2 3 4 5 6 7 8 9 10 11 12 B C D E F G H J K L M VSS OE PD0 INT0 PG0 BUSW DTACK PA1 D1 PA0 D0 MD9 A10 PM0 SDCLK PA5 D5 Top View VSS VSS VSS ...

Page 357: ...IM MIN MAX MILLIMETERS A 1 60 A1 0 27 0 47 A2 1 16 REF b 0 40 0 60 D 13 00 BSC E 13 00 BSC e 1 00 BSC NOTES 1 DIMENSIONS ARE IN MILLIMETERS 2 INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M 1994 3 DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO DATUM PLANE Z 4 DATUM Z SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS 5 PARALLELISM MEASUREMENT SHALL EX...

Page 358: ...t 20 6 PCB Finish Requirement For a more reliable BGA assembly process use HASL finish on PCB EMNI AU finish is not recommended When EMNI AU finish is used on PCB brittle intermetallic fractures occasionally occur at the BGA pad to PCB pad solder joint ...

Page 359: ...e enable bit see AST bit AST bit 6 20 Autovector interrupts 9 4 AWS0 bit 6 17 B Baud rate generator baud rates affected by PLL frequencies 14 9 block diagram 14 7 divider binary 14 7 divisor calculation 14 8 non integer prescaler 14 7 operation 14 6 reset bit see BAUD RESET bit testing bit see BAUD TEST bit BAUD RESET bit UMISC1 register 14 16 UMISC2 register 14 26 Baud source bit see BAUDSRC bit ...

Page 360: ...0 Capture value field see CAPTURE field CAS0 CAS1 signal 6 1 Cascaded timers available configurations 12 4 description of 12 4 methods to compare and capture 12 4 CCPEN bit 8 21 CCx field 8 12 CGBA field 6 7 CGM see clock generation module Chip ID and version determining 18 1 Chip select and EDO RAM interface signals 2 10 logic address select signal see AS signal configuring memory 6 2 data bus si...

Page 361: ...ield TCMP1 register 12 9 TCMP2 register 12 9 Compare value field see COMPARE field Contrast control enable bit see CCPEN bit Controlling Frame Rate Modulation function absence of 8 7 Conventions of formatting used in this manual xxix COUNT field PWMCNT1 register 15 7 PWMCNT2 register 15 10 TCN1 register 12 11 TCN2 register 12 11 Count field see COUNT field Counter clock source bit see CSRC bit CPU...

Page 362: ...al characteristics Definitions general xxx DGBA field 6 7 Direction field see DIRx field DIRx field PADIR register 10 7 PBDIR register 10 9 PCDIR register 10 12 PDDIR register 10 16 PEDIR register 10 21 PFDIR register 10 24 PGDIR register 10 28 PJDIR register 10 31 PKDIR register 10 34 PMDIR register 10 37 Disable PLL bit see DISPLL bit DISPLL bit 4 9 DIVIDE field UBAUD1 register 14 12 UBAUD2 regi...

Page 363: ...it 9 8 ET2 bit 9 9 ET3 bit 9 9 ET6 bit 9 9 EUPEN bit 6 17 EWE bit 6 20 EWSO bit 6 17 Exception vector assignments 9 3 to 9 4 definition 9 3 Exchange bit see XCH bit Execution b record format see bootstrap mode EXTAL pin description 2 4 Extended data out see EDO bit External clock crystal see EXTAL pin External INT0 interrupt bit see INT0 bit External INT1 interrupt bit see INT1 bit External INT2 i...

Page 364: ... GBDx field GSx field 8 15 H Hardware flow control UART see CTS signal HASL finish see PCB finish requirements HMARK register 14 29 I I O ports configuration 10 1 data flow from I O module 10 4 data flow to I O module 10 5 data loss when changing modes preventing 10 5 dedicated functions 10 2 drive current levels setting 10 1 introduction 10 1 operating port as GPIO 10 5 operation 10 4 to 10 6 pin...

Page 365: ...riority mask 9 4 Interrupt request bit see IRQ bit Interrupt request enable bit see IRQEN bit Interrupt request level 1 bit see IRQ1 bit Interrupt request level 2 bit see IRQ2 bit Interrupt request level 3 bit see IRQ3 bit Interrupt request level 5 bit see IRQ5 bit Interrupt request level 6 bit see IRQ6 bit Interrupt service routine programming considerations 9 5 Interrupt sources control bits 9 1...

Page 366: ...LCD cursor vertical Y pixel 8 0 field see CYPx field LCD cursor width 4 0 field see CWx field LCD cursor width and height register see LCWCH register LCD cursor X position 9 0 field see CXPx field LCD cursor X position register see LCXP register LCD cursor Y position register see LCYP register LCD data bus bits 7 0 see LD 3 0 PC 3 0 LD 7 4 PK 7 4 pins LCD frame marker polarity bit see FLMPOL bit L...

Page 367: ...1 interrupt bit see MINT1 bit Mask external INT2 interrupt bit see MINT2 bit Mask external INT3 interrupt bit see MINT3 bit Mask IRQ1 interrupt bit see MIRQ1 bit Mask IRQ2 interrupt bit see MIRQ2 bit Mask IRQ3 interrupt bit see MIRQ3 bit Mask IRQ5 interrupt bit see MIRQ5 bit Mask IRQ6 interrupt bit see MIRQ6 bit Mask keyboard interrupt bit see MKB bit Mask PWM 1 interrupt bit see MPWM1 bit Mask PW...

Page 368: ... 1 PADATA register 10 7 PADIR register 10 7 Page access clock cycle fast page mode field see BC1 0 field Page size field see PGSZ field Panel bus width 1 0 field see PBSIZ1 0 field PAPUEN register 10 8 Parity enable bit see PEN bit Parity error character status bit see PARITY ERROR bit PARITY ERROR bit URX1 register 14 14 URX2 register 14 24 PBDATA register 10 9 PBDIR register 10 9 PBPUEN register...

Page 369: ...sters data register see PADATA register direction register see PADIR register pull up enable register see PAPUEN register register summary 10 6 Port B bit 6 see TOUT TIN PB6 pin bit 7 see PWMO1 PB7 pin dedicated I O functions 10 9 to 10 10 registers data register see PBDATA register direction register see PBDIR register pull up enable register see PBPUEN register register summary 10 8 select regis...

Page 370: ...2 DATA_READY PK0 pin bits 7 4 see LD 3 0 PC 3 0 LD 7 4 PK 7 4 pins dedicated I O functions 10 35 registers data register see PKDATA register direction register see PKDIR register pull up pull down enable register see PKPUEN register register summary 10 34 select register see PKSEL register Port M dedicated I O functions 10 39 registers data register see PMDATA register direction register see PMDIR...

Page 371: ...M 1 control register see PWMC1 register PWM 1 counter register see PWMCNT1 register PWM 1 interrupt bit see PWM1 bit PWM 1 period register see PWMP1 register PWM 1 sample register see PWMS1 register PWM 2 compared to PWM 1 15 8 period register setting to 00 15 9 width and period settings 15 10 PWM 2 counter register see PWMC2 register PWM 2 period register see PWMP2 register PWM 2 pulse width cont...

Page 372: ...N bit 13 8 RTC bit 9 18 IPR register 9 18 ISR register 9 14 RTI bit IPR register 9 16 ISR register 9 13 RTS1 bit 14 17 RTS1 control bit see RTS1CONT bit RTS1 PE6 pin 2 8 RTS1 RTS2 pin 14 4 RTS1CONT bit 14 17 RTS2 bit 14 27 RTS2 control bit see RTS2CONT bit RTS2 PJ6 pin 2 8 RTS2CONT bit 14 27 RW PK1 pin 2 6 Rx data character data field see RXDATA field RX DATA field URX1 register 14 14 URX2 registe...

Page 373: ...de 4 12 operation 4 12 Slow multiplexing bit see MSW bit Slow RAM bit see SLW bit SLW bit 7 15 SOP bit CSB register 6 10 CSC register 6 12 CSD register 6 14 Source field see SRC1 0 field SPI 1 block diagram 13 1 data bad data word indication 13 9 ensuring none is lost 13 9 transferring between devices 13 2 overview 13 1 phase and polarity 13 3 programming model 13 4 to 13 11 registers control and ...

Page 374: ...4 11 USTCNT2 register 14 20 Stop bit transmission bit see STOP bit Suggested reading xxix Supervisor use only protected memory block bit see SOP bit SYSCLK SEL field 4 8 System clock select field see SYSCLK SEL field System control register see SCR register System integration module 5 1 T Tap selection field see SELECT field TCMP1 register 12 9 TCMP2 register 12 9 TCN1 register 12 11 TCN2 register...

Page 375: ...RT 2 14 5 data for see DATA field TxFIFO counter field see TXCNT field TxFIFO empty interrupt enable bit see TEEN bit TxFIFO empty status bit see TE bit TxFIFO full interrupt enable bit see TFEN bit TxFIFO full status bit see TF bit TxFIFO half interrupt enable bit see THEN bit TxFIFO half status bit see TH bit TXFIFO LEVEL MARKER field 14 29 TxFIFO level marker field see TXFIFO LEVEL MARKER field...

Page 376: ...Z bit 2 CSB register 6 18 CSC register 6 18 CSD register 6 17 UPSIZ field CSB register 6 10 CSC register 6 12 CSD register 6 14 URX1 register 14 13 URX2 register 14 23 USTCNT1 register 14 10 USTCNT2 register 14 20 UTX1 register 14 14 UTX2 register 14 24 UWE UB pin 2 6 V VCO frequency changing 4 6 VECTOR field 9 7 Vector number coding 9 6 description 9 3 Vector number field see VECTOR field Virtual...

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