Motorola M68EM05P18, User Manual

Page: 18 / 56

General Description
Connector Information
M68EM05P18UM/D
18 General Description MOTOROLA
Table 2. Logic Analyzer Connector J1 Signal Descriptions
Pin Mnemonic Signal
1, 3, 4, 12, 14, 31, 33,
34, 35, 36, 40
NC No connection
2, 6 GND GROUND
5, 7, 9, 11, 13, 15, 17,
19, 21, 23, 25, 27
LA11–LA0
LATCHED ADDRESSES (bits 11–0) — MCU latched output address
bus
10, 8 LA13, LA12
LATCHED ADDRESSES (bits 13–12) — MCU latched output address
bus
16, 18, 20, 22, 24, 26,
28, 30
AD7–AD0 ADDRESS/DATA BUS (bits 7–0) — MCU multiplexed address/data bus
29 LR/W
LATCHED READ/WRITE — The MCU’s write signal is latched and
used on the platform board to control emulator memory accesses.
32 LIR
LOAD INSTRUCTION REGISTER — Active-low signal indicating an
opcode fetch cycle is in process
37 V
CC
+5 Vdc POWER — Connection to the system voltage V
CC
38 E
E CLOCK — Internally generated clock signal used as a timing
reference. The frequency of E is 1/2 the frequency of input clock
OSC1.
39 RESET
RESET — Active-low signal will be asserted during internally or
externally caused resets.