Motorola M68CPU32BUG User Manual Download

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TABLE OF CONTENTS

M68CPU32BUG/D REV 1

CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE

6.1

Introduction......................................................................................................................... 6-1

6.2

Diagnostic Monitor............................................................................................................. 6-1

6.2.1

Monitor Start-Up ...................................................................................................... 6-1

6.2.2

Command Entry and Directories.............................................................................. 6-1

6.2.3

Help (HE) ................................................................................................................. 6-2

6.2.4

Self Test (ST) ........................................................................................................... 6-2

6.2.5

Switch Directories (SD) ........................................................................................... 6-2

6.2.6

Loop-On-Error Mode (LE)....................................................................................... 6-2

6.2.7

Stop-On-Error Mode (SE) ........................................................................................ 6-3

6.2.8

Loop-Continue Mode (LC)....................................................................................... 6-3

6.2.9

Non-Verbose Mode (NV)......................................................................................... 6-3

6.2.10 Display Error Counters (DE).................................................................................... 6-3
6.2.11 Clear (Zero) Error Counters (ZE)............................................................................. 6-3
6.2.12 Display Pass Count (DP).......................................................................................... 6-3
6.2.13 Zero Pass Count (ZP) ............................................................................................... 6-4

6.3

Utilities ............................................................................................................................... 6-4

6.3.1

Write Loop ............................................................................................................... 6-4

6.3.2

Read Loop ................................................................................................................ 6-5

6.3.3

Write/Read Loop ...................................................................................................... 6-5

6.4

CPU Tests For The MCU (CPU)........................................................................................ 6-6

6.4.1

6.4.2

Instruction Test (CPU B).......................................................................................... 6-8

6.4.3

Address Mode Test (CPU C).................................................................................... 6-9

6.4.4

Exception Processing Test (CPU D) ...................................................................... 6-10

6.5

Memory Tests (MT).......................................................................................................... 6-11

6.5.1

Set Function Code (MT A)..................................................................................... 6-13

6.5.2

Set Start Address (MT B)....................................................................................... 6-14

6.5.3

Set Stop Address (MT C) ....................................................................................... 6-15

6.5.4

Set Bus Data Width (MT D)................................................................................... 6-16

6.5.5

March Address Test (MT E)................................................................................... 6-17

6.5.6

Walk a Bit Test (MT F).......................................................................................... 6-18

6.5.7

Refresh Test (MT G) .............................................................................................. 6-19

6.5.8

Random Byte Test (MT H)..................................................................................... 6-20

6.5.9

Program Test (MT I) .............................................................................................. 6-21

6.5.10 Test and Set Test (MT J) ........................................................................................ 6-22

6.6

Bus Error Test (BERR)..................................................................................................... 6-23

Summary of Contents for M68CPU32BUG

Page 2: ...ntended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against a...

Page 3: ... Parameter 2 4 2 2 1 3 Offset Registers 2 5 2 2 2 Port Numbers 2 7 2 3 Entering And Debugging Programs 2 7 2 4 Calling System Utilities From User Programs 2 7 2 5 Preserving Debugger Operating Environment 2 7 2 5 1 CPU32Bug Vector Table and Workspace 2 8 2 5 2 CPU32Bug Exception Vectors 2 8 2 5 2 1 Using CPU32Bug Target Vector Table 2 9 2 5 2 2 Creating Vector Tables 2 10 2 5 2 3 CPU32Bug Generali...

Page 4: ...ort Format PF 3 49 3 24 1 List Current Port Assignments 3 49 3 24 2 Port Configuration 3 49 3 24 3 Port Format Parameters 3 50 3 24 4 New Port Assignment 3 51 3 25 Register Display RD 3 52 3 26 Cold Warm Reset RESET 3 56 3 27 Register Modify RM 3 57 3 28 Register Set RS 3 58 3 29 Switch Directories SD 3 59 3 30 Trace T 3 60 3 31 Trace On Change Of Control Flow TC 3 63 3 32 Transparent Mode TM 3 65...

Page 5: ...DEC 5 4 5 2 2 Parse Value Assign to Variable CHANGEV 5 5 5 2 3 Check for Break CHKBRK 5 7 5 2 4 Timer Delay Function DELAY 5 8 5 2 5 Unsigned 32 x 32 Bit Divide DIVU32 5 9 5 2 6 Erase Line ERASLN 5 10 5 2 7 Input Character Routine INCHR 5 11 5 2 8 Input Line Routine INLN 5 12 5 2 9 Input Serial Port Status INSTAT 5 13 5 2 10 Unsigned 32 x 32 Bit Multiply MULU32 5 14 5 2 11 Output Character Routine...

Page 6: ...ss Count DP 6 3 6 2 13 Zero Pass Count ZP 6 4 6 3 Utilities 6 4 6 3 1 Write Loop 6 4 6 3 2 Read Loop 6 5 6 3 3 Write Read Loop 6 5 6 4 CPU Tests For The MCU CPU 6 6 6 4 1 Register Test CPU A 6 7 6 4 2 Instruction Test CPU B 6 8 6 4 3 Address Mode Test CPU C 6 9 6 4 4 Exception Processing Test CPU D 6 10 6 5 Memory Tests MT 6 11 6 5 1 Set Function Code MT A 6 13 6 5 2 Set Start Address MT B 6 14 6 ...

Page 7: ...ERROR MESSAGES B 1 Introduction B 1 APPENDIX C USER CUSTOMIZATION C 1 Introduction C 1 C 2 CPU32BUG Customization C 2 C 3 Customization Table C 5 C 4 Communication Formats C 14 C 5 BCC REV A Chip Selection Summary C 15 C 6 BCC REV B Chip Selection Summary C 16 C 7 BCC REV C Chip Selection Summary C 17 C 8 Platform Board PFB REV C Compatibility C 18 C 9 CPU32BUG Questions and Answers C 19 ...

Page 8: ... 8 3 1 Debug Monitor Commands 3 1 4 1 CPU32Bug Assembler Addressing Modes 4 7 5 1 CPU32Bug System Call Routines 5 3 6 1 MCU CPU Diagnostic Tests 6 6 6 2 Memory Diagnostic Tests 6 11 B 1 Self Test Error Messages B 1 C 1 CPU32Bug Customization Area C 5 C 2 MCU SCI Communication Formats C 14 C 3 Rev A Chip Selection Summary C 15 C 4 Rev B Chip Selection Summary C 16 C 5 BCC Rev C Chip Selection Summa...

Page 9: ... software debugger the debugger and A user interface which accepts commands from the system console terminal There are two modes of operation in the CPU32Bug monitor the debugger mode and the diagnostic mode When the user is in the debugger directory the prompt CPU32Bug is displayed and the user has access to the debugger commands see Chapter 3 When the user is in the diagnostic mode the prompt CP...

Page 10: ... DISPLAY RESULTS OF CONFIDENCE TEST GO TO MAIN SET DEBUGGER DIRECTORY INITILIZE BUG VARIBLES RUN SYSTEM CONFIDENCE TEST NO MAIN DISPLAY BUG PROMPT WAIT FOR INPUT EXECUTE COMMAND GO TO MAIN RESTORE TARGET STATE TARGET CODE EXECPTION EXCEPTION HANDLERS SAVE TARGET STATE DISPLAY TARGET REGISTERS YES NO DOES COMMAND CAUSE TARGET CODE EXECUTION Figure 1 1 CPU32Bug Operation Mode Flow Diagram ...

Page 11: ...ter 4 includes a description of the assembler disassembler NOTE In the examples shown all user inputs are given in bold text This should clarify the examples by distinguishing between character input by the user and character output by CPU32Bug The symbol CR represents the carriage return key on the user s terminal keyboard Whenever this symbol appears it indicates a carriage return should be ente...

Page 12: ...o their default states The serial port is reset to its default state The breakpoint table is cleared The offset registers are cleared The target registers are invalidated Input and output character queues are cleared On board devices timer serial ports etc are reset During WARM reset CPU32Bug variables and tables are preserved as well as the target state registers and breakpoints Use reset if the ...

Page 13: ... of code The EPROM on board the BCC contains 128k bytes and is mapped at locations E0000 to FFFFF However the CPU32Bug code is position independent and can execute anywhere in memory The second half of the EPROM F0000 FFFFF is blank and available for user programs See Appendix C CPU32Bug Customization CPU32Bug requires a minimum of 12k bytes of random access memory RAM to operate This memory may b...

Page 14: ...UG EPROM BCC U4 OPTIONAL RAM EPROM PFB U2 U4 110000 120000 5 1 Consult the MCU device User s Manual 2 XXXBase address is user programmable Internal MCU modules such as internal RAM can be configured on power up reset by using the Initialization Table INITTBL covered in Appendix C 3 Floating Point Coprocessor MC68881 MC68882 4 Platform Board 5 Depends on the memory device type used OPTIONAL FPCP 3 ...

Page 15: ...one position The character at the new cursor position is erased del delete rubout Performs the same function as H D redisplay The entire command line as entered is redisplayed on the following line When observing output from any CPU32Bug command the XON and XOFF characters may be entered to control the output if the XON XOFF protocol is enabled default These characters are initialized to S and Q r...

Page 16: ...GENERAL INFORMATION M68CPU32BUG D REV 1 1 8 ...

Page 17: ...so returns control to the debugger by means of the TRAP 15 function RETURN described in paragraph 5 2 16 Also refer to the paragraphs in Chapter 3 which detail elements of the GO commands In general debugger commands include A command identifier i e MD or md for the memory display command Both upper or lower case characters are allowed for command identifiers and options At least one intervening s...

Page 18: ...choice is to be made Select one of several symbols separated by a straight line Select one or more of the symbols separated by the slash Brackets enclose optional symbols that may occur zero or more times 2 2 1 Syntactic Variables The following syntactic variables are used in the command descriptions which follow In addition other syntactic variables may be used and are defined in the particular c...

Page 19: ...lue is assumed to be hexadecimal A numeric value may also be expressed as a string literal of as many as four characters The string literal must begin and end with single quote marks The numeric value is interpreted as the concatenation of the ASCII values of the characters This value is right justified as is any other numeric value String Literal Numeric Value in hex A 41 ABC 414243 TEST 54455354...

Page 20: ...xpression must be between 0 and FFFFFFFF 2 2 1 2 Address as a Parameter Many commands use ADDR as a parameter The syntax accepted by CPU32Bug is similar to the one accepted by the MC68300 Family one line assembler All control addressing modes are allowed An address offset register mode is also allowed Table 2 1 summarizes the address formats which are acceptable for address parameters in debugger ...

Page 21: ...gisters Eight pseudo registers R0 through R7 called offset registers are used to simplify the debugging of re locatable and position independent files These files when listed have a starting address normally 0 but when loaded into memory due to the offset registers they are loaded into a different memory location Implementing offset registers makes it harder to correlate addresses in the listing w...

Page 22: ...The disassembled code is CPU32Bug MD 427C DI CR 0000427C 48E78080 MOVEM L D0 A0 A7 00004280 4280 CLR L D0 00004282 1018 MOVE B A0 D0 00004284 5340 SUBQ W 1 D0 00004286 12D8 MOVE B A0 A1 00004288 51C8FFFC DBF D0 4286 0000428C 4CDF0101 MOVEM L A7 D0 Ao 00004290 4E75 RTS By using one of the offset registers the disassembled code address can be made to match the listing file address as follows CPU32Bu...

Page 23: ...wnload an object file from a host system i e a personal computer The program must be in S record format described in Appendix A and may be assembled or compiled on the host system The file is downloaded from the host into BCC memory via the debugger LO command Alternately the program may be created using the CPU32Bug MM command as outlined above and stored to the host using the DU dump command A c...

Page 24: ...uld be lost resulting in a loss of communication with the system terminal If a user program corrupts the system stack then an incorrect value may be loaded into the processor s counter causing the system to crash 2 5 2 CPU32Bug Exception Vectors The debugger exception vectors are listed below Do not change these specified vector offsets in the target program vector table or the associated debugger...

Page 25: ...on vector table of its own 2 5 2 1 Using CPU32Bug Target Vector Table CPU32Bug initializes and maintains a vector table area for target programs A target program is any user program started by the CPU32Bug with GO or Trace commands The starting address of this target vector table area is the base address of the BCC described in paragraph 1 6 This address is loaded into the target state vector base...

Page 26: ...ors at 10000 MOVE L 8 A0 D0 Get generalized exception vector MOVE W 3FC D1 Load count all vectors LOOP MOVE L D0 A1 D1 Store generalized exception vector SU BQ W 4 D 1 BPL B LOOP Initialize entire vector table MOVE L 1 0 A0 1 0 A1 Copy breakpoints vector MOVE L 24 A0 24 A1 Copy trace vector MOVE L BC A0 BC A1 Copy system call vector LEA L TIMER PC A2 Get user exception vector MOVE L A2 2C A1 Insta...

Page 27: ...xpected exception occurs during user code segment execution the exception stack frame displays to assist in determining the cause of the exception EXAMPLE Bus error at address F00000 It is assumed for this example that an access of memory location F00000 initiates bus error exception processing CPU32Bug RD CR PC 00003000 SR 2700 TR OFF_S_7_ VBR 00000000 SFC 5 SD DFC 5 SD USP 0000FC00 SSP 00004000 ...

Page 28: ...the MD command CPU32Bug MD A7 C CR 00003FE8 A700 0000 3000 C008 00F0 0000 FFFF 3000 0 p 0 00003FF8 0000 3000 0001 0065 0 e CPU32Bug 2 6 FUNCTION CODE SUPPORT Function codes identify the address space being accessed on any given bus cycle and are an extension of the address The function codes provide additional information required to find the proper memory location For this reason all debugger com...

Page 29: ...a GO GN or GD the default address space is determined by bit 13 the S bit of the status register SR When set SP is used when cleared UP is used By specifying a function code with GO GT or GD command the SR S bit is forced to the correct state before execution begins For the GT command the temporary breakpoint is set using the function code specified or it defaults to SP or UP depending on the stat...

Page 30: ...DEBUG MONITOR DESCRIPTION M68CPU32BUG D REV 1 2 14 ...

Page 31: ... Block of Memory Move 3 4 BR NOBR Breakpoint Insert Delete 3 5 BS Block of Memory Search 3 6 BV Block of Memory Verify 3 7 DC Data Conversion 3 8 DU Dump S Records 3 9 GD Go Direct Ignore Breakpoints 3 10 GN Go to Next Instruction 3 11 GO Go Execute User Program alias G 3 12 GT Go To Temporary Breakpoint 3 13 HE Help 3 14 LO Load S Records from Host 3 15 MA NOMA Macro Define Display Delete 3 16 MA...

Page 32: ...C Trace On Change of Control Flow 3 31 TM Transparent Mode 3 32 TT Trace To Temporary Breakpoint 3 33 VE Verify S Records Against Memory 3 34 Each command is described in the following text Command syntax symbols are explained in section 2 1 In the examples of the debugger commands all user inputs are in bold type This helps clarify examples by distinguishing user input characters from CPU32Bug ou...

Page 33: ... 16 bytes to the addr location If the range beginning address is greater than the end address an error results An error also results if an option field is specified without a count in the range For the following examples assume the following data is in memory CPU32Bug MD 4000 20 B CR 00004000 54 48 49 53 20 49 53 20 41 20 54 45 53 54 21 21 THIS IS A TEST 00004010 00 00 00 00 00 00 00 00 00 00 00 0...

Page 34: ...ss 00004000 Effective count 32 Effective address 00004100 CPU32Bug Memory compares nothing printed CPU32Bug MM 410F B CR 0000410F 21 0 CR CPU32Bug Create a mismatch CPU32Bug BC 4000 20 4100 B CR Effective address 00004000 Effective count 32 Effective address 00004100 0000400F 21 0000410F 00 CPU32Bug Mismatch is printed out ...

Page 35: ... assumed to be in terms of the data size Truncation always occurs on byte or word sized fields when negative values are entered For example entering 1 internally becomes FFFFFFFF which gets truncated to FF for byte or FFFF for word sized fields There is no difference internally between entering 1 and entering FFFFFFFFF so truncation occurs for byte or word sized fields If the upper address of the ...

Page 36: ...8 L CR Effective address 00004000 Effective address 00004003 CPU32Bug MD 4000 30 B CR 00004000 12 34 56 78 00 00 00 00 00 00 00 00 00 00 00 00 4Vx 00004010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00004020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 CPU32Bug The longword pattern would not fit evenly in the given range Only one longword was written and the Effective address messages refl...

Page 37: ...ption field is specified without a count in the range EXAMPLES Assume memory from 4000 to 402F is clear CPU32Bug MD 4100 20 B CR 00004100 544B 4953 2049 5320 4120 5445 5354 2121 THIS IS A TEST 00004110 0000 0000 0000 0000 0000 0000 0000 0000 CPU32Bug BM 4100 410F 4000 CR Effective address 00004100 Effective address 0000410F Effective address 00004000 CPU32Bug MD 4000 20 B CR 00004000 5448 4953 204...

Page 38: ...e address 00006004 CPU32Bug MD 6000 600C DI CR 00006000 D480 ADD L D0 D2 00006002 E2A2 ASR L D1 D2 00006004 E2A2 ASR L D1 D2 00006006 2602 MOVE L D2 D3 00006008 4E4F SYSCALL OUTSTR 0000600C 4E71 NOP Now the user need simply enter the NOP at address 6002 CPU32Bug MM 6002 DI CR 00006002 E2A2 ASR L D1 D2 NOP CR 00006002 4E71 NOP 00006004 E2A2 ASR L D1 D2 CR CPU32Bug CPU32Bug MD 6000 600C DI CR 000060...

Page 39: ...d each time either BR or NOBR is used If an address is specified with the BR command that address is added to the breakpoint table The count field specifies how many times the instruction at the breakpoint address is fetched before a breakpoint is taken The count field defaults to hexidecimal input unless a numeric identifier prefix is used The count if greater than zero is decremented with each f...

Page 40: ... following occurs during a data search 1 The user entered data pattern is right justified Leading bits are truncated or leading zeros are added as necessary to make the data pattern the specified size 2 Successive bytes words or longwords within the specified range are compared to the user entered data Comparison is made only on those bits at bit positions corresponding to a 1 in the mask If no ma...

Page 41: ... 00003000 0000 0045 7272 6F72 2053 7461 7475 733D Error Status 00003010 3446 2F2F 436F 6E66 6967 5461 626C 6553 4F ConfigTableS 00003020 7461 7274 3A00 0000 0000 0000 0000 0000 tart CPU32Bug BS 3000 302F Task Status CR Effective address 00003000 Mode 1 the string is not found so a Effective address 0000302F message is output not found CPU32Bug BS 3000 302F Error Status CR Effective address 0000300...

Page 42: ...n is 0000300F 3D34 found and displayed CPU32Bug BS 3000 30 60 F0 B CR Effective address 00003000 Effective count 48 00003006 6F 0000300B 61 00003015 6F 00003016 6E 00003017 66 00003018 69 00003019 67 0000301B 61 0000301C 62 0000301D 6C 0000301E 65 00003021 61 Mode 2 using RANGE with count mask option and size option count is displayed in decimal and the actual unmasked data patterns found are disp...

Page 43: ...eld or leading bits are truncated to size If truncation occurs then a message is printed stating the actual data pattern and or the actual increment value If the range is specified using a count then the count is assumed to be in terms of the data size Truncation always occurs on byte or word sized fields when negative values are entered For example entering 1 internally becomes FFFFFFFF which get...

Page 44: ... is as indicated CPU32Bug MD 5000 30 B CR 00005000 0000 0000 0000 0000 0000 0000 0000 0000 00005010 0000 0000 0000 0000 0000 0000 0000 0000 00005020 0000 0000 0000 0000 0000 4AFB 4AFB 4AFB J J J CPU32Bug BV 5000 30 0 B CR Effective address 00005000 Effective count 48 0000502A 4A 0000502B FB 0000502C 4A 0000502D FB 0000502E 4A 0000502F FB CPU32Bug Mismatches are printed out Assume memory from 7000 ...

Page 45: ...yed Use DC to obtain the equivalent effective address of an MCU device addressing mode EXAMPLES CPU32Bug DC 10 CR 00000010 10 16 CPU32Bug DC 10 20 CR SIGNED FFFFFFF6 A 10 UNSIGNED FFFFFFF6 FFFFFFF6 4294967286 CPU32Bug DC 123 345 67 1100001 CR 00000314 314 788 CPU32Bug DC 2 3 8 4 CR 0000000C C 12 CPU32Bug DC 55 F CR 00000005 5 5 CPU32Bug DC 55 1 CR 0000002A 2A 42 The subsequent examples assume A0 0...

Page 46: ...nter an entry address for code contained in the block of records This address is incorporated into the address field of the block s termination record If no entry address is entered then the address field of the termination record will contain the beginning range address The termination record is an S7 S8 or S9 record and depends upon the entered address An optional offset may also be specified by...

Page 47: ...oComm terminal emulation utility Assume memory from 4000 to 4007 is initialized as follows CPU32Bug MD 4000 4 DI CR 00004000 7001 MOVEQ L 1 D0 00004002 D089 ADD L A1 D0 00004004 4A00 TST B D0 00004006 4E75 RTS CPU32Bug Enter the following command to dump S records from memory locations 4000 4007 with a start address of 4000 a title of TEST MX and an offset of 65000000 Before entering the CR to sen...

Page 48: ...er ALT F1 again to close the log file TEST MX The log file contains the extra lines of Effective address and CPU32Bug but they will not affect subsequent CPU32Bug load LO commands as it keys on the S character The file could be edited to remove the extra lines if so desired ...

Page 49: ...rned to CPU32Bug by various conditions Press the ABORT switch or RESET switch of the M68300PFB Platform Board Execute the RETURN TRAP 15 function Generation of an unexpected exception EXAMPLE The following program resides at 4000 CPU32Bug MD 4000 DI CR 00004000 2200 MOVE L D0 D1 00004002 4282 CLR L D2 00004004 D401 ADD B D1 D2 00004006 E289 LSR L 1 D1 00004008 66FA BNE B 4004 0000400A E20A LSR B 1...

Page 50: ...0 F0 DFC 0 F0 USP 0000FC00 SSP 0000FF50 D0 00052A9C D1 00000000 D2 000000FF D3 00000000 D4 00000000 D5 00000000 D6 00000000 D7 00000000 A0 00005000 A1 00000000 A2 00000000 A3 00000000 A4 00000000 A5 00000400 A6 00000000 A7 0000FF50 0000400E 60FE BRA B 400E CPU32Bug Set PC to start of program and restart target code CPU32Bug RM PC CR PC 0000400E 4000 CR CPU32Bug GD CR Effective address 00004000 ...

Page 51: ...tion EXAMPLE The following section of code resides at 6000 CPU32Bug MD 6000 4 DI CR 00006000 7003 MOVE L 3 D0 00006002 7201 MOVEQ L 1 D1 00006004 61000FFA BSR W 7000 00006008 2600 MOVE L D0 D3 CPU32Bug The following simple subroutine resides at address 7000 CPU32Bug MD 7000 2 DI CR 00007000 D081 ADD L D1 D0 00007002 4E75 RTS CPU32Bug Execute up to the BSR instruction CPU32Bug RM PC CR PC 00003000 ...

Page 52: ...empory breakpoint at 6004 Effective address 00006004 Current PC at 6000 At Breakpoint PC 00006008 SR 2700 TR OFF_S_7_ VBR 00000000 SFC 0 F0 DFC 0 F0 USP 00003830 SSP 00010000 D0 00000004 D1 00000001 D2 00000000 D3 00000000 D4 00000000 D5 00000000 D6 00000000 D7 00000000 A0 00000000 A1 00000000 A2 00000000 A3 00000000 A4 00000000 A5 00000000 A6 00000000 A7 00010000 00006008 2600 MOVE L D0 D3 CPU32B...

Page 53: ... at the target PC executed in trace mode 3 All breakpoints are inserted in the target code 4 Target code execution resumes at the target PC address There are several methods for returning control to CPU32Bug Execute the RETURN TRAP 15 function Press the ABORT switch or RESET switch of the M68300PFB Platform Board Encountering a breakpoint with 0 count Generation of an unexpected exception EXAMPLE ...

Page 54: ...000000 A5 00000000 A6 00000000 A7 00010000 0000400E 60FE BRA B 400E Note that in this case breakpoints are inserted after tracing the first instruction therefore the first breakpoint is not taken Continue target program execution CPU32Bug G CR Effective address 0000400E At Breakpoint PC 0000400E SR 2711 TR OFF_S_7_X C VBR 00000000 SFC 5 SD DFC 5 SD USP 0000FC00 SSP 00010000 D0 00052A9C D1 00000000...

Page 55: ...target code Exception ABORT PC 0000400E SR 2711 TR OFF_S_7_X C VBR 00000000 SFC 5 SD DFC 5 SD USP 0000FC00 SSP 00010000 D0 00052A9C D1 00000000 D2 000000FF D3 00000000 D4 00000000 D5 00000000 D6 00000000 D7 00000000 A0 00000000 A1 00000000 A2 00000000 A3 00000000 A4 00000000 A5 00000000 A6 00000000 A7 00010000 0000400E 60FE BRA B 400E ...

Page 56: ...t control is returned to CPU32Bug by Executing the RETURN SYSCALL TRAP 15 function Press the ABORT switch or RESET switch of the M68300PFB Platform Board Encountering a breakpoint with 0 count Generation of an unexpected exception EXAMPLE The following program resides at 4000 CPU32Bug MD 4000 DI CR 00004000 2200 MOVE L D0 D1 00004002 4282 CLR L D2 00004004 D401 ADD B D1 D2 00004006 E289 LSR L 1 D1...

Page 57: ...A6 00000000 A7 00010000 00004006 E289 LSR L 1 D1 CPU32Bug Set another temporary breakpoint at 4002 and continue target program execution CPU32Bug GT 4002 CR Effective address 00004002 Tempory breakpoint at 4002 Effective address 00004006 Current PC at 4006 At Breakpoint PC 0000400E SR 2711 TR OFF_S_7_X C VBR 00000000 SFC 0 F0 DFC 0 F0 USP 00003830 SSP 00010000 D0 00052A9C D1 00000000 D2 000000FF D...

Page 58: ...ed command name and title EXAMPLES CPU32Bug HE CR BC Block Compare BF Block Fill BM Block Move BR Breakpoint Insert NOBR Breakpoint Delete BS Block Search BV Block Verify DC Data Conversion and Expression Evaluation DU Dump S Records GD Go Direct no breakpoints GN Go and Stop after Next Instruction GO Go to Target Code G Alias for previous command GT Go and Insert Temporary Breakpoint HE Help Faci...

Page 59: ...Verbose Mode MT Memory Tests Dir RL Read Loop Dir SE Stop on Error Mode SM Modify Self Test Mask ST Self Test Sequence WL Write Loop Dir WR Write Read Loop Dir ZE Clear Error Counters ZP Zero Pass Count BC Block Compare BF Block Fill BM Block Move BR Breakpoint Insert NOBR Breakpoint Delete BS Block Search BV Block Verify DC Data Conversion and Expression Evaluation DU Dump S Records GD Go Direct ...

Page 60: ...ffset Registers PA Printer Attach NOPA Printer Detach PF Port Format RD Register Display RESET Warm Cold Reset RM Register Modify RS Register Set SD Switch Directory T Trace Instruction TC Trace on Change of Flow TM Transparent Mode TT Trace to Temporary Breakpoint VE Verify S Records CPU32Bug To display the command TC enter CPU32Bug HE TC CR TC Trace on Change of Flow CPU32Bug ...

Page 61: ...nge 0 to 1F and the port number is omitted enter a comma before the address to distinguish it from a port number Only absolute addresses i e 1000 should be entered as other addressing modes cause unpredictable results An address is allowed here rather than an offset expression to permit support for function codes see paragraph 2 5 The optional text field entered after the equal sign is sent to the...

Page 62: ...ermination record The contents of the termination record address field plus any offset address is put into the target PC Thus after a download the user need only enter G or GO instead of G addr or GO addr to execute the downloaded code If a non hex character is encountered within the data field of a data record then that part of the record preceeding the non hex character is displayed This causes ...

Page 63: ... CPU32Bug LO 65000000 CR Blank line as the BCC waits for an S record Enter the terminal emulator s escape key to return to the host computer s operating system ALT F4 for ProComm A host command is then entered to send the S record file to the port where the BCC is connected for MS DOS based host computer this would be type test mx com1 where the BCC was connected to the com1 port After the file ha...

Page 64: ...macro definition prompt M enter a CPU32Bug command and a carriage return Commands entered are not checked for syntax until the macro is executed To exit the macro definition mode enter only a carriage return null line in response to the prompt If the macro contains errors it can either be deleted and redefined or it can be edited with the MAE command A macro containing no primitive CPU32Bug comman...

Page 65: ...ros If NOMA is executed with a valid macro name that does not have a definition an error message is printed EXAMPLES CPU32Bug MA ABC CR Define macro ABC M MD 3000 M GO 0 M CR CPU32Bug CPU32Bug MA DASM CR Define macro DASM M MD 0 5 DI M CR CPU32Bug CPU32Bug MA CR List macro definitions MACRO ABC 010 MD 3000 020 GO 0 MACRO DIS 010 MD 0 5 DI CPU32Bug CPU32Bug DASM 427C CR Execute DASM macro 0000427C ...

Page 66: ...NOMA Macro Delete NOMA CPU32Bug MA ASM CR Define macro ASM M MM 0 DI M CR CPU32Bug CPU32Bug MA CR List all macros MACRO ABC 010 MD 3000 020 GO 0 MACRO ASM 010 MD 0 DI CPU32Bug CPU32Bug NOMA CR Delete all macros CPU32Bug CPU32Bug MA CR List all macros NO MACROS DEFINED CPU32Bug ...

Page 67: ...d must also be specified on the command line following the line number To replace a line specify its line number and enter the replacement text after the line number on the command line A line is deleted if its line number is specified and the replacement line is omitted Attempting to delete a nonexistent line results in an error message being printed MAE does not permit deletion of a line if the ...

Page 68: ...000 020 GO 0 CPU32Bug CPU32Bug MAE ABC 15 RD CR Add a line to macro ABC MACRO ABC 010 MD 3000 020 RD This line was inserted 030 GO 0 CPU32Bug CPU32Bug MAE ABC 10 MD 10 R0 CR Replace line 10 MACRO ABC 010 MD 10 R0 This line was overwritten 020 RD 030 GO 0 CPU32Bug CPU32Bug MAE ABC 30 CR Delete line 30 MACRO ABC 010 MD 10 R0 020 RD CPU32Bug ...

Page 69: ...AL NOMAL The MAL command allows the user to view expanded macro lines as they are executed This is especially useful when errors result as the line with the error appears on the display The NOMAL command is used to suppress the listing of macro lines during execution The use of MAL and NOMAL is a convenience for the user and in no way interacts with the function of the macros ...

Page 70: ...f data items to be displayed or the number of disassembled instructions to display if the disassembly option is selected The default is 8 if no value for count is entered The default count is changed to 128 if the S sector modifier is used After the command has completed enter CR at the prompt to re execute the command and display the same number of lines of data beginning at the next address EXAM...

Page 71: ... 00005012 4E7AD801 MOVEC L VBR A5 00005016 41ED7FFC LEA L 7FFC A5 A0 0000501A 5888 ADDQ L 4 A0 0000501C 2E48 MOVE L A0 A7 0000501E 2C48 MOVE L A0 A6 00005020 13C7FFFB003A MOVE B D7 FFFB003A L CPU32Bug NOTE If the address location requested is not displayed the automatic offset register is non zero and has been added to the address See the offset OF command ...

Page 72: ... prompt or after writing new data Enter one of the following step control characters to modify the command execution V or v The next successive memory location is opened This is the default It initializes whenever MM is executed and remains initialized until changed by entering one of the other special characters MM backs up and opens the previous memory location MM re opens the same memory locati...

Page 73: ...08 0000 CR Exit MM CPU32Bug MD 4000 CR 00004008 0041 0042 4344 4647 0000 0000 0000 0000 A BCDFG CPU32Bug The DI option activates the one line assembler disassembler All other options are invalid if DI is selected The contents of the specified memory location is disassembled and displayed and the user prompted for an input with a question mark At this point the user has three options Enter CR This ...

Page 74: ...tring enter two consecutive quotes EXAMPLE Memory is initially cleared CPU32Bug ms 25000 0123456789abcDEF This is CPU32Bug 23456 CR CPU32Bug md 25000 10 w CR 00025000 0123 4567 89AB CDEF 5468 6973 2069 7320 Eg MoThis is 00025010 2733 3332 4275 6727 2345 6000 0000 0000 CPU32Bug E CPU32Bug NOTE If the address location requested is not displayed the automatic offset register is non zero and has been ...

Page 75: ...ddress address format or an address count format When specifying a count the value of count is in bytes If the top address is omitted from the range then a top address of FFFFFFFF is the default The top address must equal or exceed the base address Wrap around is not permitted Command usage OF Display all offset registers An asterisk indicates which register is the automatic register OF Rn Display...

Page 76: ... displayed entered absolutely However the RS register set command does use the automatic register There is always an automatic register To disable the effect of the automatic register set R7 as the automatic register This is the default condition EXAMPLES Display offset registers Shows base and top values for each register CPU32Bug OF CR R0 00000000 00000000 R1 00000000 00000000 R2 00000000 000000...

Page 77: ...PU32Bug OF R0 A CR R0 00005000 000050FF CR Display location 0 relative to the default offset register R0 i e absolute location 5000 CPU32Bug M 0 DI CR 00000 R0 41F95445 5354 LEA L 54455354 L A0 CR CPU32Bug Display absolute location 0 override the automatic offset CPU32Bug M 0 R7 DI CR 00000000 FFF8 DC W FFF8 CR CPU32Bug ...

Page 78: ...splays an error message If NOPA is attempted on a printer that is not currently attached an error message is displayed Use the PF port format command to configure the port before attaching a printer to it RECOVERING FROM A HUNG PRINTER attached ports are not detached by exceptions bus errors abort etc If PA is executed using incorrect parameters or a fault such as a paper jam occurs press the RESE...

Page 79: ...umber lists the board and port names EXAMPLE CPU32Bug PF CR Current port assignments Port Board name Port name 00 BCC SCI CPU32Bug 3 24 2 Port Configuration Use PF to primarily change baud rates stop bits etc Execute the PF command with the desired port number to assign and configure port parameters Refer to paragraph 3 20 4 New Port Assignment When PF is executed with the number of a previously a...

Page 80: ...0 2400 4800 9600 19200 Parity type Set parity even E odd 0 or disabled N Character width Select 5 6 7 or 8 bit characters Number of stop bits Only 1 and 2 stop bits are supported Automatic software handshake Current drivers have the capability of responding to XON XOFF characters sent to the debugger ports Receiving a XOFF causes a driver to cease transmission until a XON character is received Non...

Page 81: ...ration mode the user is allowed to change the port base address Press RETURN to retain the present base address If the configuration of the new port is not fixed then the system enters the interactive configuration mode Refer to paragraph 3 20 2 regarding configuring assigned ports If the new port has a fixed configuration then PF issues the OK to proceed Y N prompt The user must enter the letter ...

Page 82: ...ommand Optional arguments allow the user the capability to enable or disable the display of any register or group or registers This is useful for showing only the registers of interest minimizing unnecessary data on the screen The arguments are Add a device or register range Remove a device or register range except when used between two register names In which case it indicates a register range Se...

Page 83: ...o right with each field being processed after parsing thus the sequence in which qualifiers and registers are organized has an impact on the resultant register mask When specifying a register range REG1 and REG2 do not have to be of the same class i e D0 A7 The register mask used by RD is also used by all the exception handler routines including the trace and breakpoint exception handlers The MPU ...

Page 84: ... status register it includes a mnemonic portion These mnemonics are Trace Bits The trace bits T0 T1 control the trace feature of the MCU and are displayed by the mnemonic as shown in the following table The user should not modify these bits when executing user programs T1 T0 Mnemonic Description 0 0 TR OFF Trace off 0 1 TR CHG Trace on change of flow 1 0 TR ALL Trace all states 1 1 TR INV Invalid ...

Page 85: ...RD D6 A3 CR D6 00000000 A3 00000000 00003000 4AFC ILLEGAL CPU32Bug Note that the above sequence sets the display to D6 only and then adds register A3 to the display To restore all the MPU registers CPU32Bug rd mpu CR PC 00003000 SR 2700 TR OFF_S_7_ VBR 00000000 SFC 0 F0 DFC 0 F0 USP 00003830 SSP 00004000 D0 00000000 D1 00000000 D2 00000000 D3 00000000 D4 00000000 D5 00000000 D6 00000000 D7 0000000...

Page 86: ...ode of operation and is the default at power up In this mode all the static variables are initialized every time a reset is executed WARM In this mode all the static variables are preserved when a reset exception occurs This is convenient for keeping breakpoints offset register values the target register state and any other static variables in the system EXAMPLE CPU32Bug RESET CR Cold Warm Start C...

Page 87: ...nctions in essentially the same way as the MM command and the same step control characters are used to control the display change session Refer to the MM command EXAMPLES CPU32Bug RM D4 CR D5 12345678 ABCDEF CR Modify register and backup D4 00000000 3000 CR Modify register and exit CPU32Bug CPU32Bug rm sfc CR SFC 7 CS 1 CR Modify register and re open SFC 1 UD CR Exit CPU32Bug ...

Page 88: ... only valid when reg is an offset register i e R0 R7 Use the A option to set reg as the automatic register If R7 is specified no exp is allowed R7 cannot be changed See the OF offset register command EXAMPLES CPU32Bug RS PC 40 1000 4 CR PC 00040004 CPU32Bug CPU32Bug OF R4 A CR R4 00000000 00000000 4000 4FFF CR Set up automatic offset register R4 CPU32Bug RS PC 124 CR PC 00004124 Set PC 124 R4 CPU3...

Page 89: ... list the current directory commands Directory structure allows access to the debugger commands from either directory but the diagnostic commands are only available from the diagnostic directory EXAMPLES CPU32Bug SD CR CPU32Diag The user has changed from the debugger directory to the diagnostic directory as can be seen by the CPU32Diag prompt CPU32Diag SD CR CPU32Bug The user is now back in the de...

Page 90: ...h 0 count is encountered Trace functions are implemented with the trace bits T0 T1 in the MCU device status register Do not modify trace bits T0 T1 while using the trace commands Because the trace functions are implemented using the hardware trace bits in the MCU code in ROM can be traced During trace mode breakpoints are monitored and their counts decremented when the corresponding instruction wi...

Page 91: ...02 SR 2700 TR OFF_S_7_ VBR 00000000 SFC 0 F0 DFC 0 F0 USP 0000382C SSP 00004000 D0 0008F41C D1 0008F41C D2 002003A2 D3 00000000 D4 00000000 D5 00000000 D6 00000000 D7 00000000 A0 00000000 A1 00000000 A2 00000000 A3 00000000 A4 00000000 A5 00000000 A6 00000000 A7 00004000 00007002 4282 CLR L D2 CPU32Bug Trace next instruction CPU32Bug CR PC 00007004 SR 2704 TR OFF_S_7_ Z VBR 00000000 SFC 0 F0 DFC 0...

Page 92: ...0000 D6 00000000 D7 00000000 A0 00000000 A1 00000000 A2 00000000 A3 00000000 A4 00000000 A5 00000000 A6 00000000 A7 00004000 00007006 E289 LSR L 1 D1 PC 00007008 SR 2700 TR OFF_S_7_ VBR 00000000 SFC 0 F0 DFC 0 F0 USP 0000382C SSP 00004000 D0 0008F41C D1 00047A0E D2 0000001C D3 00000000 D4 00000000 D5 00000000 D6 00000000 D7 00000000 A0 00000000 A1 00000000 A2 00000000 A3 00000000 A4 00000000 A5 00...

Page 93: ...oint only if it is at a change of flow instruction Control is returned to CPU32Bug if a breakpoint with 0 count is encountered See the trace T command for more details The trace functions are implemented with the trace bits T0 T1 in the MCU device status register Do not modify the trace bits T0 T1 while using the trace commands Because the trace functions are implemented using the hardware trace b...

Page 94: ...00 TR OFF_S_7_ VBR 00000000 SFC 0 F0 DFC 0 F0 USP 0000382C SSP 00004000 D0 0008F41C D1 00047A0E D2 0000001C D3 00000000 D4 00000000 D5 00000000 D6 00000000 D7 00000000 A0 00000000 A1 00000000 A2 00000000 A3 00000000 A4 00000000 A5 00000000 A6 00000000 A7 00004000 00007004 D401 ADD B D1 D2 CPU32Bug Note that the above display also shows the change of flow instruction ...

Page 95: ...port 1 The port number must be within the range 0 to 1F Ports do not have to have the same baud rate but for reliable operation the terminal port baud rate should be equal to or greater than the host port baud rate Use the PF command to change baud rates The optional escape argument allows the user to specify the exit character Use one of three formats ascii code 03 Set escape character to C ascii...

Page 96: ...tered See the trace T command for more details The trace functions are implemented with the trace bits T0 T1 in the MCU status register Do not modify trace bits T0 T1 while using the trace commands Because the trace functions are implemented using the hardware trace bits in the MCU code in ROM can be traced During trace mode breakpoints are monitored and their counts decremented when the correspon...

Page 97: ... PC 00007004 SR 2704 TR OFF_S_7_ Z VBR 00000000 SFC 0 F0 DFC 0 F0 USP 0000382C SSP 00004000 D0 0008F41C D1 0008F41C D2 00000000 D3 00000000 D4 00000000 D5 00000000 D6 00000000 D7 00000000 A0 00000000 A1 00000000 A2 00000000 A3 00000000 A4 00000000 A5 00000000 A6 00000000 A7 00004000 00007004 D401 ADD B D1 D2 At Breakpoint PC 00007006 SR 2700 TR OFF_S_7_ VBR 00000000 SFC 0 F0 DFC 0 F0 USP 0000382C ...

Page 98: ...ress which is added to the address contained in the record address field This causes the records to be compared to memory at different locations than would normally occur The contents of the automatic offset register are not added to the S record addresses If the address is in the range 0 to 1F and the port number is omitted precede the address with a comma to distinguish it from a port number Onl...

Page 99: ...ith the address contained in the S record address field plus the offset address If the verification fails then the non comparing record is set aside until the verify is complete and then it is displayed on the screen If three non comparing records are encountered in the course of a verify operation then the command is aborted If a non hex character is encountered within the data field then the rec...

Page 100: ...CC waits for an S record Enter the terminal emulator s escape key to return to the host computer s operating system ALT F4 for ProComm A host command is then entered to send the S record file to the port where the BCC is connected for MS DOS based host computer this would be type test mx com1 where the BCC was connected to the com1 port After the file has been sent the user then restarts the termi...

Page 101: ... the BCC is connected for MS DOS based host computer this would be type test mx com1 where the BCC was connected to the com1 port After the file has been sent the user then restarts the terminal emulation program for MS DOS based host computers enter EXIT at the prompt Since the port number equals the current terminal two CR s are required to signal CPU32Bug that verification is complete and the t...

Page 102: ...DEBUG MONITOR COMMANDS M68CPU32BUG D REV 1 3 72 ...

Page 103: ...r creating modifying and debugging code of the M68300 Family 4 1 1 M68300 Family Assembly Language M68300 Family assembly language is the symbolic language used to code source programs for processing by the assembler This language is a collection of mnemonics representing Operations M68300 Family machine instruction operation code Directives pseudo ops Operators Special symbols 4 1 1 1 Machine Ins...

Page 104: ... as mnemonics and operands Only two directives DC W and SYSCALL are accepted No macro operation capability is included No conditional assembly is used No structured assembly is used Several symbols recognized by the resident assembler are not included in the CPU32Bug assembler character set These symbols include and Three other symbols have multiple meaning to the resident assembler depending on t...

Page 105: ...ult size applicable to the instruction is used The size code need not be specified if only one data size is permitted by an operation The operation field is followed by a period and the data size code The data size codes are B Byte 8 bit data W Word 16 bit data the usual default size L Longword 32 bit data When the instruction or directive does not have a data size attribute the data size code is ...

Page 106: ... to the source line entered The disassembler decides how to interpret the numbers used If the number is an offset of an address register it is treated as a signed hexadecimal offset Otherwise it is treated as a straight unsigned hexadecimal EXAMPLE MOVE L 1234 5678 MOVE L FFFFFFFC A0 5678 disassembles to 00003000 21FC0000 12345678 MOVE L 1234 5678 W 00003008 21E8FFFC 5678 MOVE L 4 A0 5678 W Also f...

Page 107: ...e operands 00003000 21FC0000 12345678 MOVE L 1234 5678 W 005000 0053 DC W S 005002 223C41424344 MOVE L ABCD D1 005008 3536 DC W 56 The following register mnemonics are recognized referenced by the assembler disassembler Pseudo Registers R0 R7 User Offset Registers Main Processor Registers PC Program Counter Used only in forcing program counter relative addressing SR Status Register CCR Condition C...

Page 108: ...llar sign specifies a hexadecimal number ampersand specifies a decimal number commercial at sign specifies an octal number percent sign specifies a binary number apostrophe specifies an ASCII literal character string Five separating characters Space period slash dash The asterisk character indicates current location 4 2 2 Addressing Modes Effective address modes combined with operation codes defin...

Page 109: ... An Xi Address register indirect with index base displacement ADDR PC Program counter indirect with displacement ADDR PC Xi Program counter indirect with index 8 bit displacement ADDR PC Xi Program counter indirect with index base displacement xxxx W Absolute word address xxxx L Absolute long address xxxx Immediate data The user may use an expression in any numeric field of these addressing modes ...

Page 110: ...te numbers and registers to avoid confusion For example CLR D0 means CLR W register D0 On the other hand CLR D0 CLR 0D0 CLR D0 CLR D0 0 all mean CLR W memory location D0 With the use of asterisk to represent both multiply and program counter how does the assembler know when to use which definition For parsing algebraic expressions the order of parsing is OPERAND OPERATOR OPERAND OPERATOR with a po...

Page 111: ...cates that register is suppressed If the user does not specify the index register the default is ZD0 W 1 Any unspecified displacements are defaulted to 0 4 2 3 Define Constant Directive DC W The format for the DC W directive is DC W operand This directive defines a constant in memory The DC W directive has only one operand 16 bit value which can contain the actual value decimal hexadecimal or ASCI...

Page 112: ...version Refer to Chapter 5 SYSTEM CALLS for a complete listing of all the functions provided 4 3 ENTERING AND MODIFYING SOURCE PROGRAM User programs are entered into memory using the one line assembler disassembler The program is entered in assembly language statements on a line by line basis The source code is not saved as it is converted immediately upon entry into machine code This imposes seve...

Page 113: ...recedence to instructions a word of data interpreted as a valid instruction is returned as the instruction 4 3 2 Entering a Source Line Enter a new source line immediately following the disassembled line Use the format discussed in paragraph 4 2 1 CPU32Bug MM 6000 DI CR 00006000 2600 MOVE L D0 D3 ADDQ L 1 A3 CR When a line is terminated with a carriage return the old source line is erased from the...

Page 114: ...he user may enter an asterisk for branch to self in order to reserve space After the actual address is discovered the line containing the branch instruction can be re entered using the correct value Enter branch sizes B or W as opposed to S and L 4 3 4 Assembler Output Program Listings Use the MD Memory Display command with the DI option to obtain a listing of the program The MD command requires t...

Page 115: ...program simply insert a TRAP 15 instruction into the source program The code corresponding to the particular system routine is specified in the word following the TRAP opcode as shown in the following example Format in user program TRAP 15 System call to CPU32Bug DC W xxxx Routine being requested xxxx code In some of the examples shown in the following descriptions a SYSCALL macro is used with the...

Page 116: ...D0 SYSCALL OUTLN CR 0000 3000 4E3F0022 SYSCALL OUTLN 0000 3004 00000000 ORI B 0 D0 CR CPU32Bug 5 1 2 Input Output String Formats Within the context of the TRAP 15 handler are three string formats Pointer Pointer Format The string is defined by a pointer to the first character and a pointer to the last character 1 Pointer Count Format The string is defined by a pointer to a count byte which contain...

Page 117: ...integers OUTCHR 0020 Output character OUTLN 0022 Output line pointer pointer format OUTSTR 0021 Output string pointer pointer format PCRLF 0026 Output carriage return and line feed READLN 0004 Input line pointer count format READSTR 0003 Input string pointer count format RETURN 0063 Return to CPU32Bug SNDBRK 0029 Send break STRCMP 0068 Compare two strings pointer count format TM_INI 0040 Timer ini...

Page 118: ...s a 32 bit unsigned binary number and changes it to its equivalent BCD Binary Coded Decimal Number Entry Conditions SP Argument Hex number long Space for result 2 long Exit Conditions SP Decimal number 2 Most Significant Digits long 8 Most Significant Digits long EXAMPLE SUBQ L 8 A7 Allocate space for result MOVE L D0 A7 Load hex number SYSCALL BINDEC Call BINDEC MOVEM L A7 D1 D2 Load result into ...

Page 119: ...and assigned to the variable unless the user s input is an empty string Entry Conditions SP Address of 32 bit offset into user s buffer Address of user s buffer pointer count format string Address of 32 bit integer variable to change Address of string to use in prompting and displaying value Exit Conditions SP Top of stack EXAMPLE PROMPT DC B 14 COUNT 10 8 GETCOUNT PEA PROMPT PC Point to prompt st...

Page 120: ...art address not the address of the first character in the buffer to the next character to process In this case a value of 2 in POINT indicates that the space between 1 and 3 is the next character to be processed After calling CHANGEV the screen displays COUNT 3 If the above code was called again nothing could be parsed from BUFFER so a prompt would be issued For example if the string 5 is entered ...

Page 121: ... Break SYSCALL CHKBRK TRAP CODE 0005 Returns zero 0 status in condition code register if break status is detected at the default input port Entry Conditions No arguments or stack allocation required Exit Conditions Z flag set in CCR if break detected EXAMPLE SYSCALL CHKBRK BEQ BREAK ...

Page 122: ...nerated DELAY returns system control to the user after the specified delay is completed Initialize TM_INI and start TM_STR0 the timer before using the TM_RD function Entry Conditions SP Delay time number of interrupt pulses long Exit Conditions Different From Entry SP The timer keeps running after the delay and parameters are removed from the stack EXAMPLE SYSCALL TM INI Initialize timer SYSCALL T...

Page 123: ...The case of division by zero is handled by returning the maximum unsigned value FFFFFFFF Entry Conditions SP 32 bit divisor value to divide by 32 bit dividend value to divide 32 bit space for result Exit Conditions SP 32 bit quotient result from division EXAMPLE Divide D0 by D1 load result into D2 SUBQ L 4 A7 Allocate space for result MOVE L D0 A7 Push dividend MOVE L D1 A7 Push divisor SYSCALL DI...

Page 124: ...ine ERASLN 5 2 6 Erase Line SYSCALL ERASLN TRAP CODE 0027 Use ERASLN to erase the line at the present cursor position Entry Conditions No arguments required Exit Conditions The cursor is positioned at the beginning of a blank line EXAMPLE SYSCALL ERASLN ...

Page 125: ...NCHR TRAP CODE 0000 Reads a character from the default input port The character remains in the stack Entry Conditions SP Space for character byte Word fill byte Exit Conditions SP Character byte Word fill byte EXAMPLE SUBQ L 2 A7 Allocate space for result SYSCALL INCHR Call INCHR MOVE B A7 D0 Load character in D0 ...

Page 126: ...e string 1 long EXAMPLE If A0 contains the string destination address SUBQ L 4 A7 Allocate space for result PEA A0 Push pointer to destination TRAP 15 May also invoke by SYSCALL DC W 2 macro SYSCALL INLN MOVE L A7 A1 Retrieve address of last character 1 NOTE A line is a string of characters terminated by a carriage return CR The maximum allowed size is 254 characters The terminating CR is not incl...

Page 127: ...fer for characters The condition codes are set to indicate the result of the operation Entry Conditions No arguments or stack allocation required Exit Conditions Z zero 1 if the receiver buffer is empty EXAMPLE LOOP SYSCALL INSTAT Any characters BEQ S EMPTY If no branch SUBQ L 2 A7 If yes then read them in buffer SYSCALL INCHR MOVE B A7 A0 BRA S LOOP Check for more EMPTY ...

Page 128: ...he stack as a 32 bit unsigned integer No overflow checking is performed Entry Conditions SP 32 bit multiplier 32 bit multiplicand 32 bit space for result Exit Conditions SP 32 bit product result from multiplication EXAMPLE Multiply D0 by D1 load result into D2 SUBQ L 4 A7 Allocate space for result MOVE L D0 A7 Push multiplicand MOVE L D1 A7 Push multiplier SYSCALL MULU32 Multiply D0 by D1 MOVE L A...

Page 129: ...YSCALL OUTCHR TRAP CODE 0020 Outputs a character to the default output port Entry Conditions SP Character byte Word fill byte Placed automatically by the MCU Exit Conditions SP Top of stack Character is sent to the default I O port EXAMPLE MOVE B D0 A7 Send character in D0 SYSCALL OUTCHR To default output port ...

Page 130: ...ODE 0021 OUTSTR outputs a string of characters to the default output port OUTLN outputs a string of characters followed by a CR LF sequence Entry Conditions SP Address of first character long 4 Address of last character 1 long Exit Conditions SP Top of stack EXAMPLE If A0 start of string and A1 end of string 1 MOVEM L A0 A1 A7 Load pointers to string and print it SYSCALL OUTSTR ...

Page 131: ... 5 2 13 Print Carriage Return and Line Feed SYSCALL PCRLF TRAP CODE 0026 PCRLF sends a carriage return and a line feed to the default output port Entry Conditions No arguments or stack allocation required Exit Conditions None EXAMPLE SYSCALL PCRLF Output a carriage return and line feed ...

Page 132: ...ber of characters in the input string excluding carriage return CR and line feed LF A string may be as many as 254 characters Entry Conditions SP Address of input buffer long Exit Conditions SP Top of stack The first byte in the buffer indicates the string length EXAMPLE If A0 points to a 256 byte buffer PEA A0 Long buffer address SYSCALL READLN And read a line from the default input port NOTE The...

Page 133: ...e count byte defines the number of characters in the buffer Enter a carriage return CR and line feed LF to terminate the input The characters echo to the default output port CR is not echoed Entry Conditions SP Address of input buffer long Exit Conditions SP Top of stack The count byte containing the number of bytes in the buffer EXAMPLE If A0 contains the string buffer address PEA A0 Push buffer ...

Page 134: ...estores control to CPU32Bug from the target program First any breakpoints inserted in target code are removed Then the target state is saved in the register image area Finally the routine returns to CPU32Bug Entry Conditions No arguments required Exit Conditions Control is returned to CPU32Bug EXAMPLE SYSCALL RETURN Return to CPU32Bug ...

Page 135: ...end Break SNDBRK 5 2 17 Send Break SYSCALL SNDBRK TRAP CODE 0029 Use SNDBRK to send a break to the default output port Entry Conditions No arguments or stack allocation required Exit Conditions The default port is sent break EXAMPLE SYSCALL SNDBRK ...

Page 136: ...ing 1 Address of string 2 Three bytes unused Byte to receive string comparison result Exit Conditions SP Three bytes unused Byte that received string comparison result EXAMPLE If A1 and A2 contain the addresses of the two strings SUBQ L 4 A7 Allocate longword to receive result PEA A1 Push address of one string PEA A2 Push address of the other string SYSCALL STRCMP Compare the strings MOVE L A7 D0 ...

Page 137: ...ot restart the timer use TM_STR0 to restart the timer Timing is accomplished by counting the number of interrupt pulses generated The default interrupt pulse frequency is 125 milliseconds Use this routine the first time the timer functions are used Entry Conditions No arguments required Exit Conditions Different From Entry Periodic interrupt timer is stopped no interrupts and initialized for futur...

Page 138: ...r of interrupt pulses generated Initialize TM_INI and start TM_STR0 the timer before using the TM_RD function Entry Conditions SP Space for result long Exit Conditions Different From Entry SP Time number of interrupt pulses long The timer keeps running after the read EXAMPLE SUBQ L 4 A7 Allocate space for result SYSCALL TM_RD Read timer MOVE L A7 D0 Load interrupt pulse count ...

Page 139: ...nual MC68332UM AD concerning the Periodic Interrupt Timer for more details Entry Conditions SP Timer control value for PICR word Timer period value for PITR word Exit Conditions Different From Entry Parameters are removed from the stack the timer is started and the interrupt pulse counter is cleared If the user s interrupt level as defined in the status register SR disables the timer interrupts th...

Page 140: ...er to zero and start it with the default control SYSCALL TM_STR0 value PICR and a period value PITR of 0002 244 usec interrupt MOVE L 054400A0 A7 Reset the timer to zero and start it with the control value SYSCALL TM_STR0 PICR of 0544 level 5 vector 68 44 and a period value PITR of 00A0 19 5 msec interrupt ...

Page 141: ...LN outputs a string of characters with data followed by a carriage return and line feed The user passes the starting address of the string and the data stack address containing the data which is inserted into the string The output goes to the default output port Entry Conditions Eight bytes of parameter positioned in the stack as follow SP Address of string long Data list pointer long A separate d...

Page 142: ...t format see 5 1 2 Format data fields within the string as follows radix fieldwidth Z where radix is the data s numerical base in hexadecimal i e A is base 10 10 is base 16 etc and fieldwidth is the number of data characters to output The data is right justified and left most characters are truncated to size Include Z to suppress leading zeros in the output All data is placed in the stack as longw...

Page 143: ...tput port After formatting the count byte is the first byte in the string The user passes the starting address of the string WRITELN appends a CR LF to the end of the string Entry Conditions Four bytes of parameters are positioned in the stack as follows SP Address of string long Exit Conditions SP Top of stack parameter bytes removed EXAMPLE MESSAGE1 DC B 9 MOTOROLA MESSAGE2 DC B 8 QUALITY PEA ME...

Page 144: ...ITELN WRITELN prints this message MOTOROLA QUALITY Using WRITELN instead of WRITE outputs this message MOTOROLA QUALITY NOTE The string must be formatted such that the first byte the byte pointed to by the passed address contains the byte count of the string pointer count format see 5 1 2 ...

Page 145: ...CPU32Bug prompt enter SD to switch to the diagnostics directory The Switch Directories SD command is described elsewhere in this chapter The prompt should now read CPU32Diag 6 2 2 Command Entry and Directories Enter commands at the CPU32Diag prompt The command name is entered before pressing the carriage return CR Multiple commands may be entered If a command expects parameters and another command...

Page 146: ...mechanism called self test Entering ST command causes the monitor to run only the tests included in that command Entering ST command runs all the tests included in an internal self test directory except the command listed ST without any parameters runs the entire directory which contains most of the diagnostics Each test for each particular command is listed in the paragraph pertaining to the comm...

Page 147: ...MT causes the monitor to run the MT self test but show only the names of the sub tests and the results pass fail 6 2 10 Display Error Counters DE Each test in the diagnostic monitor has a dedicated error counter As errors are encountered in a particular test its error counter is incremented If one were to run a self test or a series of tests the test results could be determined by examining the er...

Page 148: ... identified The write loop is very short in execution so measuring devices such as oscilloscopes may be utilized in tracking failures Pressing the BREAK key does not terminate this command but pressing the ABORT switch or RESET switch does Command size must be specified as B for byte W for word or L for longword The command requires two parameters target address and data to be written The address ...

Page 149: ...from which to read byte value CPU32Diag RL W A000 CR Read longword at A000 6 3 3 Write Read Loop WR SIZE ADDR DEL DATA The WR command executes a streamlined write and read of specified size to a specified memory location This command is intended as a debugging aid once specific fault areas are identified The write read loop is very short in execution so measuring devices such as oscilloscopes may ...

Page 150: ...f diagnostics used to test the CPU portion of the BCC MCU as listed below Table 6 1 Table 6 1 MCU CPU Diagnostic Tests Monitor Command Title CPU A Register Test CPU B Instruction Test CPU C Address Mode Test CPU D Exception Processing Test The normal procedure for correcting a CPU error is to replace the MCU micro controller unit ...

Page 151: ...ing line is printed A CPU Register test Running If any part of the test fails then the display appears as follows A CPU Register test Running FAILED error message Here error message is one of the following Failed DO D7 register check Failed SR register check Failed USP VBR CAAR register check Failed CACR register check Failed AO A4 register check Failed A5 A7 register check If all parts of the tes...

Page 152: ...struction Test Running If any part of the test fails then the display appears as follows B CPU Instruction Test Running FAILED error message Here error message is one of the following Failed AND OR NOT EOR instruction check Failed DBF instruction check Failed ADD or SUB instruction check Failed MULU or DIVU instruction check Failed BSET or BCLR instruction check Failed LSR instruction check Failed...

Page 153: ...en issued the following line is printed C CPU Address Mode test Running If any part of the test fails then the display appears as follows C CPU Address Mode test Running FAILED error message error message is one of the following Failed Absolute Addressing check Failed Indirect Addressing check Failed Post increment check Failed Pre decrement check Failed Indirect Addressing with Index check Unexpe...

Page 154: ... Exception Processing Test Running If any part of the test fails then the display appears as follows D CPU Exception Processing Test Running FAILED Test Failed Vector XXX XXX is the hexadecimal exception vector offset as explained in the CPU32 Reference Manual However if the failure involves taking an exception different from that being tested the display is D CPU Exception Processing Test Running...

Page 155: ...raphs Memory tests are listed in Table 6 2 NOTE If one or more memory tests are attempted at an address where there is no memory a bus error message appears giving the details of the problem Table 6 2 Memory Diagnostic Tests MONITOR COMMAND TITLE MT A Set Function Code MT B Set Start Address MT C Set Stop Address MT D Set Bus Data Width MT E March Address Test MT F Walk a Bit Test MT G Refresh Tes...

Page 156: ...0 X 00000100 00000000 5 00010004 X X FFFFEFFF FFFFFFEF Each line displayed consists of five items function code test address graphic bit report expected data and read data The test address expected data and read data are displayed in hexadecimal The graphic bit report shows a letter X at each errant bit position and a dash at each good bit position The heading used for the graphic bit report is in...

Page 157: ...MT A new value CR Function Code new value CPU32Diag If a new value was not specified by the user then the old value is displayed all and the user is allowed to enter a new value NOTE The default is Function Code 5 which is for on board RAM CPU32Diag MT A CR Function Code current value new value CR Function Code new value CPU32Diag This command may be used to display the current value without chang...

Page 158: ...ified by the user then the old value is displayed and the user is allowed to enter a new value NOTE The default is Start Addr 00003000 which is for on board RAM CPU32Diag MT B CR Start Addr current value new value CR Start Addr new value CPU32Diag This command may be used to display the current value without changing it by pressing a carriage return CR without entering the new value CPU32Diag MT B...

Page 159: ...s displayed and the user is allowed to enter a new value NOTE The default is Stop Addr 00010000 which is the end of on board RAM CPU32Diag MT C Stop Addr current value new value CR Stop Addr new value CPU32Diag This command may be used to display the current value without changing it by pressing a carriage return CR without entering the new value CPU32Diag MT C Start Addr current value CR Start Ad...

Page 160: ...as follows CPU32Diag MT D new value CR Bus Width 32 1 16 0 new value CPU32Diag If a new value was not specified by the user then the old value is displayed and the user is allowed to enter a new value NOTE The default value is Bus Width 32 1 16 0 1 CPU32Diag MT D CR Bus Width 32 1 16 0 current value new value CR Bus Width 32 1 16 0 new value CPU32Diag This command may be used to display the curren...

Page 161: ...hanged to all F s all the bits are set This process reveals address lines that are stuck high 3 Beginning at Start Address and proceeding upward to Stop Address each memory location is checked for bits that did not set and then the memory location is again cleared to 0 This process reveals address lines that are stuck low EXAMPLE After the command is entered the display should appear as follows E ...

Page 162: ...that the value written equals the one read Report any errors Shift the 32 bit value to move the bit up one position Repeat the procedure write read and verify for all 32 bit positions EXAMPLE After the command is entered the display should appear as follows F MT Walk a bit Test Running If an error is encountered then the memory location and other related information are displayed F MT Walk a bit T...

Page 163: ...e out the complement of FC84B730 037B48CF Verify that the location contains 037B48CF Proceed to next memory location 4 Delay for 500 milliseconds 5 For each memory location Verify that the location contains 037B48CF Write out value FC84B730 Verify that the location contains FC84B730 Proceed to next memory location EXAMPLE After the command is entered the display should appear as follows G MT Refre...

Page 164: ...ister Proceed to next memory location 3 Reload ECA86420 into the register 4 For each memory location Compare the contents of the memory to the register to verify that the contents are good one byte at a time Add 02468ACE to the contents of the register Proceed to next memory location EXAMPLE After the command is entered the display should appear as follows H MT Random Byte Test Running If an error...

Page 165: ...Finally the test performs a JSR to location Start Address 4 The program itself performs a wide variety of operations with the results frequently checked and a count of the errors maintained locations are reported in the same fashion as any memory test failure refer to paragraph 6 8 13 EXAMPLE After the command is entered the display should appear as follows I MT Program Test Running If the operato...

Page 166: ...ry location to 0 Test And Set the location should set upper bit only Verify that the location now contains 80 Proceed to next location next byte EXAMPLE After the command is entered the display should appear as follows J MT TAS Test Running If an error occurs then the memory location and other related information are displayed J MT TAS Test Running FAILED error related information If no errors occ...

Page 167: ...n issued the following line is printed BERR Bus Error Test Running If a bus error occurs in the first part of the test then the test fails and the display appears as follows BERR Bus Error Test Running FAILED Got Bus Error when reading from ROM If no bus error occurs in one of the other parts of the test then the test fails and the appropriate error message appears as one of the following No Bus E...

Page 168: ...DIAGNOSTIC FIRMWARE GUIDE M68CPU32BUG D REV 1 6 24 ...

Page 169: ...its and the second the low order 4 bits of the byte The five fields which comprise an S record are shown below TYPE RECORD LENGTH ADDRESS CODE DATA CHECKSUM Where the fields are composed as follows Field Printable Characters Contents type 2 S records type S0 S1 etc record length 2 The count of the character pairs in the record excluding type and record length address 4 6 or 8 The 2 3 or 4 byte add...

Page 170: ...records The address field is normally zeros S1 A record containing code data and the 2 byte address at which the code data is to reside S2 A record containing code data and the 3 byte address at which the code data is to reside S3 A record containing code data and the 4 byte address at which the code data is to reside S5 A record containing the number of S1 S2 and S3 records transmitted in a parti...

Page 171: ...30000FC The module consists of one S0 record four S1 records and an S9 record The S0 record is comprised of the following character pairs S0 S record type S0 indicating that it is a header record 06 Hexadecimal 06 decimal 6 indicating that six character pairs or ASCII bytes follow 00 00 Four character 2 byte address field zeros in this example 48 44 52 ASCII H D and R HDR 1B The checksum The first...

Page 172: ...13 19 character pairs and are ended with checksums 13 and 52 respectively The fourth S1 record contains 07 character pairs and has a checksum of 92 The S9 record is explained as follows S9 S record type S9 indicating that it is a termination record 03 Hexadecimal 03 indicating that three character pairs 3 bytes follow 00 00 The address field zeros FC The checksum of the S9 record Each printable ch...

Page 173: ...n may also be printed Table B 1 Self Test Error Messages Test Type and Error Message Failure Description CPU Register Test ERROR 01 000EXXXX CONFIDENCE TEST FAILED Dn test 1 ERROR 02 000EXXXX CONFIDENCE TEST FAILED Dn test 2 ERROR 03 000EXXXX CONFIDENCE TEST FAILED Dn test 3 ERROR 04 000EXXXX CONFIDENCE TEST FAILED SR ERROR 05 000EXXXX CONFIDENCE TEST FAILED VBR USP ERROR 06 000EXXXX CONFIDENCE TE...

Page 174: ...DESIZE ERROR 21 000EXXXX CONFIDENCE TEST FAILED Checksum error RAM Test ERROR 30 000EXXXX CONFIDENCE TEST FAILED RAM error CPU Addressing Test ERROR 40 000EXXXX CONFIDENCE TEST FAILED Absolute immediate ERROR 41 000EXXXX CONFIDENCE TEST FAILED Address indirect ERROR 42 000EXXXX CONFIDENCE TEST FAILED Postincrement pre decrement ERROR 43 000EXXXX CONFIDENCE TEST FAILED Address indirect with index ...

Page 175: ...ameter area is the first 512 bytes of CPU32Bug E0000 E01FF see Table C 1 For brevity s sake all entries have been shown as an offset value from the E0000 base address of CPU32Bug The source code equivalent of the customization area initialization table and chip select initialization module are available on the Motorola FREEWARE Bulletin Board Service BBS under the archive filename C32SRC ARC Futur...

Page 176: ... S record file of the changes on the host computer by entering the ALT F1 key on the host computer terminal for ProComm emulator program to open a log file Enter the file name C32B1 MX and then complete the CPU32Bug DU command by pressing CR The offset of DC000 is required to create the S records with the proper starting address of E0000 CPU32Bug DU 4000 41FF C32B1 MX DC000 ALT F1 CR CPU32Bug ALT ...

Page 177: ...fication is complete and the terminal emulator program is ready to receive the status message CR CR Verify passes CPU32Bug 7 Verify the main S record file C32B23 MX by entering the command shown below No offset is required CPU32Bug VE CR Enter the terminal emulator s escape key to return to the host computer s operating system ALT F4 for ProComm Then enter the host computer command to send the S r...

Page 178: ...the filename to C32B1C MX To speed up reprogramming a temporary file consisting of only the checksum word could be used by entering DU 400E 400F TMP MX DC000 ALT F1 CR after creating the C32B1C MX file STEP 4 Skip this step STEP 5 No change STEP 6 Change the filename to C32B1C MX STEP 7 This step is optional STEP 8 Only the checksum value needs to be programmed using the indicated value Since the ...

Page 179: ...003 5830 CSBAR0 CSOR0 CS0 base address register value and option register value 14 15 16 17 0003 3830 CSBAR1 CSOR1 CS1 base address register value and option register value 18 19 1A 1B 0103 6870 CSBAR2 CSOR2 CS2 base address register value and option register value 1C 1D 1E 1F 0103 3030 CSBAR3 CSOR3 CS3 base address register value and option register value 20 21 22 23 1004 5870 CSBAR4 CSOR4 CS4 ba...

Page 180: ...FFF8 680F CSBAR4 CSOR4 CS4 base address register value and option register value 54 55 56 57 FFE8 783F CSBAR5 CSOR5 CS5 base address register value and option register value 58 59 5A 5B 1004 38F0 CSBAR6 CSOR6 CS6 base address register value and option register value 5C 5D 5E 5F 1004 58F0 CSBAR7 CSOR7 CS7 base address register value and option register value 60 61 62 63 0103 6870 CSBAR8 CSOR8 CS8 b...

Page 181: ... watchdog is not serviced soon enough The failure is constant RESETing before the CPU32Bug prompt appears or RESETing during execution of particular commands Disabling the bus monitor timeout period causes CPU32Bug to lock up on any unterminated bus cycle i e accessing non existant memory Changing the bus monitor timeout period to too small of a value can cause problems with slow memory or if the ...

Page 182: ...ress Enabling is equivalent to changing the stack pointer SP and program counter PC and entering the GO command If any error was detected during self test PWR_TST the auto boot is disabled CONSOLE DEFAULT TABLE FOR SCI CONSCI 80 83 00001C0F PARMS Parameter definition for below Do not change this value 84 85 2580 BAUD Baud rate in decimal 19200 4B00 9600 2580 4800 12C0 2400 0960 1200 04B0 600 0258 ...

Page 183: ... bit 02 89 FF XON_ENB XON XOFF enable enable FF disable 00 8A 11 XON XON character 7 bit ASCII Q 11 8B 13 XOFF XOFF character 7 bit ASCII S 13 Periodic Interrupt Timer 8C 8D 0642 PICR Periodic interrupt control register value Default value is set for level 6 vect 66 8E 8F 0102 PITR Periodic interrupt timing register value Controls the tick time for the SYSCALL timing functions 4X Default value is ...

Page 184: ...070 PWR_TBL2 BRA L to Initialization Table 2 routine See INITTBL below Exit D7 L preserved A2 A7 60FF00000004 PWR_TTL BRA L to title printing routine Returns to PWR_TST no stack usage Exit D7 L preserved A8 AD 60FF0000D8AA PWR_TST BRA L to self test routine Exit D7 B error code D7 31 8 power up status flags Returns to PWR_GO no stack usage AE B3 60FF0000D4B4 PWR_GO BRA L to CPU32Bug start up routi...

Page 185: ...number of DATA elements of size s that are to be stored in successive addresses starting with ADDR s is the lower nibble and contains the size code for the DATA and the storage operation itself Valid size codes are as follows 1 BYTE data 2 WORD data 4 LONG WORD data An invalid size code terminates the routine FILL is a dummy placeholder filler that is only present for WORD and LONG WORD sized DATA...

Page 186: ... 0006 00FFFFA21 DC L FFFFA21 ADDR 000A 31 DC B 31 4 BYTE DATA 000B 04 22 47 FE DC B 04 22 47 FE Skips 1F 0010 00FFFFA22 DC L FFFFA22 ADDR 0014 02 DC B 2 1 WORD DATA Skips 15 0016 0544 DC W 0544 DATA 0018 00FFFFA74 DC L FFFFA74 ADDR 001C 04 DC B 4 1 LONG DATA Skips 1D 001E 12345678 DC L 12345678 DATA 0022 00FFFFA74 DC L FFFFA74 ADDR 0026 04 DC B 14 2 LONG DATA Skips 27 0028 12345678 DC L 12345678 2...

Page 187: ...wn in MASM assembly language format below except has been substituted for each space character to show exact spacing The Motorola copyright must be preserved SIGNON DC B SIGN 2 SIGN 1 Char count 8F SIGN 1 DC B 0D 0A 0A CR LF LF DC B CPU32Bug Debugger Diagnostics Version 1 00 45 chars DCB B 34 20 Pad to end of line 79 45 34 DC B 0D 0A CR LF DC B C Copyright 1991 by Motorola Inc DCB B 23 20 Reserve ...

Page 188: ...MCU SCI Table C 2 details the legal combinations that can be used when customizing CPU32Bug Table C 2 MCU SCI Communication Formats Character Width Parity Stop bit Description 7 None 1 Invalid port setting 7 None 2 7 Even 1 7 Even 2 7 Odd 1 7 Odd 2 8 None 1 8 None 2 8 Even 1 8 Even 2 Invalid port setting 8 Odd 1 8 Odd 2 Invalid port setting ...

Page 189: ...BCC U2 read write enable for LSB LOWER ODD RAM CS2 PFB U1 U3 read enable for MSB LSB BOTH RAMS CS3 PFB U1 write enable for LSB LOWER ODD RAM CS4 PFB U4 read enable for MSB UPPER EVEN RAM EPROM CS5 PFB U2 read enable for LSB LOWER ODD RAM EPROM CS6 PFB U5 chip enable for MC68881 882 CS7 unused CS8 PFB ABORT pushbutton autovector CS9 unused CS10 PFB U3 write enable for MSB UPPER EVEN cut jump U3 27 ...

Page 190: ...e enable for LSB LOWER ODD RAM CS2 BCC U2 U3 read enable for MSB LSB BOTH RAMS CS3 unused CS4 PFB ABORT pushbutton autovector CS5 PFB U5 chip enable for MC68881 882 cut jump U5 J3 from CS2 to CS5 required CS6 PFB U2 read enable for LSB LOWER ODD RAM EPROM CS7 PFB U4 read enable for MSB UPPER EVEN RAM EPROM CS8 PFB U1 U3 read enable for MSB LSB BOTH RAMS CS9 PFB U1 write enable for LSB LOWER ODD RA...

Page 191: ...EPROM for LSB LOWER ODD CS0 BCC U1 write enable for MSB UPPER EVEN RAM CS1 BCC U2 write enable for LSB LOWER ODD RAM CS2 BCC U3 U1 read enable for MSB LSB BOTH RAM CS3 unused CS4 PFB ABORT push button autovector CS5 PFB U5 chip enable for MC68881 882 cut jump U5 J3 from CS2 to CS5 required CS6 PFB U2 read enable for LSB LOWER ODD RAM EPROM CS7 PFB U4 read enable for MSB UPPER EVEN RAM EPROM CS8 PF...

Page 192: ...hing jumpers from Rev A to Rev B or C compatibility on a Rev C PFB all jumpers must be set to the same selection Table C 6 PFB Rev C Compatibility PFB Rev C BCC BOARD REVISION PFB Rev A PFB Rev B Jumper block not installed 1 Jumpers installed for Rev A Jumpers installed for Rev B BCC Rev A YES NO NO YES NO BCC Rev B NO YES YES NO YES BCC Rev C NO YES YES NO YES 1 The default when no jumper block i...

Page 193: ... The following example shows how Initialization Table 2 can be used to initialize the 2K Standby RAM Module on the MC68332 to appear at address 80000 in unrestricted space and assumes the register module base address is at 00FFF000 MM bit in MCR register equals one Remember Initialization Table 1 is invoked before the normal chip select initialization via PWR_INI while Initialization Table 2 is in...

Page 194: ... CPU32Bug monitors the MODCLK signal after reset to determine which parameter to use when calculating SCI baud rates Q Why do certain baud rates fail to work after I change the crystal frequency or use an external clock A There is an integral relationship between the system clock rate FSYSTEM and QSCI baud rates as per Section 5 6 3 1 SCI CONTROL REGISTER 0 SCCR0 in the MC68332 User s Manual MC683...

Page 195: ...R_AND parameter so the MM bit position bit 6 is zero The PWR_INI routine initializes the MCR register by first reading the register OR ing in theMCR_OR parameter value and then AND ing the result with theMCR_AND parameter value before storing the resulting value back into the MCR register Q How can I enable the Software Watchdog or change the Bus Monitor Timing when they are controlled by the writ...

Page 196: ...automatically execute my user program upon power up A Use the ROM Auto Boot Vectors RB_SP and RB_PC to implement a turn key system whereby CPU32Bug initializes itself and then loads the stack pointer SSP and program counter PC thus starting execution of the user s program ...

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