Theory of Operation
7-21
Receive Signalling Circuits
Refer to the following sections.
Figure 7-6 Receive Signalling Path.
Sub-audible Data (PL/DPL)
and High Speed Data Decoder
The ASFIC (U0201) is used to filter and limit all received data. The data enters
the ASFIC at U0201-J7. Inside U0201 the data is filtered according to data type
(HS or LS), then it is limited to a 0-5V digital level. The MDC and trunking high
speed data appear at U0201-G4, where it connects to the
µ
P U0101-11.
The low speed limited data output (PL, DPL, and trunking LS) appears at U0201-
A4, where it connects to the
µ
P U0101-10. While receiving low speed data, the
µ
P may output a sampling waveform depending on the sampling technique to
U0201-C3 between 1 and 2 kHz.
The low speed data is read by the
µ
P at twice the frequency of the sampling
waveform; a latch configuration in the ASFIC stores one bit every clock cycle.
The external capacitors C0226, C0225, and C0223 set the low frequency pole for
a zero crossings detector in the limiters for PL and HS data. The hysteresis of these
limiters is programmed based on the type of received data.
Note:
During HS data, the
µ
P may generate a sampling waveform
seen at U0201-G1.
Alert Tone Circuits
When the software determines that it needs to give the operator an audible
feedback (for a good key press, or for a bad key press), or radio status (trunked
system busy, phone call, circuit failures), it sends an alert tone to the speaker.
It does so by sending SPI BUS data to U0201 which sets up the audio path to the
speaker for alert tones. The alert tone itself can be generated in one of two ways:
internally by the ASFIC, or externally using the
µ
P and the ASFIC.
DET AUDIO
G4
A4
C5
J3
G1
C3
J7
11
10
6
5
LOW SPEED
PL
IN
RX LIM
PL
RX
LOW SPEED
HIGH SPEED
DATA FILTER
LIMITER
FILTER
LIMITER
ASFIC U0201
MICRO
U0101
DISCRIMINATOR AUDIO
FROM RF SECTION
(IFIC)
CLOCK
CLOCK
& DEEMPHASIS
CONTROLLER
LIM
CAP
LIM CAP
LIM
OUT
