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EVB555

MOTOROLA

Quick Reference

3-13

SECTION 3

Overview of the Evaluation Board

Figure 3-1 EVB555 Top

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Summary of Contents for EVB555

Page 1: ...MPC555 Evaluation Board Quick Reference ...

Page 2: ......

Page 3: ...r authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall i...

Page 4: ......

Page 5: ...face 16 BDM Interface 16 BDM Modes 16 BDM JTAG Support 16 Programming the Flash Modules 17 External Flash 17 Internal Flash of the MPC555 17 Interfaces for Testing and Debugging 18 Logic Analyzer Interface 18 Trace32 Lauterbach 18 ETK Connector 18 MAPI 400 100 Interface 18 Reset and Reset Configuration 19 Reset Button 19 Hard Reset Configuration 19 Configuration of the PLL 21 Working with the EVB5...

Page 6: ...O502 connector 40 Assignment of CO503 connector 41 Assignment of CO504 connector 42 Assignment of CO505 connector 43 Assignment of CO506 connector 44 Assignment of CO507 connector 45 Assignment of ETK Connectors 46 Connectors and their Counterparts 50 CO 100 Background Debug Mode Interface BDM 50 CO 101 RS232 Serial Interface 50 CO 103 JTAG Service 50 CO 104 105 Customized Communication Expansion ...

Page 7: ... system All special features of the MPC555 are supported The evaluation board is a development and test platform for software and hardware for the MPC555 It can be used by software and hardware developers to test programs tools or circuits with out having to develop a complete microcontroller system themselves The heart of the evaluation board is the MPC555 The processor can be operated in single ...

Page 8: ...MOTOROLA EVB555 1 10 Quick Reference ...

Page 9: ...tensive analysis and debug support Flexible BDM interface background debug mode for debugging Direct connection to the ETAS emulator test probe ETKP 1 Excellent analysis possibilities with 268 pin interface for logic analyzers 6 AMP Mictor and 2 berg type connector Connection of the probe to Lauterbach Trace32 emulation and programming system Very good expansion capability MAPI 400 interface Inter...

Page 10: ... TMR 14 1MGXSV GSRRIGXSV TMR 4 8 SRRIGXSV TMR 7EQXIG 830 7 5 0 Power Supply 7 36 V 3 3 V PRU Port Replacement Unit ETK Emulator Probe 5 V RS232 9 pin D Sub Connector Customized Communication Expansion 7 2 1 User Extension Board Connector 5x 100 pin Robinson Nugent P50L 100 S BS Bus Switch TMS28F033 PQFP 80 2x MCM69F737 TQFP 100 14 2x 20 pin Samtec TFM 110 12 S D LC 2x 60 pin Samtec TFM 130 12 S D ...

Page 11: ...EVB555 MOTOROLA Quick Reference 3 13 SECTION 3 Overview of the Evaluation Board Figure 3 1 EVB555 Top ...

Page 12: ...MOTOROLA EVB555 3 14 Quick Reference Figure 3 2 EVB555 Bottom ...

Page 13: ...s mode is shown by the Standby Power LED LD703 yellow 4 1 3 Power On The toggle switch Power On SW703 is used for activating the operating voltage of the EVB555 The activated state is shown by the additional LED Power On LD702 green All modules on the evaluation board are now supplied with power 4 2 Single Chip External Bus Mode The MPC555 can be operated as a single chip microcontroller or by usi...

Page 14: ... maximum external bus capability 4 3 2 BDM JTAG Support Due to the double use of the same pins on the MPC555 for the BDM and the JTAG interface only one of both interfaces can be used at the same time The operating mode is selected via the SW102 switch BDM Service The relevant configuration of the MPC555 is explained in the MPC555 User Manual BDM setting The BDM interface is available at the BDM c...

Page 15: ... the programming voltage control register cf Figure 5 2 Vpp12 is deactivated by entering a 0 in the register Control by the emulator test probe ETK The ETK can activate the programming voltage by applying a high level at the SGEPEE signal CO508 pin 137 This makes it possible for the ETK to pro gram the external flash 4 4 2 Internal Flash of the MPC555 Two prerequisites must be fulfilled for progra...

Page 16: ...n be controlled and adapted at program runtime This procedure is used for example in the calibration of engine ECUs in the automobile industry 4 5 4 MAPI 400 100 Interface The MAPI 400 100 interface makes it possible to expand the EVB555 with extensive and customer specific hardware For example there could be signal converters and output drivers connected to extend the EVB555 to a test sample of a...

Page 17: ...akes it possible to influence the behavior of the MPC555 from outside It particularly includes settings that are necessary before or during the start of the first program The reset configuration is read by the MPC555 after the supply voltage is switched on and after a hard reset has occurred Setting the hard reset configuration is conveniently solved on the EVB555 by assign ing the hard reset conf...

Page 18: ...13 1 1 10 11 DBPC Debug pin configuration 0 BDM 1 JTAG 0 12 ATWC Address type Write enable 0 WE 1 AT 0 13 14 EBDF External bus division factor 00 CLKOUT GCLK2 01 CLKOUT GCLK2 2 00 16 PRPM Peripheral mode enable 0 normal 1 external master 0 17 18 SC Single chip select 00 extended chip 32 bit data 01 extended chip 16 bit data 10 single chip show cycle address 11 single chip 00 19 ETRE Extended table...

Page 19: ...VB555 Table 4 2 PLL configuration Please consult the MPC555 User Manual for an explanation of the PLL function and limp mode The standard setting for the evaluation board should be 010 The PLL works using the quartz crystal assembled on the EVB555 4 MHz whereby the limp mode is enabled MODCK LME MF 1 Timing Reference 1 2 3 0 1 0 1 5 freq OSCM 4 MHz limb mode enabled 1 0 0 0 1 freqclkout max freq E...

Page 20: ...MOTOROLA EVB555 4 22 Quick Reference ...

Page 21: ...ces to the most important bus control signals of the MPC555 Figure 5 1 Using external resources on the EVB 555 MPC555 ETK Flash RAM Piggyback RAM EPLD SGCSR SGCSF SGWCS WE 0 3 OE SGEOF SGOE SGWCS SGCSF SGEOF SGCSM SGWE 0 3 A 8 15 A 28 31 CS1 OE PRU PDIR 0 7 D 0 7 POE A B PLE A B PRUOE PRUDIR RD_ WR TSIZ 0 1 Bus Switch A 8 31 D 0 31 D 0 31 A 8 31 OE VCC3 A_PIO 0 31 ExtBus CS0 WE_AT 0 3 SGHCE CS2 CS...

Page 22: ...e MPC555 should therefore be 4 Mbyte If the units intended for the higher addresses are not used this area can also be selected to be smaller e g only 2 Mbyte for RAM and PRU PRU Configuration 1 MB RAM at ETK Piggyback 1 MB external RAM 1 MB external Flash ETK SGCSR ETK SGCSF 0x 00 0000 0x 00 0004 Chip Select 0 Chip Select 1 1 MB Address Space Host Communication Extension HCE A8 A11 XX11 HCE SGHCE...

Page 23: ... an I O line defined as input is read from address PRU_DATA1 for A_PIO 0 31 or PRU_DATA2 for B_PIO 0 31 The EPLD drives the PRU to put the values of all 32 bits per group on the bus For setting output values data is written to address PRU_DATA1 or PRU_DATA2 and latched to the output ports If a PRU read operation follows the previously written val ues are read in again from the ports working as out...

Page 24: ... start up configuration It has to be configured before you can read from it Booting from the internal flash of the MPC555 is supported by the evaluation board Earlier versions of the MPC555 are not however capable of booting from the internal flash at an internal clock rate of 20 MHz The standard clock rate is 20 MHz which is generated by multiplying the crystal frequency 4 MHz with the mode clock...

Page 25: ...5 MOTOROLA Quick Reference A 27 APPENDIX A Connector Assignment The following tables display the connector assignment of the EVB555 evaluation board Only the connected pins are listed all other pins are open ...

Page 26: ...PWM0 43 C4 A_TPUCH7 See A_TPUCH0 44 E18 MPWM17 See MPWM0 45 A4 A_TPUCH8 See A_TPUCH0 47 C5 A_TPUCH9 See A_TPUCH0 48 F18 MPWM18 See MPWM0 49 B4 A_TPUCH10 See A_TPUCH0 50 E19 MPWM19 See MPWM0 51 B5 A_TPUCH11 See A_TPUCH0 53 A5 A_TPUCH12 See A_TPUCH0 54 A6 A_TPUCH15 See A_TPUCH0 55 C6 A_TPUCH13 See A_TPUCH0 56 C2 A_T2CLK to clock or gate the timer count register 2 TCR2 within the TPU 57 B6 A_TPUCH14 ...

Page 27: ...3 similar to IRQ5B no SGPIO 68 Y18 IRQ6B_mck2 Interrupt request mode clock 2 similar to IRQ5B no SGPIO 100 P17 VPP Flash supply voltage 5V used during program and erase operation of the CMF 28 41 46 71 74 89 92 GND Ground Pin MPC pin Signal name Description corresponding to data sheet ...

Page 28: ...struction queue flush status Load store watchpoint 3 35 U4 BDIPB Burst data in progress indicates that a data beat follows the current one 36 N3 BGB_LWP1 Bus grant indicates external data bus status Visible instruction queue flush status Load store watchpoint 37 V2 BIB_ STSB Burst inhibit 0 slave device is not able to support burst transfers Special transfer start beginning of an internal transact...

Page 29: ...O 75 H19 MPIO14 GPIO 76 H18 MPIO15 GPIO 88 A12 BAN0_PQB0 See AAN0_PQB0 90 B12 BAN1_PQB1 See AAN0_PQB0 92 A13 BAN2_PQB2 See AAN0_PQB0 94 A14 BAN3_PQB3 See AAN0_PQB0 96 B13 BAN48_PQB4 See AAN48_PQB4 98 C12 BAN49_PQB5 See AAN48_PQB4 100 D12 BAN50_PQB6 See AAN48_PQB4 17 18 43 46 63 64 83 84 GND Ground Pin MPC pin Signal name Description corresponding to the data sheet ...

Page 30: ... QSPI in master mode and serial data output from the QSPI in slave mode 42 F3 B_TPUCH8 See B_TPUCH0 44 G4 B_TPUCH9 See B_TPUCH0 45 L20 MOSI_QGP5 Master out slave in MOSI provides serial data output to the QSPI in master mode and serial data input from the QSPI in slave mode 46 E2 B_TPUCH10 See B_TPUCH0 47 L18 PCS0_QGP PCS0 provide QSPI peripheral chip select 0 SS places the QSPI in slave mode QSPI...

Page 31: ...he requested data transfer 87 J3 TRSTB Test reset asynchronous reset to the test logic 88 T3 TSIZ1 Transfer size indicates the size of the requested data transfer 89 V20 SRESETB Soft reset after negation of SRESET is detected a 16 cycle period is taken before testing an external reset An external pull up device is required to negate SRESET 90 U17 RSTCONF_TEXP Reset configuration input the reset co...

Page 32: ...2 7 W11 Data_SGP5 8 Y11 Data_SGP4 9 W12 Data_SGP7 10 Y12 Data_SGP6 11 W13 Data_SGP9 12 Y13 Data_SGP8 13 W14 Data_SGP11 14 Y14 Data_SGP10 17 W15 Data_SGP13 18 Y15 Data_SGP12 19 W16 Data_SGP15 20 Y16 Data_SGP14 21 W17 Data_SGP17 22 Y17 Data_SGP16 23 V16 Data_SGP19 24 V17 Data_SGP18 25 V15 Data_SGP21 26 U16 Data_SGP20 29 U14 Data_SGP23 30 V14 Data_SGP22 31 U13 Data_SGP25 32 V13 Data_SGP24 33 U12 Data...

Page 33: ...d in the current transaction 80 N1 WEB_AT 0 Write enable WE0 is asserted if the data lane DATA 0 7 contains valid data 81 R1 RD_ WRB Read write 1 read 0 write 82 P1 WEB_AT 1 Write enable WE1 is asserted if the data lane DATA 8 15 contains valid data 84 P2 WEB_AT 2 Write enable WE2 is asserted if the data lane DATA 16 23 contains valid data 85 P4 CS0B Chip select CS0 can be the global chip select f...

Page 34: ...responding to the data sheet 1 B_PIO0 B_PIO0 B_PIO31 second group of 32 General Purpose I O lines operated by the Port Replacement Unit 2 A_PIO0 A_PIO0 A_PIO31 first group of 32 General Purpose I O lines operated by the Port Replacement Unit 3 B_PIO1 See B_PIO0 4 A_PIO1 See A_PIO0 5 B_PIO2 See B_PIO0 6 A_PIO2 See A_PIO0 7 B_PIO3 See B_PIO0 8 A_PIO3 See A_PIO0 9 B_PIO4 See B_PIO0 10 A_PIO4 See A_PI...

Page 35: ...PIO25 See A_PIO0 59 B_PIO26 See B_PIO0 60 A_PIO26 See A_PIO0 61 B_PIO27 See B_PIO0 62 A_PIO27 See A_PIO0 63 B_PIO28 See B_PIO0 64 A_PIO28 See A_PIO0 65 B_PIO29 See B_PIO0 66 A_PIO29 See A_PIO0 67 B_PIO30 See B_PIO0 68 A_PIO30 See A_PIO0 69 B_PIO31 See B_PIO0 70 A_PIO31 See A_PIO0 71 B_PIO0 See B_PIO0 72 A_PIO0 See A_PIO0 85 EXTBUS disconnect external resources from processor bus 86 STANDBY switch ...

Page 36: ...6 ADDR A 25 Y8 Addr_SGP25 28 D5 ADDR A 26 W8 Addr_SGP26 30 D4 ADDR A 27 V8 Addr_SGP27 32 D3 ADDR A 28 U8 Addr_SGP28 34 D2 ADDR A 29 U9 Addr_SGP29 36 D1 ADDR A 30 U7 Addr_SGP30 38 D0 ADDR A 31 U6 Addr_SGP31 5 Clk STAT TS U3 TSB 7 D15 PORESET V19 PORESETB 9 D14 KAPWR Not to MPC555 direct to VSTBY3_3 11 D13 EXTCLK U18 EXTCLK 13 D12 Test point 500 15 D11 ADDR CS 0 P4 CS0B 17 D10 ADDR CS 1 R4 CS1B 19 D...

Page 37: ... D 26 V12 Data_SGP26 30 D4 DATA D 27 U12 Data_SGP27 32 D3 DATA D 28 V11 Data_SGP28 34 D2 DATA D 29 U11 Data_SGP29 36 D1 DATA D 30 V10 Data_SGP30 38 D0 DATA D 31 V9 Data_SGP31 5 Clk STAT STS V2 BIB_ STSB 7 D15 DATA D 0 Y9 Data_SGP0 9 D14 DATA D 1 W9 Data_SGP1 11 D13 DATA D 2 Y10 Data_SGP2 13 D12 DATA D 3 W10 Data_SGP3 15 D11 DATA D 4 Y11 Data_SGP4 17 D10 DATA D 5 W11 Data_SGP5 19 D9 DATA D 6 Y12 Da...

Page 38: ... T3 TSIZ1 28 D5 STAT VFLS 0 J18 VFLS0_MPIO3 30 D4 STAT VFLS 1 K18 VFLS1_MPIO4 32 D3 STAT FRZ_ PTR K3 FRZ_ PTR 34 D2 STAT RETRY L3 IRQ3B_SGP 36 D1 STAT SRESET V20 SRESETB 38 D0 STAT HRESET W20 HRESETB 5 Clk STAT RD_ WR R1 RD_ WRB 7 D15 CR M3 IRQ2B_SGP 9 D14 KR M2 IRQ1B_SGP 11 D13 RSTCONF U17 RSTCONF_TEXP 13 D12 IWP 0 L2 IWP0_VFLS 15 D11 IWP 1 L1 IWP1_VFLS 17 D10 IWP 2 N2 BRB_IWP2 19 D9 IWP 3 N4 BBB...

Page 39: ...XD 1 _QGPI 1 N17 RXD1_QGPI 26 D6 RXD 2 _QGPI 2 N19 RXD2_QGPI 28 D5 MDA 4 DA0 A17 MDA11 30 D4 MDA 5 DA1 A18 MDA12 32 D3 MDA 6 DA2 A19 MDA13 34 D2 MDA 7 DA3 B17 MDA14 36 D1 MDA 8 DA4 B18 MDA15 38 D0 n c 5 Clk ECK ECK 7 D15 MDA 9 DA5 C17 MDA27 9 D14 MDA 10 DA6 B20 MDA28 11 D13 MDA 11 DA7 C18 MDA29 13 D12 MDA 12 DA8 C19 MDA30 15 D11 MDA 13 DA9 C20 MDA31 17 D10 MPWM 14 PWM0 E17 MPWM0 19 D9 MPWM 15 PWM1...

Page 40: ...O 11 G19 MPIO11 32 D3 MGPIO 12 G20 MPIO12 34 D2 MGPIO 13 H20 MPIO13 36 D1 MGPIO 14 H19 MPIO14 38 D0 MGPIO 15 H18 MPIO15 5 Clk T2CLK TPU_A C2 A_T2CLK 7 D15 TPUCH 0 TPU_A D3 A_TPUCH0 9 D14 TPUCH 1 TPU_A A2 A_TPUCH1 11 D13 TPUCH 2 TPU_A D4 A_TPUCH2 13 D12 TPUCH 3 TPU_A C3 A_TPUCH3 15 D11 TPUCH 4 TPU_A A3 A_TPUCH4 17 D10 TPUCH 5 TPU_A D5 A_TPUCH5 19 D9 TPUCH 6 TPU_A B3 A_TPUCH6 21 D8 TPUCH 7 TPU_A C4 ...

Page 41: ...CH 8 TPU_B F3 B_TPUCH8 26 D6 TPUCH 9 TPU_B G4 B_TPUCH9 28 D5 TPUCH 10 TPU_B E2 B_TPUCH10 30 D4 TPUCH 11 TPU_B D1 B_TPUCH11 32 D3 TPUCH 12 TPU_B F4 B_TPUCH12 34 D2 TPUCH 13 TPU_B D2 B_TPUCH13 36 D1 TPUCH 14 TPU_B E3 B_TPUCH14 38 D0 TPUCH 15 TPU_B C1 B_TPUCH15 5 Clk n c 7 D15 CNTX0_A K19 A_CNTX0 9 D14 CNRX0_A K20 A_CNRX0 11 D13 CNTX0_B H4 B_CNTX0 13 D12 CNRX0_B H3 B_CNRX0 15 D11 EPEE P18 EPEE 17 D10...

Page 42: ...AAN3_PQB3 8 D11 AN 48 _PQB 4 QADC_A A9 AAN48_PQB4 9 D10 AN 49 _PQB 5 QADC_A B9 AAN49_PQB5 10 D9 AN 50 _PQB 6 QADC_A D9 AAN50_PQB6 11 D8 AN 51 _PQB 7 QADC_A C9 AAN51_PQB7 12 D7 AN 52 _MA 0 _PQA 0 QADC_A A10 AAN52_PQA0 13 D6 AN 53 _MA 1 _PQA 1 QADC_A B10 AAN53_PQA1 14 D5 AN 54 _MA 2 _PQA 2 QADC_A A11 AAN54_PQA2 15 D4 AN 55 _PQA 3 QADC_A D10 AAN55_PQA3 16 D3 AN 56 _PQA 4 QADC_A C10 AAN56_PQA4 17 D2 A...

Page 43: ... BAN3_PQB3 8 D11 AN 48 _PQB 4 QADC_B B13 BAN48_PQB4 9 D10 AN 49 _PQB 5 QADC_B C12 BAN49_PQB5 10 D9 AN 50 _PQB 6 QADC_B D12 BAN50_PQB6 11 D8 AN 51 _PQB 7 QADC_B A15 BAN51_PQB7 12 D7 AN 52 _MA 0 _PQA 0 QADC_B B14 BAN52_PQA0 13 D6 AN 53 _MA 1 _PQA 1 QADC_B C13 BAN53_PQA1 14 D5 AN 54 _MA 2 _PQA 2 QADC_B B15 BAN54_PQA2 15 D4 AN 55 _PQA 3 QADC_B D13 BAN55_PQA3 16 D3 AN 56 _PQA 4 QADC_B C14 BAN56_PQA4 17...

Page 44: ... 22 SGD9 SDATA 22 See SDATA 31 23 SGD10 SDATA 21 See SDATA 31 24 SGD11 SDATA 20 See SDATA 31 25 SGD12 SDATA 19 See SDATA 31 26 SGD13 SDATA 18 See SDATA 31 27 GND GND Ground 28 SGD14 SDATA 17 See SDATA 31 29 SGD15 SDATA 16 See SDATA 31 30 GND GND Ground 31 SGD16 SDATA 15 See SDATA 31 32 SGD17 SDATA 14 See SDATA 31 33 SGD18 SDATA 13 See SDATA 31 34 SGD19 SDATA 12 See SDATA 31 35 SGD20 SDATA 11 See S...

Page 45: ... 80 SGRW RD_ WR Read write 1 read 0 write 81 GND GND Ground 82 SGRW OE Output enable 83 SGWCS SGWCS Chip select SRAM 84 SGBE0 WE_AT 3 Write enable WE3 is asserted if the data lane DATA 24 31 contains valid data 85 SGOEF SGOEF To gate OE of flash flash emulation 86 GND GND Ground 87 GND GND Ground 88 SGBE1 WE_AT 2 Write enable WE2 is asserted if the data lane DATA 16 23 contains valid data 89 SGSIZ...

Page 46: ...IWP0_VFLS0 125 SGTCK TCK_DSCK Test clock development serial clock clock for the debug interface 126 SGTMS TMS Test mode select 127 SGIWP2 BR_VF1_IWP2 Bus request the data bus has been requested for external cycle Visible instruction queue flush status Load store watchpoint 2 128 SGIWP3 BB_VF2_IWP3 Bus busy master is using the bus Visible instruction queue flush status Load store watchpoint 3 129 S...

Page 47: ...511 145 SGPOE TP512 Test point 512 146 GND GND Ground 147 RESERVED TP513 Test point 513 148 RESERVED TP514 Test point 514 149 SGPDIR0 TP515 Test point 515 150 SGPDIR1 TP516 Test point 516 151 RESERVED TP517 Test point 517 152 RESERVED TP518 Test point 518 153 SGPDIR2 TP519 Test point 519 154 SGPDIR3 TP520 Test point 520 155 GND GND Ground 156 SGCLKO EXTCLK External frequency source for the chip 15...

Page 48: ... etc CO 103 EVB555 Counterpart Description Micro Strips FTS series 2 rows 20 pins Micro Strips 2 rows Manufacturer Samtec Samtec Order No FTS 110 01 F DV P FLE 110 01 G DV P Comment JTAG CO 104 105 EVB555 Counterpart Description Micro Strips 2 rows 20 pins Micro Strips 2 rows Manufacturer Samtec Samtec Order No TFM 110 12 S D P SFM 110 02 S D P Comment Piggyback CO 106 107 EVB555 Counterpart Descr...

Page 49: ...cturer of your emulator probe for further informa tion before connecting it to the EVB555 Manufacturer Samtec Order No MOLC 140 02 S Q TR Comment CO 509 EVB555 Counterpart Description Micro Strips 2 rows 64 pins Micro Strips 2 rows 64 pins Manufacturer Samtec Samtec Order No FTE 132 02 G DV P CLE 132 01 G DV P CO 600 603 EVB555 Counterpart Description P50L SMT series socket type 100 contacts P50L ...

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