Motorola EVB555, Quick Reference

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MOTOROLA EVB555
A-28 Quick Reference
A.1 MAPI-400+100 Interface
A.1.1 MAPI0 Interface Assignment
A.1.1.1 Assignment of J1/P1 (CO600) connector:
Pin MPC pin Signal name Description corresponding to data sheet
1 C9 AAN51_PQB7 See AAN48_PQB4
3 A10 AAN52_PQA0 Analog input: passed on as a separate signal to the QADC.
5 B10 AAN53_PQA1 See AAN52_PQA0
7 A11 AAN54_PQA2 See AAN52_PQA0
9 D10 AAN55_PQA3 See AAN52_PQA0
11 C10 AAN56_PQA4 See AAN52_PQA0
13 B11 AAN57_PQA5 See AAN52_PQA0
15 D11 AAN58_PQA6 See AAN52_PQA0
17 C11 AAN59_PQA7 See AAN52_PQA0
27 D3 A_TPUCH0 A_TPUCH0 - A_TPUCH15: Time Processor Unit A channel
29 A2 A_TPUCH1 See A_TPUCH0
30 E17 MPWM0 MPWM0 - MPWM3, MPWM16 - MPWM19: Pulse width modulation
31 D4 A_TPUCH2 See A_TPUCH0
32 D18 MPWM1 See MPWM0
33 C3 A_TPUCH3 See A_TPUCH0
35 A3 A_TPUCH4 See A_TPUCH0
36 D19 MPWM2 See MPWM0
37 D5 A_TPUCH5 See A_TPUCH0
38 D20 MPWM3 See MPWM0
39 B3 A_TPUCH6 See A_TPUCH0
42 F17 MPWM16 See MPWM0
43 C4 A_TPUCH7 See A_TPUCH0
44 E18 MPWM17 See MPWM0
45 A4 A_TPUCH8 See A_TPUCH0
47 C5 A_TPUCH9 See A_TPUCH0
48 F18 MPWM18 See MPWM0
49 B4 A_TPUCH10 See A_TPUCH0
50 E19 MPWM19 See MPWM0
51 B5 A_TPUCH11 See A_TPUCH0
53 A5 A_TPUCH12 See A_TPUCH0
54 A6 A_TPUCH15 See A_TPUCH0
55 C6 A_TPUCH13 See A_TPUCH0
56 C2 A_T2CLK to clock or gate the timer count register 2 (TCR2) within the TPU.
57 B6 A_TPUCH14 See A_TPUCH0
61 M2 /IRQ1B_SGP
Interrupt request, SGPIO, reservation:
to indicate that the internal core initiated a transfer.
62 M1 /IRQ0B_SGP Interrupt request, SGPIO
63 L3 /IRQ3B_SGP
Interrupt request, SGPIO, kill reservation,
retry: indicates to a master that the cycle is terminated
but should be repeated.
64 M3 /IRQ2B_SGP Interrupt request, SGPIO, cancel reservation: to clear its reservation.
65 W18 /IRQ5B_SGP
Interrupt request, SGPIO, mode clock [1]:
sampled at the negation of /PORESET in order to
configure the PLL/clock mode.
66 L4 /IRQ4B_SGP
Interrupt request, SGPIO, address type:
indicates one of the 16 ”address types”. The address type signals are
valid at the rising edge of the clock in which the special transfer start
(STS) is asserted.