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Memory Maps

Memory Configuration

3

-7

3.7

Memory Maps

The following figures describe each of the memory space and RAM configurations defined by
the settings of the SC, MS, and CE bits. The figures show the configuration and the table
describes the bit settings, memory sizes, and memory locations.

Figure 3-1. Default Settings (0, 0, 0)

Internal

Reserved

Bootstrap ROM

External

Internal

Program RAM

4 K

$FFFFFF

$FFF0C0

$FF0000

$001000

$000000

Internal

Reserved

Internal I/O

External

Internal

X data RAM

2 K

External

$000800

Internal

Reserved

External I/O

External

Internal

Y data RAM

2 K

External

$FF0000

$000000

$FFF000

$FFFF80

Program

X Data

Y Data

Default

Bit Settings

Memory Configuration

SC

MS

CE

Program RAM

X Data RAM

Y Data RAM

Cache

Addressable

Memory Size

0

0

0

4 K

$000–$FFF

2 K

$000–$7FF

2 K

$000–$7FF

None

16 M

$FFFFFF

$000800

$FF0000

$000000

$FFF000

$FFFF80

$FFFFFF

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Summary of Contents for DSP56303

Page 1: ...DSP56303 User s Manual 24 Bit Digital Signal Processor DSP56303UM AD Revision 1 January 2001 ...

Page 2: ...njury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associat...

Page 3: ...ctions Memory Configuration Programming the Peripherals Enhanced Synchronous Serial Interface ESSI Serial Communications Interface SCI Bootstrap Program Programming Reference 9 Triple Timer Module 4 Core Configuration 6 Host Interface HI08 ...

Page 4: ...ctions Memory Configuration Programming the Peripherals Enhanced Synchronous Serial Interface ESSI Serial Communications Interface SCI Bootstrap Program Programming Reference 9 Triple Timer Module 4 Core Configuration 6 Host Interface HI08 ...

Page 5: ... 1 7 1 5 4 PLL and Clock Oscillator 1 8 1 5 5 JTAG TAP and OnCE Module 1 9 1 5 6 On Chip Memory 1 9 1 5 7 Off Chip Memory Expansion 1 10 1 6 Internal Buses 1 10 1 7 DMA 1 11 1 8 Peripherals 1 12 1 8 1 GPIO Functionality 1 12 1 8 2 HI08 1 12 1 8 3 ESSI 1 13 1 8 4 SCI 1 13 1 8 5 Timer Module 1 14 Chapter 2 Signals Connections 2 1 Power 2 3 2 2 Ground 2 4 2 3 Clock 2 5 2 4 Phase Lock Loop PLL 2 5 2 5...

Page 6: ...es X Data Memory 3 3 3 2 3 Internal I O Space X Data Memory 3 4 3 3 Y Data Memory Space 3 4 3 3 1 Internal Y Data Memory 3 4 3 3 2 Memory Switch Modes Y Data Memory 3 4 3 3 3 External I O Space Y Data Memory 3 5 3 4 Dynamic Memory Configuration Switching 3 5 3 5 Sixteen Bit Compatibility Mode Configuration 3 6 3 6 RAM Configuration Summary 3 6 3 7 Memory Maps 3 7 Chapter 4 Core Configuration 4 1 O...

Page 7: ...1 Port B Signals and Registers 5 7 5 5 2 Port C Signals and Registers 5 8 5 5 3 Port D Signals and Registers 5 8 5 5 4 Port E Signals and Registers 5 9 5 5 5 Triple Timer Signals and Registers 5 9 Chapter 6 Host Interface HI08 6 1 Features 6 1 6 1 1 DSP Core Interface 6 1 6 1 2 Host Processor Interface 6 2 6 2 Host Port Signals 6 3 6 3 Overview 6 4 6 4 Operation 6 6 6 4 1 Software Polling 6 7 6 4 ...

Page 8: ...Data Signal SRD 7 3 7 2 3 Serial Clock SCK 7 3 7 2 4 Serial Control Signal SC0 7 4 7 2 5 Serial Control Signal SC1 7 4 7 2 6 Serial Control Signal SC2 7 6 7 3 Operation 7 6 7 3 1 ESSI After Reset 7 6 7 3 2 Initialization 7 6 7 3 3 Exceptions 7 7 7 4 Operating Modes Normal Network and On Demand 7 10 7 4 1 Normal Network On Demand Mode Selection 7 10 7 4 2 Synchronous Asynchronous Operating Modes 7 ...

Page 9: ...up 8 3 8 1 3 4 Address Mode Wakeup 8 3 8 2 I O Signals 8 3 8 2 1 Receive Data RXD 8 4 8 2 2 Transmit Data TXD 8 4 8 2 3 SCI Serial Clock SCLK 8 4 8 3 SCI After Reset 8 5 8 4 SCI Initialization 8 6 8 4 1 Preamble Break and Data Transmission Priority 8 7 8 4 2 Bootstrap Loading Through the SCI Boot Mode 2 or A 8 8 8 5 Exceptions 8 8 8 6 SCI Programming Model 8 9 8 6 1 SCI Control Register SCR 8 12 8...

Page 10: ...24 9 3 4 3 Reserved Modes 9 25 9 3 5 Special Cases 9 25 9 3 6 DMA Trigger 9 25 9 4 Triple Timer Module Programming Model 9 25 9 4 1 Prescaler Counter 9 25 9 4 2 Timer Prescaler Load Register TPLR 9 27 9 4 3 Timer Prescaler Count Register TPCR 9 28 9 4 4 Timer Control Status Register TCSR 9 28 9 4 5 Timer Load Register TLR 9 33 9 4 6 Timer Compare Register TCPR 9 34 9 4 7 Timer Count Register TCR 9...

Page 11: ...Contents xi Appendix B Programming Reference B 1 Internal I O Memory Map B 3 B 2 Interrupt Sources and Priorities B 8 B 3 Programming Sheets B 12 Index ...

Page 12: ...rs AAR 0 3 X FFFFF9 FFFFF6 4 30 4 9 DMA Control Register DCR 4 32 4 10 Identification Register Configuration Revision E 4 37 4 11 JTAG Identification Register Configuration Revision E 4 38 5 1 Memory Mapping of Peripherals Control Registers 5 2 5 2 Port B Signals 5 7 5 3 Port C Signals 5 8 5 4 Port D Signals 5 8 5 5 Port E Signals 5 9 5 6 Triple Timer Signals 5 9 6 1 HI08 Block Diagram 6 5 6 2 HI0...

Page 13: ...er B RSMB 7 35 7 18 Port Control Registers PCRC X FFFFBF PCRD X FFFAF 7 36 7 19 Port Direction Registers PRRC X FFFFBE PRRD X FFFFAE 7 37 7 20 Port Data Registers PDRC X FFFFBD PDRD X FFFFAD 7 38 8 1 SCI Data Word Formats SSFTD 1 1 8 10 8 2 SCI Data Word Formats SSFTD 0 2 8 11 8 3 SCI Control Register SCR 8 12 8 4 SCI Clock Control Register SCCR 8 19 8 5 SCI Baud Rate Generator 8 20 8 6 16 x Seria...

Page 14: ...ster DCR B 18 B 8 Address Attribute Registers AAR 3 0 B 19 B 9 DMA Control Registers 5 0 DCR 5 0 B 20 B 10 Host Transmit Data Register B 21 B 11 Host Base Address and Host Port Control Registers B 22 B 12 Host Control Register B 23 B 13 Interrupt Control and Command Vector Registers B 24 B 14 Interrupt Vector and Host Transmit Data Registers B 25 B 15 ESSI Control Register A CRA B 26 B 16 ESSI Con...

Page 15: ...it Definitions 4 10 4 3 Operating Mode Register OMR Bit Definitions 4 15 4 4 Interrupt Priority Level Bits 4 20 4 5 Interrupt Sources 4 20 4 6 Interrupt Source Priorities Within an IPL 4 22 4 7 PLL Control Register PCTL Bit Definitions 4 24 4 8 Bus Control Register BCR Bit Definitions 4 26 4 9 DRAM Control Register DCR Bit Definitions 4 28 4 10 Address Attribute Registers AAR 0 3 Bit Definitions 4...

Page 16: ...finitions 7 15 7 4 ESSI Control Register B CRB Bit Definitions 7 19 7 5 ESSI Status Register SSISR Bit Definitions 7 28 7 6 ESSI Port Signal Configurations 7 37 8 1 SCI Registers After Reset 8 5 8 2 SCI Control Register SCR Bit Definitions 8 12 8 3 SCI Status Register 8 17 8 4 SCI Status Register SSR Bit Definitions 8 17 8 5 SCI Clock Control Register SCCR Bit Definitions 8 19 9 1 Timer Prescaler ...

Page 17: ...ge at the address given on the back cover of this document 1 1 Manual Organization This manual contains the following sections and appendices Chapter 1 Overview Features list and block diagram related documentation organization of this manual and the notational conventions used Chapter 2 Signals Connections DSP56303 signals and their functional groupings Chapter 3 Memory Configuration DSP56303 mem...

Page 18: ...g the contents of the major DSP56303 registers for programmer s reference 1 2 Manual Conventions This manual uses the following conventions Bits within registers are always listed from most significant bit MSB to least significant bit LSB Bits within a register are indicated AA n m n m when more than one bit is involved in a description For purposes of description the bits are presented as if they...

Page 19: ...for the core interrupt priority register The word reset is used in four different contexts in this manual the reset signal written as RESET the reset instruction written as RESET the reset operating state written as Reset the reset function written as reset PIN True Asserted VCC PIN False Deasserted Ground Note 1 PIN is a generic term for any pin on the chip 2 Ground is an acceptable low voltage l...

Page 20: ... supports a wide variety of memory and peripheral configurations In particular the DSP56303 includes a JTAG port integrated with the Motorola OnCE module The DSP56303 is intended for use in telecommunication applications such as multi line voice data fax processing video conferencing audio applications control and general digital signal processing 1 4 DSP56300 Core Core features are fully describe...

Page 21: ...hip Emulation OnCE module Joint Test Action Group JTAG Test Access Port TAP Address Trace mode reflects internal Program RAM accesses at the external port Reduced power dissipation Very low power CMOS design Wait and stop low power standby modes Fully static design specified to operate down to 0 Hz dc Optimized power management circuitry instruction dependent peripheral dependent and mode dependen...

Page 22: ...rom data ALU registers The results of all data ALU operations are stored in an accumulator Data ALU operations are performed in two clock cycles in a pipeline so that a new instruction can be initiated in every clock cycle yielding an effective execution rate of one instruction per clock cycle The destination of every arithmetic operation can be a source operand for the immediately following opera...

Page 23: ... opposite directions Test logic determines which of the three summed results of the full adders is output Each address ALU can update one address register from its own address register file during one instruction cycle The contents of the associated modifier register specify the type of arithmetic used in the address register update calculation The modifier value is decoded in the address ALU 1 5 ...

Page 24: ...n blocks the PLL which performs clock input division frequency multiplication and skew elimination and the clock generator which performs low power division and clock pulse generation These features allow you to Change the low power divide factor without losing the lock Output a clock with skew elimination The PLL allows the processor to operate at a high internal clock frequency using a low frequ...

Page 25: ... chip peripherals This facilitates hardware and software development on the DSP56300 core processor OnCE module functions are provided through the JTAG TAP signals For details on the OnCE module consult the DSP56300 Family Manual 1 5 6 On Chip Memory The memory space of the DSP56300 core is partitioned into program X data and Y data memory space The data memory space is divided into X and Y data m...

Page 26: ...data exchange between the blocks the DSP56303 implements the following buses Peripheral I O expansion bus to peripherals Program memory expansion bus to program ROM X memory expansion bus to X memory Y memory expansion bus to Y memory Global data bus between PCU and other core structures Program data bus for carrying program data throughout the core X memory data bus for carrying X data throughout...

Page 27: ...erator Internal Data Bus Switch YAB XAB PAB YDB XDB PDB GDB MODB IRQB MODC IRQC External Data Bus Switch 13 MODD IRQD DSP56300 6 16 24 Bit 24 18 DDB DAB Peripheral Core YM_EB XM_EB PM_EB PIO_EB Expansion Area 6 SCI Interface JTAG 5 3 RESET MODA IRQA PINIT NMI 2 Bootstrap ROM EXTAL XTAL Address Control Data Triple Timer Host Interface HI08 ESSI Interface Address Generation Unit Six Channel DMA Unit...

Page 28: ...nality are detailed in Chapter 5 Programming the Peripherals 1 8 2 HI08 The HI08 is a byte wide full duplex double buffered parallel port that can connect directly to the data bus of a host processor The HI08 supports a variety of buses and provides connection with a number of industry standard DSPs microcomputers and microprocessors without requiring any additional logic The DSP core treats the H...

Page 29: ...essors or peripherals such as modems The SCI interfaces without additional logic to peripherals that use TTL level signals With a small amount of additional logic the SCI can connect to peripheral interfaces that have non TTL level signals such as the RS 232C RS 422 etc This interface uses three dedicated signals transmit data receive data and SCI serial clock It supports industry standard asynchr...

Page 30: ...on as a GPIO signal or as a timer signal Uses internal or external clocking and can interrupt the DSP after a specified number of events clocks or signal an external device after counting internal events Connection to the external world through one bidirectional signal When this signal is configured as an input the timer functions as an external event counter or measures external pulse width signa...

Page 31: ...2 6 Bus control 13 Table 2 8 on page 2 6 Interrupt and mode control 5 Table 2 9 on page 2 9 HI08 Port B2 16 Table 2 11 on page 2 11 ESSI Ports C and D3 12 Table 2 12 on page 2 15 Table 2 13 on page 2 17 SCI Port E4 3 Table 2 14 on page 2 19 Timer5 3 Table 2 15 on page 2 20 OnCE JTAG Port 6 Table 2 16 on page 2 21 NOTES 1 Port A signals define the external memory interface port including the extern...

Page 32: ... HACK HACK RXD TXD SCLK SC0 0 2 SCK0 SRD0 STD0 TIO0 TIO1 TIO2 8 3 4 2 EXTAL XTAL Clock Enhanced Synchronous Serial Interface Port 1 ESSI1 2 SC1 0 2 SCK1 SRD1 STD1 3 Multiplexed Bus HAD 0 7 HAS HAS HA8 HA9 HA10 Double DS HRD HRD HWR HWR Double HR HTRQ HTRQ HRRQ HRRQ Port B GPIO PB 0 7 PB8 PB9 PB10 PB13 PB11 PB12 PB14 PB15 Port E GPIO PE0 PE1 PE2 Port C GPIO PC 0 2 PC3 PC4 PC5 Port D GPIO PD 0 2 PD3...

Page 33: ...r chip power inputs except for VCCP The user must provide adequate external decoupling capacitors VCCC 2 Bus Control Power An isolated power for the bus control I O drivers This input must be tied externally to all other chip power inputs except for VCCP The user must provide adequate external decoupling capacitors VCCH Host Power An isolated power for the HI08 I O drivers This input must be tied ...

Page 34: ...drivers This connection must be tied externally to all other chip ground connections except GNDP and GNDP1 The user must provide adequate external decoupling capacitors GNDC 2 Bus Control Ground An isolated ground for the bus control I O drivers This connection must be tied externally to all other chip ground connections except GNDP and GNDP1 The user must provide adequate external decoupling capa...

Page 35: ...e Connect one capacitor terminal to PCAP and the other terminal to VCCP If the PLL is not used PCAP can be tied to VCC GND or left floating CLKOUT Output Chip driven Clock Output Provides an output clock synchronized to the internal core clock phase If the PLL is enabled and both the multiplication and division factors equal one then CLKOUT is also synchronized to EXTAL If the PLL is disabled the ...

Page 36: ...State During Reset Stop or Wait Signal Description D 0 23 Input Output Tri stated Data Bus When the DSP is the bus master D 0 23 provide the bidirectional data bus for external program and data memory accesses Otherwise D 0 23 are tri stated Table 2 8 External Bus Control Signals Signal Name Type State During Reset Stop or Wait Signal Description AA0 RAS0 AA3 RAS3 Output Tri stated Address Attribu...

Page 37: ... improper operation may result BR Output Output deasserted Bus Request Asserted when the DSP requests bus mastership and deasserted when the DSP no longer needs the bus BR can be asserted or deasserted independently of whether the DSP56303 is a bus master or a bus slave Bus parking allows BR to be deasserted even though the DSP56303 is the bus master see the description of bus parking in the BB si...

Page 38: ...igh and then released and held high by an external pull up resistor BB requires an external pull up resistor CAS Output Tri stated Column Address Strobe When the DSP is the bus master DRAM uses CAS to strobe the column address Otherwise if the Bus Mastership Enable BME bit in the DRAM Control Register is cleared the signal is tri stated BCLK Output Tri stated Bus Clock When the DSP is the bus mast...

Page 39: ...cts the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing MODA IRQA MODA MODB MODC and MODD select one of sixteen initial chip operating modes latched into the OMR when the RESET signal is deasserted Internally synchronized to CLKOUT If IRQA is asserted synchronous to CLKO...

Page 40: ...ted synchronous to CLKOUT multiple processors can be re synchronized using the WAIT instruction and asserting IRQC to exit the Wait state MODC IRQC can tolerate 5 V MODD IRQD Input Input Mode Select D External Interrupt Request D Selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal inst...

Page 41: ...utput Input Output Input or Output Disconnected internally Host Data When the HI08 is programmed to interface with a non multiplexed host bus and the HI function is selected these signals are lines 0 7 of the Data bus Host Address When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected these signals are lines 0 7 of the Address Data bus Port B 0 7 When ...

Page 42: ...e HI08 is programmed to interface with a multiplexed host bus and the HI function is selected this signal is line 9 of the Host Address bus Port B 10 When the HI08 is configured as GPIO through the HPCR this signal is individually programmed through the HDDR This input is 5 V tolerant HRW HRD HRD PB11 Input Input Input or Output Disconnected internally Host Read Write When the HI08 is programmed t...

Page 43: ...s 10 When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected this signal is line 10 of the Host Address bus Port B 13 When the HI08 is configured as GPIO through the HPCR this signal is individually programmed through the HDDR This input is 5 V tolerant HREQ HREQ HTRQ HTRQ PB14 Output Output Input or Output Disconnected internally Host Request When the ...

Page 44: ... When the HI08 is programmed to interface with a double host request host bus and the HI function is selected this signal is the Receive Host Request HRRQ output The polarity of the host request is programmable but is configured as active low HRRQ after reset The host request may be programmed as a driven or open drain output Port B 15 When the HI08 is configured as GPIO through the HPCR this sign...

Page 45: ...s SC00 or PC0 through the Port C Control Register PCRC This input is 5 V tolerant SC01 PC1 Input Output Input or Output Input Disconnected internally Serial Control 1 Functions in either Synchronous or Asynchronous mode For Asynchronous mode this signal is the receiver frame sync I O For Synchronous mode this signal is either Transmitter 2 output or Serial I O Flag 1 Port C 1 The default configura...

Page 46: ... PCRC This input is 5 V tolerant SRD0 PC4 Input Input or Output Input Disconnected internally Serial Receive Data Receives serial data and transfers the data to the ESSI receive shift register SRD0 is an input when data is being received Port C 4 The default configuration following reset is GPIO For PC4 signal direction is controlled through PRRC This signal is configured as SRD0 or PC4 through PC...

Page 47: ...lly Serial Control 1 Functions in either Synchronous or Asynchronous mode For Asynchronous mode this signal is the receiver frame sync I O For Synchronous mode this signal is either Transmitter 2 output or Serial I O Flag 1 Port D 1 The default configuration following reset is GPIO For PD1 signal direction is controlled through PRRD This signal is configured as SC11 or PD1 through PCRD This input ...

Page 48: ... PCRD This input is 5 V tolerant SRD1 PD4 Input Input or Output Input Disconnected internally Serial Receive Data Receives serial data and transfers the data to the ESSI receive shift register SRD0 is an input when data is being received Port D 4 The default configuration following reset is GPIO For PD4 signal direction is controlled through PRRD This signal is configured as SRD1 or PD4 through PC...

Page 49: ...PRRE This signal is configured as RXD or PE0 through the Port E Control Register PCRE This input is 5 V tolerant TXD PE1 Output Input or Output Input Disconnected internally Serial Transmit Data Transmits data from SCI transmit data register Port E 1 The default configuration following reset is GPIO When configured as PE1 signal direction is controlled through the SCI PRRE This signal is configure...

Page 50: ...r 0 Control Status Register TCSR0 This input is 5 V tolerant TIO1 Input or Output Input Disconnected internally Timer 1 Schmitt Trigger Input Output As an external event counter or in Measurement mode TIO1 is input In Watchdog Timer or Pulse Modulation mode TIO1 is output The default mode after reset is GPIO input This can be changed to output or configured as a Timer Input Output through the Time...

Page 51: ...or This input is 5 V tolerant TRST Input Input Test Reset Asynchronously initializes the test controller has an internal pull up resistor and must be asserted after power up This input is 5 V tolerant DE Input Output Input Debug Event Provides a way to enter Debug mode from an external command controller as input or to acknowledge that the chip has entered Debug mode as output When asserted as an ...

Page 52: ...JTAG OnCE Interface 2 22 DSP56303 User s Manual ...

Page 53: ...g Internal program RAM 4 K by default Instruction cache optional 1 K formed from program RAM When enabled the memory addresses used by the internal cache memory are switched to external memory The internal memory in this address range switches to cache only mode and is not available via direct addressing when cache is enabled In systems using Instruction Cache always enable the cache CE 1 before l...

Page 54: ...ch mode allows reallocation of portions of program RAM to X and Y data RAM OMR 7 is the memory switch MS bit that controls this function as follows When the MS bit is cleared program memory consists of the default 4 K 24 bit memory space described in the previous section In this default mode the lowest external program memory location is 1000 If the CE bit is set the program memory consists of the...

Page 55: ...accessed 3 2 1 Internal X Data Memory The default on chip X data RAM is a 24 bit wide internal static memory occupying the lowest 2 K locations 000 7FF in X memory space The on chip X data RAM is organized into 8 banks with 256 locations each Available X data memory space is increased by 1 K through reallocation of program memory using the memory switch mode described in the next section 3 2 2 Mem...

Page 56: ...ails on using the external memory interface to access external Y data memory Note The Y memory space at FF0000 FFEFFF is reserved and should not be accessed 3 3 1 Internal Y Data Memory The default on chip Y data RAM is a 24 bit wide internal static memory occupying the lowest 2 K 000 7FF of Y memory space The on chip Y data RAM is organized into 8 banks with 256 locations each Available Y data me...

Page 57: ... cache is enabled can cause conflicts To change the MS bit when CE is set 1 Clear CE 2 Change MS 3 Set CE Because an interrupt could cause the DSP to fetch instructions out of sequence and might violate the switch condition special care should be taken in relation to the interrupt vector routines CAUTION To ensure that dynamic switching is trouble free do not allow any accesses including instructi...

Page 58: ... all data and program code are 16 bits wide 3 6 RAM Configuration Summary The RAM configurations for the DSP56303 are listed in Table 3 1 The actual memory locations for Program RAM and the Instruction Cache in the Program memory space are determined by the MS and CE bits and their addresses are given in Table 3 2 Table 3 1 DSP56303 RAM Configurations Bit Settings Memory Sizes in K MS CE Program R...

Page 59: ...0 0 Internal Reserved Bootstrap ROM External Internal Program RAM 4 K FFFFFF FFF0C0 FF0000 001000 000000 Internal Reserved Internal I O External Internal X data RAM 2 K External 000800 Internal Reserved External I O External Internal Y data RAM 2 K External FF0000 000000 FFF000 FFFF80 Program X Data Y Data Default Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache A...

Page 60: ...External Internal X data RAM 2 K External 000800 Internal Reserved External I O External Internal Y data RAM 2 K External FFF000 FFFF80 Program X Data Y Data 000C00 Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 0 0 1 3 K 000 BFF 2 K 000 7FF 2 K 000 7FF 1 K internal not accessible 16 M FFFFFF FF0000 000000 000800 FFF000 FFFF80 FFFFFF FF00...

Page 61: ...xternal Internal X data RAM 3 K External 000C00 Internal Reserved External I O External Internal Y data RAM 3 K External FFF000 FFFF80 Program X Data Y Data Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 0 1 0 2 K 000 7FF 3 K 000 BFF 3 K 000 BFF None 16 M External FFFFFF FF0000 000000 000C00 FFF000 FFFF80 FFFFFF FF0000 000000 000800 ...

Page 62: ... I O External Internal X data RAM 3 K External 000C00 Internal Reserved External I O External Internal Y data RAM 3 K External FFF000 FFFF80 Program X Data Y Data 000400 Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 0 1 1 1 K 000 3FF 3 K 000 BFF 3 K 000 BFF 1 K internal not accessible 16 M Program FFFFFF FF0000 000000 000C00 FFF000 FFFF8...

Page 63: ...F 1000 0000 Internal I O Internal X data RAM 2 K External External I O Internal Y data RAM 2 K External Program X Data Y Data Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 1 0 0 4 K 000 FFF 2 K 000 7FF 2 K 000 7FF None 64 K FFFF 0000 FF80 0800 FFFF 0000 FF80 0800 ...

Page 64: ...00 Internal I O External Internal X data RAM 2 K External I O External Internal Y data RAM 2 K Program X Data Y Data 0C00 0800 Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 1 0 1 3 K 000 BFF 2 K 000 7FF 2 K 000 7FF 1 K internal not accessible 64 K FFFF 0000 FF80 0800 FFFF 0000 FF80 ...

Page 65: ...0 Internal I O Internal X data RAM 3 K External External I O Internal Y data RAM 3 K External FFFF 0000 Program X Data Y Data FF80 0C00 0800 Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 1 1 0 2 K 000 7FF 3 K 000 BFF 3 K 000 BFF None 64 K External FFFF 0000 FF80 0C00 ...

Page 66: ...nternal X data RAM 3 K External 0C00 External I O Internal Y data RAM 3 K External Program X Data Y Data 0400 Bit Settings Memory Configuration SC MS CE Program RAM X Data RAM Y Data RAM Cache Addressable Memory Size 1 1 1 1 K 000 3FF 3 K 000 BFF 3 K 000 BFF 1 K internal not accessible 64 K Internal RAM 1 K Program FFFF 0000 FF80 0C00 FFFF 0000 FF80 ...

Page 67: ... register OMR n Interrupt Priority Registers IPRC and IPRP n PLL control PCTL register n Bus Interface Unit registers Bus Control Register BCR DRAM Control Register DCR Address Attribute Registers AAR 3 0 n DMA Control Registers 5 0 DCR 5 0 n Device identification register IDR n JTAG identification register n JTAG boundary scan register BSR For information on specific registers or modules in the D...

Page 68: ...000 Expanded mode Bypasses the bootstrap ROM and the DSP56303 starts fetching instructions beginning at address C00000 Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected default Address C00000 is reflected as address 00000 on Port A signals A 0 17 1 0 0 0 1 FF0000 Bootstrap from byte wide memory The bootstrap program it loads a progra...

Page 69: ...ternal and the clock frequency must be 16x the baud rate After each byte is received it is echoed back through the SCI transmitter 3 0 0 1 1 FF0000 Reserved 4 0 1 0 0 FF0000 HI08 bootstrap in ISA DSP563xx mode The HI08 is configured to load the program RAM from the Host Interface programmed to operate in the ISA mode The HOST ISA bootstrap code expects to read a 24 bit word specifying the number o...

Page 70: ... with the Intel 8051 bus through the HI08 The HI08 pin configuration is optimized for connection to the Intel 8051 multiplexed bus in double strobe pin configuration The HOST 8051 bootstrap code expects accesses that are byte wide The HOST 8051 bootstrap code expects to read 3 bytes forming a 24 bit word specifying the number of program words 3 bytes forming a 24 bit word specifying the address to...

Page 71: ...d mode Bypasses the bootstrap ROM and the DSP56303 starts fetching instructions beginning at address 008000 Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected 9 1 0 0 1 FF0000 Bootstrap from byte wide memory The bootstrap program it loads a program RAM segment from consecutive byte wide P memory locations starting at P D00000 bits 7 0...

Page 72: ...external and the clock frequency must be 16x the baud rate After each byte is received it is echoed back through the SCI transmitter B 1 0 1 1 FF0000 Reserved C 1 1 0 0 FF0000 HI08 bootstrap in ISA DSP563xx mode The HI08 is configured to load the program RAM from the Host Interface programmed to operate in the ISA mode The HOST ISA bootstrap code expects to read a 24 bit word specifying the number...

Page 73: ...th the Intel 8051 bus through the HI08 The HI08 pin configuration is optimized for connection to the Intel 8051 multiplexed bus in double strobe pin configuration The HOST 8051 bootstrap code expects accesses that are byte wide The HOST 8051 bootstrap code expects to read 3 bytes forming a 24 bit word specifying the number of program words 3 bytes forming a 24 bit word specifying the address to st...

Page 74: ... the OMR Bootstrap modes 0 and 8 are the normal DSP56303 functioning modes The other bootstrap modes select different specific bootstrap loading source devices Refer to Appendix A for detailed information about the bootstrap program F 1 1 1 1 FF0000 HI08 bootstrap in MC68302 bus mode The bootstrap program loads the program RAM from the Host Interface programmed to operate in the MC68302 bus mode i...

Page 75: ...evious arithmetic computations The SR is pushed onto the system stack when program looping is initialized or a JSR is performed including long interrupts The SR consists of the following three special purpose 8 bit control registers n Extended Mode Register EMR SR 23 16 and Mode Register MR SR 15 8 These special purpose registers define the current system state of the processor The bits in both re...

Page 76: ... These bits are compared against the priority bits of the active DMA channel If the core priority is greater than the DMA priority the DMA waits for a free time slot on the external bus If the core priority is less than the DMA priority the core waits for a free time slot on the external bus If the core priority equals the DMA priority the core and DMA access the external bus in a round robin patt...

Page 77: ...it register portions Shifting limiting rounding arithmetic instructions and moves are performed accordingly For details on Sixteen Bit Arithmetic mode consult the DSP56300 Family Manual 16 FV 0 DO FOREVER Flag Set when a DO FOREVER loop executes The FV flag like the LF flag is restored from the stack when a DO FOREVER loop terminates Stacking and restoring the FV flag when initiating and exiting a...

Page 78: ... other Data ALU registers to be used and restored before the interrupt routine terminates 13 SC 0 Sixteen Bit Compatibility Mode Affects addressing functionality enabling full compatibility with object code written for the DSP56000 family When SC is set MOVE operations to from any of the following PCU registers clear the eight MSBs of the destination LA LC SP SSL SSH EP SZ VBA and SC If the source...

Page 79: ...ale down 24 S A47 XOR A46 OR B47 XOR B46 OR S previous 1 0 Scale up 22 S A45 XOR A44 OR B45 XOR B44 OR S previous 1 1 Reserved S undefined 9 8 I 1 0 11 Interrupt Mask Reflect the current Interrupt Priority Level IPL of the processor and indicate the IPL needed for an interrupt source to interrupt the processor The current IPL of the processor can be changed under software control The interrupt mas...

Page 80: ... 4 U 0 Unnormalized Set if the two MSBs of the Most Significant Portion MSP of the result are identical otherwise this bit is cleared The MSP portion of the A or B accumulators is defined by the Scaling mode S1 S0 Scaling Mode Integer Portion 0 0 No scaling U Bit 47 XOR Bit 46 0 1 Scale down U Bit 48 XOR Bit 47 1 0 Scale up U Bit 46 XOR Bit 45 1 1 Reserved U undefined 3 N 0 Negative Set if the MSB...

Page 81: ...22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PEN MSW 1 0 SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CDP 1 0 MS SD EBD MD MC MB MA Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 After reset these bits reflect the corresponding value of the mode input that is MODD MODC MODB or MODA respectively Reserved bit Read as zero write to zero for future compatibility Figure 4 2 Operating Mode Re...

Page 82: ...it enables Address Trace mode The Address Trace mode is a debugging tool that reflects internal memory accesses at the external bus address 14 APD 0 Address Attribute Priority Disable Disables the priority assigned to the Address Attribute signals AA 0 3 When APD 0 default setting the four Address Attribute signals each have a certain priority AA3 has the highest priority AA0 has the lowest priori...

Page 83: ...t during an instruction cache miss If the bit is cleared Burst mode is disabled and only one program word is fetched from the external memory when an instruction cache miss condition is detected If the bit is set Burst mode is enabled and up to four program words are fetched from the external memory when an instruction cache miss is detected 9 8 CDP 1 0 11 Core DMA Priority Specify the priority of...

Page 84: ...definitely until a defined event occurs to restart it If SD is cleared a 128K clock cycle delay is invoked before a STOP instruction cycle continues However if SD is set the delay before the instruction cycle continues is 16 clock cycles The long delay allows a clock stabilization period for the internal clock to begin oscillating and to stabilize When a stable external clock is used the shorter d...

Page 85: ...ster Core IPRC X FFFFFF IAL0 IAL1 IAL2 IBL0 IBL1 IBL2 ICL0 ICL1 ICL2 0 1 2 3 4 5 6 7 8 9 10 11 IRQA IPL IRQA mode IRQB IPL IRQB mode IRQC IPL IRQC mode IRQD IPL D0L0 D0L1 D1L0 D1L1 23 22 21 20 19 18 17 16 15 14 13 12 DMA0 IPL DMA1 IPL D2L0 D2L1 D3L0 D3L1 D4L0 D4L1 D5L0 D5L1 DMA2 IPL DMA3 IPL DMA4 IPL DMA5 IPL IDL2 IDL1 IDL0 IRQD mode HPL0 HPL1 S0L0 S0L1 S1L0 S1L1 23 22 21 20 19 18 17 16 15 14 13 1...

Page 86: ...hows the table entry address for each interrupt source The DSP56303 initialization program loads the table entry for each interrupt serviced with two interrupt servicing instructions In the DSP56303 only some of the 128 vector addresses are used for specific interrupt sources The remaining interrupt vectors are reserved and can be used for host NMI IPL 3 or for host command interrupt IPL 2 Unused ...

Page 87: ... ESSI0 receive data VBA 32 0 2 ESSI0 receive data with exception status VBA 34 0 2 ESSI0 receive last slot VBA 36 0 2 ESSI0 transmit data VBA 38 0 2 ESSI0 transmit data with exception status VBA 3A 0 2 ESSI0 transmit last slot VBA 3C 0 2 Reserved VBA 3E 0 2 Reserved VBA 40 0 2 ESSI1 receive data VBA 42 0 2 ESSI1 receive data with exception status VBA 44 0 2 ESSI1 receive last slot VBA 46 0 2 ESSI1...

Page 88: ... Register I 1 0 can be programmed to ignore low priority level interrupt requests VBA 50 0 2 SCI receive data VBA 52 0 2 SCI receive data with exception status VBA 54 0 2 SCI transmit data VBA 56 0 2 SCI idle line VBA 58 0 2 SCI timer VBA 5A 0 2 Reserved VBA 5C 0 2 Reserved VBA 5E 0 2 Reserved VBA 60 0 2 Host receive data full VBA 62 0 2 Host transmit data empty VBA 64 0 2 Host command default VBA...

Page 89: ...RX data interrupt ESSI0 receive last slot interrupt ESSI0 TX data with exception interrupt ESSI0 transmit last slot interrupt ESSI0 TX data interrupt ESSI1 RX data with exception interrupt ESSI1 RX data interrupt ESSI1 receive last slot interrupt ESSI1 TX data with exception interrupt ESSI1 transmit last slot interrupt ESSI1 TX data interrupt SCI receive data with exception interrupt SCI receive d...

Page 90: ...D 3 0 0 Predivider Factor Define the predivision factor PDF to be applied to the PLL input frequency The PD 3 0 bits are cleared during DSP56303 hardware reset which corresponds to a PDF of one 19 COD 0 Clock Output Disable Controls the output buffer of the clock at the CLKOUT pin When COD is set the CLKOUT output is pulled high When COD is cleared the CLKOUT pin provides a 50 percent duty cycle c...

Page 91: ...ace Unit BIU operation All BCR bits except bit 21 BBS are read write bits The BCR bits are defined in Table 4 8 Figure 4 6 Bus Control Register BCR 14 12 DF 2 0 0 Division Factor Define the DF of the low power divider These bits specify the DF as a power of two in the range from 20 to 27 11 0 MF 11 0 0 PLL Multiplication Factor Define the multiplication factor that is applied to the PLL input freq...

Page 92: ...cting eight or more wait states two additional wait states are inserted at the end of the access These trailing wait states increase the data hold time and the memory release time and do not increase the memory access time 15 13 BA3W 2 0 1 7 wait states Bus Area 3 Wait State Control Defines the number of wait states one through seven inserted in each external SRAM access to Area 3 DRAM accesses ar...

Page 93: ...he area defined by AAR1 NOTE Do not program the value of these bits as zero since SRAM memory access requires at least one wait state When four through seven wait states are selected one additional wait state is inserted at the end of the access When selecting eight or more wait states two additional wait states are inserted at the end of the access These trailing wait states increase the data hol...

Page 94: ...enerated and a refresh access is executed to all DRAM banks the exact timing of the refresh access depends on the pending external accesses and the status of the BME bit After the refresh access CAS before RAS is executed the DRAM controller hardware clears the BSTR bit The refresh cycle length depends on the BRW 1 0 bits a refresh access is as long as the out of page access 13 BREN 0 Bus Refresh ...

Page 95: ...us DRAM Page Size Defines the size of the external DRAM page and thus the number of the column address bits The internal page mechanism works according to these bits only if the page logic is enabled by the BPLE bit The four combinations of BPS 1 0 enable the use of many DRAM sizes 1 M bit 4 M bit 16 M bit and 64 M bit The encoding of BPS 1 0 is 00 9 bit column width 512 words 01 10 bit column wid...

Page 96: ...assert the corresponding AA RAS signal This is also true of 16 bit compatibility mode The BNC 3 0 bits define the number of address bits to compare 11 8 BNC 3 0 0 Bus Number of Address Bits to Compare Specify the number of bits from the BAC bits that are compared to the external address The BAC bits are always compared with the Most Significant Portion of the external address for example if BNC 3 ...

Page 97: ...g the packing access that is the three accesses are treated as one access with respect to arbitration and the bus mastership is not released during these accesses 6 0 Reserved Write to 0 for future compatibility 5 BYEN 0 Bus Y Data Memory Enable A read write control bit that enables disables the AA pin and logic during external Y data space accesses When set BYEN enables the comparison of the exte...

Page 98: ...access type that is BAT 10 To ensure proper operation of Port A this initialization must occur even for an AAR register that is not used during any Port A access Note that at reset the BAT bits are initialized to 00 Table 4 11 DMA Control Register DCR Bit Definitions Bit Number Bit Name Reset Value Description 23 DE 0 DMA Channel Enable Enables the channel operation Setting DE either triggers a si...

Page 99: ...nter with the original value 010 request Yes Line Transfer A line by line block transfer length set by the counter that is DE enabled The transfer is complete when the counter decrements to zero and the DMA controller reloads the counter with the original value 011 DE Yes Block Transfer The DE initiated transfer is complete when the counter decrements to zero and the DMA controller reloads the cou...

Page 100: ...ransfers and continues for its pending DMA transfers n If a lower priority channel is executing DMA transfers when a higher priority channel receives a transfer request the lower priority channel finishes the current word transfer and arbitration starts again n If some channels with the same priority are active in a round robin fashion and a new higher priority channel receives a transfer request ...

Page 101: ...he core has higher priority If another higher priority DMA channel requests access the halted channel finishes its previous access with a new higher priority before the new requesting DMA channel is serviced 16 DCON 0 DMA Continuous Mode Enable Enables disables DMA Continuous mode When DCON is set the channel enters the Continuous Transfer mode and cannot be interrupted during a transfer by any ot...

Page 102: ... empty HTDE 1 10101 11111 Reserved Peripheral requests 18 21 DRS 4 0 111xx can serve as fast request sources Unlike a regular peripheral request in which the peripheral can not generate a second request until the first one is served a fast peripheral has a full duplex handshake to the DMA enabling a maximum throughput of a trigger every two clock cycles This mode is functional only in the Word Tra...

Page 103: ...E In Cache mode a DMA to Program memory space has some limitations as described in Chapter 8 Instruction Cache and Chapter 11 Operating Modes and Memory Spaces DDS1 DDS0 DMA Destination Memory Space 0 0 X Memory Space 0 1 Y Memory Space 1 0 P Memory Space 1 1 Reserved 1 0 DSS 1 0 0 DMA Source Space Specify the memory space referenced as a source by the DMA NOTE In Cache mode a DMA to Program memor...

Page 104: ...and their associated control signals All DSP56303 bidirectional pins have a corresponding register bit in the BSR for pin data and are controlled by an associated control bit in the BSR For details on the BSR consult the DSP56300 Family Manual For the latest description of the BSR contents by available package type in boundary scan description language BSDL call your local Motorola Semiconductor S...

Page 105: ... initialization process However all four peripherals share some common steps which follow 1 Determine the Register values to be programmed using the following steps a Find the peripheral register descriptions in the manual b Choose the appropriate modes to configure for a given application c Determine the bit settings for programming those modes 2 Make sure the peripheral is in individual reset st...

Page 106: ...e B 2 5 3 Reading Status Registers Each peripheral has a read only status register that indicate the state of the peripheral at a given time The HI08 ESSI and SCI have dedicated status registers The triple timer has status bits embedded within a control status register Changes in the status bits can generate interrupt conditions For example the HI08 has a host status register with two host flag bi...

Page 107: ... with the peripheral Similar flags exist for each peripheral Example 5 1 shows software polling programmed in an application using the HI08 Example 5 1 Software Polling jclr 1 x M_HSR loop if HSR 1 HTDE 0 move y TBUFF_PTR x1 move data to x1 In this example the core waits until the Host Status Register HSR Host Transmit Data Empty HTDE flag is set When the flag is set the core moves data from Y mem...

Page 108: ... can be short only two opcodes long or long more than two opcodes and requiring a JSR instruction 2 Enabling the interrupts a Set the corresponding bits in the applicable peripheral control register b Enable peripheral interrupts in the Interrupt Priority Register IPRP c Enable global interrupts in the Mode Register MR portion of the Status Register SR Events that change bits in the peripheral con...

Page 109: ...eration does not interfere with the core operation or slow it down The DMA moves data to from the peripheral transmit receive registers The programmer can use the DMA control registers to configure sources and destinations of data transfers Depending on the peripheral one to four peripheral request sources are available This is the most efficient method of data transfer available Core intervention...

Page 110: ...res a large amount of DSP56303 core processing power The core cannot be involved in other processing activities while it is polling receive and transmit ready bits Interrupts require more code but the core can process other routines while waiting for data I O An interrupt is generated when data is ready to be transferred to or from the peripheral device DMA requires even less core intervention and...

Page 111: ...d with the triple timer signals 5 5 1 Port B Signals and Registers Each of the 16 Port B signals not used as an HI08 signal can be configured as a GPIO signal Three registers control the GPIO functionality of Port B host control register HCR host port GPIO data register HDR and host port GPIO direction register HDDR Chapter 6 Host Interface HI08 discusses these registers Figure 5 2 Port B Signals ...

Page 112: ... 3 Port C Signals 5 5 3 Port D Signals and Registers Each of the six Port D signals not used as an ESSI1 signal can be configured as a GPIO signal Three registers control the GPIO functionality of Port D Port D control register PCRD Port D direction register PRRD and Port D data register PDRD Chapter 7 Enhanced Synchronous Serial Interface ESSI discusses these registers Figure 5 4 Port D Signals D...

Page 113: ...al Communication Interface SCI discusses these registers 5 5 5 Triple Timer Signals and Registers Each of the three triple timer interface signals TIO 0 2 not used as a timer signal can be configured as a GPIO signal Each signal is controlled by the appropriate timer control status register TCSR 0 2 Chapter 9 Triple Timer Module discusses these registers Figure 5 5 Port E Signals Figure 5 6 Triple...

Page 114: ...General Purpose Input Output GPIO 5 10 DSP56303 User s Manual ...

Page 115: ... Thus the HI08 peripheral has a host processor interface and a DSP core interface This section lists the features of the host processor and DSP core interfaces 6 1 1 DSP Core Interface n Mapping Registers are directly mapped into eight internal X data memory locations n Data word DSP56303 24 bit native data words are supported as are 8 bit and 16 bit words n Handshaking protocols Software polled I...

Page 116: ...EQ or host transmit request HTRQ HACK HRRQ host acknowledge HACK or host receive request HRRQ Note The signals in the above list that are shown as asserted low for example HRD all have programmable polarity The default value following reset is shown in the above list n Mapping HI08 registers are mapped into eight consecutive locations in the host s external bus address space The HI08 acts as a mem...

Page 117: ...tachi H8 8051 family Thomson P6 family Minimal glue logic pull ups pull downs required to interface to ISA bus Motorola 68K family Intel X86 family 6 2 Host Port Signals The host port signals are discussed in Chapter 2 Signals Connections Each host port signal can be programmed as a host port signal or as a GPIO signal PB 0 15 See Table 6 1 through Table 6 3 Table 6 1 HI08 Signal Definitions for O...

Page 118: ...n page 6 16 and Section 6 6 4 Host Data Register HDR on page 6 16 6 3 Overview The HI08 is partitioned into two register banks as Figure 6 1 shows The host side register bank is accessible only to the host and the DSP side register bank is accessible only to the DSP core For the host the HI08 appears as eight byte wide locations mapped in its external address space The DSP side registers appear to...

Page 119: ... Data Bus RXH HCR Host Control Register HSR Host Status Register HPCR Host Port Control Register HBAR Host Base Address Register HTX Host Transmit Register HRX Host Receive Register HDDR Host Data Direction Register HDR Host Data Register ICR Interface Control Register CVR Command Vector Register IVR Interrupt Vector Register RXH Receive Register High RXM Receive Register Middle RXL Receive Regist...

Page 120: ...ata to these registers The transfer to the DSP side Host Receive Data Register HRX occurs only if HRX is empty that is the DSP has read it The DSP core then uses an appropriate handshaking protocol to move data from the HRX to the receiving buffer or register Without handshaking the host might overwrite data not transferred to the DSP side or the DSP might receive stale data Similarly when the hos...

Page 121: ...rmine the state of the Transmit Registers TXH TXM TXL and Receive Registers RXH RHM RHL Two bits are provided to the host for polling n the Transmit Data Empty TXDE bit in the Interface Status Register ISR 1 TXDE n the Receive Data Full RXDF bit in the Interface Status Register ISR 0 RXDF The HI08 also offers four general purpose flags for communication between the host and the DSP The DSP side us...

Page 122: ... enables a DMA transfer The DSP56303 processor has reserved interrupt vector addresses for application specific service routines However this flexibility is independent of the data transfer mechanisms in the HI08 and allows the host to force execution of any interrupt handler for example SSI SCI IRQx and so on To enable Host Command interrupts the HCR 2 HCIE bit is set on the DSP side The host the...

Page 123: ...t access the host bus The host must determine when data is available in the host side data registers using an appropriate polling mechanism 6 4 4 Host Requests A set of signal lines allow the HI08 to request service from the host The request signal lines normally connect to the host interrupt request pins IRQx and indicate to the host when the DSP HI08 port requires service The HI08 can be configu...

Page 124: ...uest Structure Table 6 5 HREQ Pin Operation In Single Request Mode ICR 2 HDRQ 0 ICR 1 TREQ ICR 0 RREQ HREQ Pin 0 0 No interrupts 0 1 RXDF request enabled 1 0 TXDE request enabled 1 1 RXDF and TXDE request enabled Table 6 6 HTRQ and HRRQ Pin Operation In Double Request Mode ICR 2 HDRQ 1 ICR 1 TREQ ICR 0 RREQ HTRQ Pin HRRQ Pin 0 0 No interrupts No interrupts 0 1 No interrupts RXDF request enabled 1 ...

Page 125: ...nsfer all bytes in a single operation instruction For example in the PowerPC MPC860 processor the General Purpose Controller Module GPCM in the memory controller can be programmed so that the host can execute a single read load word LDW or write store word STW instruction to the HI08 port and cause four byte transfers to occur on the host bus The 32 bit datum transfer shown in Figure 6 4 has byte ...

Page 126: ...bootstrap the application code to the DSP Table 6 7 describes these modes The bootstrap program is factory programmed into an internal 192 word by 24 bit bootstrap ROM at locations FF0000 FF00BF of P memory This program can load program RAM segment from the HI08 host port When any of the modes in the preceding table are used the core begins executing the bootstrap program and configures the HI08 b...

Page 127: ...o transfer data efficiently at high speed Direct memory mapping allows the DSP56303 core to communicate with the HI08 registers using standard instructions and addressing modes In addition the MOVEP instruction allows direct data transfers between DSP56303 internal memory and the HI08 registers or vice versa There are two types of host processor registers data and control with eight registers in a...

Page 128: ...ded pairs in a simple DSP to host communication protocol implemented in both the DSP and the host processor software The bit value is indeterminate after an individual reset 2 HCIE 0 Host Command Interrupt Enable Generates a host command interrupt request if the host command pending HCP status bit in the HSR is set If HCIE is cleared HCP interrupts are disabled The interrupt address is determined ...

Page 129: ...itions Bit Number Bit Name Reset Value Description 15 5 0 Reserved Write to 0 for future compatibility 4 3 HF 1 0 0 Host Flags 0 1 General purpose flags for host to DSP communication These bits reflect the status of host flags HF 1 0 in the ICR on the host side These two general purpose flags can be used individually or as encoded pairs in a simple host to DSP communication protocol implemented in...

Page 130: ...ates that the host receive data register HRX contains data from the host processor HRDF is set when data is transferred from the TXH TXM TXL registers to the HRX register The host processor can also clear HRDF using the initialize function 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DR15 DR14 DR13 DR12 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 Figure 6 8 Host Data Direction Register HDDR X FFFFC...

Page 131: ...t logic uses HBAR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 Reserved bit read as 0 write to 0 for future compatibility Figure 6 10 Host Base Address Register HBAR X FFFFC5 Table 6 11 Host Base Address Register HBAR Bit Definitions Bit Number Bit Name Reset Value Description 15 8 0 Reserved Write to 0 for future compatibility 7 0 BA 10 3 80 Base Address Reflect the base...

Page 132: ...ignal is configured as an active low input The HI08 drives the contents of the IVR onto the host bus when the HACK signal is low If the HAP bit is set the HACK signal is configured as an active high input The HI08 outputs the contents of the IVR when the HACK signal is high 14 HRP 0 Host Request Polarity Controls the polarity of the host request signals In single host request mode that is when HDR...

Page 133: ...SP 0 Host Data Strobe Polarity If HDSP is cleared the data strobe signals are configured as active low inputs and data is transferred when the data strobe is low If HDSP is set the data strobe signals are configured as active high inputs and data is transferred when the data strobe is high The data strobe signals are either HDS by itself or both HRD and HWR together 8 HROD 0 Host Request Open Drai...

Page 134: ... host chip select HCS in the non multiplexed bus mode that is when HMUX is cleared and host address line 10 HA10 in the multiplexed bus mode that is when HMUX is set If this bit is cleared HCS HA10 is configured as a GPIO signal according to the value of the HDDR and HDR 2 HA9EN 0 Host Address Line 9 Enable If HA9EN is set and the HI08 is in multiplexed bus mode then HA9 HA2 is host address line 9...

Page 135: ...nterrupt when HSR HTDE is set To prevent the previous data from being overwritten the DSP56303 should never write to the HTX when HSR HTDE is cleared Note When data is written to a peripheral device there is a two cycle pipeline delay until any status bits affected by this operation are updated If you read any of the status bits within the next two cycles the bit does not reflect its current statu...

Page 136: ...is cleared Note The DSP56303 should never try to read the HRX register if the HSR HRDF bit is already cleared 6 6 9 DSP Side Registers After Reset Table 6 13 shows the results of the four reset types on the bits in each of the HI08 registers accessible to the DSP56303 The hardware reset HW is caused by the RESET signal The software reset SW is caused by execution of the RESET instruction The indiv...

Page 137: ... the HI08 places the data on the bus 3 Strobes the data transfer Host processors can use standard host processor instructions for example byte move and addressing modes to communicate with the HI08 registers The HI08 registers are aligned so that 8 bit host processors can use 8 16 or 24 bit load and store instructions for data transfers The HREQ HTRQ and HACK HRRQ handshake flags are provided for ...

Page 138: ...CR The ICR is an 8 bit read write control register by which the host processor controls the HI08 interrupts and flags The DSP core cannot access the ICR The ICR is a read write register which allows the use of bit manipulation instructions on control register bits Hardware and software reset clear the ICR bits Table 6 14 Host Side Register Map Host Address Big Endian HLEND 0 Little Endian HLEND 1 ...

Page 139: ... to DSP 1 1 INIT 0 RXDF 0 HTDE 1 TXDE 1 HRDF 0 Host to from DSP 6 0 Reserved Write to 0 for future compatibility 5 HLEND 0 Host Little Endian If the HLEND bit is cleared the host can access the HI08 in Big Endian byte order If set the host can access the HI08 in Little Endian byte order If the HLEND bit is cleared the RXH TXH register is located at address 5 the RXM TXM register at 6 and the RXL T...

Page 140: ...RREQ HREQ Signal 0 0 No interrupts polling 0 1 RXDF request interrupt 1 0 TXDE request interrupt 1 1 RXDF and TXDE request interrupts TREQ and RREQ modes HDRQ 1 TREQ RREQ HTRQ Signal HRRQ Signal 0 0 No interrupts polling No interrupts polling 0 1 No interrupts polling RXDF request interrupt 1 0 TXDE request interrupt No interrupts polling 1 1 TXDE request interrupt RXDF request interrupt 0 RREQ 0 ...

Page 141: ...g the HC bit causes host command pending HCP to be set in the HSR The host can write to the HC and HV bits in the same write cycle 6 0 HV 6 0 32 Host Vector Select the host command interrupt address for use by the host command interrupt logic When the DSP interrupt control logic recognizes the host command interrupt the address of the interrupt routine taken is 2 HV The host can write HC and HV in...

Page 142: ...Q HREQ Effect 0 0 HREQ is cleared no host processor interrupts are requested 0 1 HREQ is set an interrupt is requested 1 0 HTRQ and HRRQ are cleared no host processor interrupts are requested 1 1 HTRQ or HRRQ are set an interrupt is requested 6 5 0 Reserved Write to 0 for future compatibility 4 HF3 0 Host Flag 3 Indicates the state of HF3 in the HCR on the DSP side HF3 can be changed only by the D...

Page 143: ...lize function TXDE can assert the external HTRQ signal if the TREQ bit is set Regardless of whether the TXDE interrupt is enabled TXDE indicates whether the TX registers are full and data can be latched in so that polling techniques may be used by the host processor Hardware software individual and stop resets all set TXDE 0 RXDF 0 Receive Data Register Full Indicates that the receive byte registe...

Page 144: ...d When the host reads the receive byte register at host address 7 the ISR RXDF bit is cleared Note The external host should never read the RXH RXM RXL registers if the ISR RXDF bit is cleared 6 7 6 Transmit Data Registers TXH TXM TXL The host processor views the transmit byte registers as three 8 bit write only registers These registers are the transmit high register TXH the transmit middle regist...

Page 145: ... on bits in each of the HI08 registers seen by the host processor To cause a hardware reset assert the RESET signal To cause a software reset execute the RESET instruction To reset the HEN bit individually clear the HPCR HEN bit To cause a stop reset execute the STOP instruction Table 6 18 Host Side Registers After Reset Register Name Register Data Reset Type HW Reset SW Reset Individual Reset STO...

Page 146: ...rrupt disabled HCP interrupt enabled 0 3 HF2 Host Flag 2 0 4 HF3 Host Flag 3 0 HPCR 0 HGEN Host GPIO Enable 0 1 GPIO signal disconnected GPIO signals active 0 1 HA8EN Host Address Line 8 Enable 0 1 HA8 A1 GPIO HA8 A1 HA8 0 2 HA9EN Host Address Line 9 Enable 0 1 HA9 A2 GPIO HA9 A2 HA9 0 3 HCSEN Host Chip Select Enable 0 1 HCS A10 GPIO HCS A10 HCS 0 4 HREN Host Request Enable 0 1 HDRQ 0 HDRQ 1 HREQ ...

Page 147: ...tive low HREQ HTRQ HRRQ active high 0 15 HAP HostAcknowledge Polarity 0 1 HACK active low HACK active high 0 HSR 0 HRDF Host Receive Data Full 0 1 no receive data to be read Receive Data Register is full 0 0 0 1 HTDE Host Transmit Data Empty 1 0 The Transmit Data Register is empty The Transmit Data Register is not empty 1 1 1 2 HCP Host Command Pending 0 1 no host command pending host command pend...

Page 148: ... 1 Reset data paths according to TREQ and RREQ 0 ISR 0 RXDF Receive Data Register Full 0 1 Host Receive Register is empty Host Receive Register is full 0 0 0 1 TXDE Transmit Data Register Empty 1 0 Host Transmit Register is empty Host Transmit Register is full 1 1 1 2 TRDY Transmitter Ready 1 0 transmit FIFO 6 deep is empty transmit FIFO is not empty 1 1 1 3 HF2 Host Flag 2 0 4 HF3 Host Flag 3 0 7...

Page 149: ...ver sections and a common ESSI clock generator There are two independent and identical ESSIs in the DSP56303 ESSI0 and ESSI1 For simplicity a single generic ESSI is described here The ESSI block diagram is shown in Figure 7 1 This interface is synchronous because all serial transfers are synchronized to one clock Figure 7 1 ESSI Block Diagram RSMA RSMB TSMA TSMB SSISR RX RX SHIFT REG TX0 SHIFT REG...

Page 150: ... mode is for nonperiodic transfers of data This mode which offers a subset of the Motorola Serial Peripheral Interface SPI protocol can transfer data serially at high speed when the data become available Since each ESSI unit can be configured with one receiver and three transmitters the two units can be used together for surround sound applications which need two digital input channels and six dig...

Page 151: ...n use 7 2 2 Serial Receive Data Signal SRD SRD receives serial data and transfers the data to the receive shift register SRD can be programmed as a GPIO signal P4 when the SRD function is not in use 7 2 3 Serial Clock SCK SCK is a bidirectional signal providing the serial bit rate clock for the ESSI interface The signal is a clock input or output used by all the enabled transmitters and receivers ...

Page 152: ...Flag 0 SC0 controls the state of the serial Input Flag 0 IF0 bit in the ESSI Status Register SSISR When SC0 is configured as a transmit data signal it is always an output signal regardless of the SCD0 bit value SC0 is fully synchronized with the other transmit data signals STD and SC1 SC0 can be programmed as a GPIO signal P0 when the ESSI SC0 function is not in use Note The ESSI can operate with ...

Page 153: ...als SYN TE0 TE1 TE2 RE SC0 SC1 SC2 SCK STD SRD 0 0 X X 0 U U U U U U 0 0 X X 1 RXC FSR U U U RD 0 1 X X 0 U U FST TXC TD0 U 0 1 X X 1 RXC FSR FST TXC TD0 RD 1 0 0 0 0 U U U U U U 1 0 0 0 1 F0 U F1 T0D U FS XC U RD 1 0 0 1 0 F0 U TD2 FS XC U U 1 0 0 1 1 F0 U TD2 FS XC U RD 1 0 1 0 0 TD1 F1 T0D U FS XC U U 1 0 1 0 1 TD1 F1 T0D U FS XC U RD 1 0 1 1 0 TD1 TD2 FS XC U U 1 0 1 1 1 TD1 TD2 FS XC U RD 1 1...

Page 154: ...I signals are programmed as GPIO it is active only if at least one of the ESSI I O signals is programmed as an ESSI signal 7 3 2 Initialization To initialize the ESSI do the following 1 Send a reset hardware RESET signal software RESET instruction ESSI individual reset or STOP instruction reset 2 Program the ESSI control and time slot registers 3 Write data to all the enabled transmitters 4 Config...

Page 155: ...rnally generated clock and frame sync these signals start activity immediately after the ESSI is enabled 2 The ESSI receives data after a frame sync signal either internally or externally gener ated only when the receive enable RE bit is set 3 Data is transmitted after a frame sync signal either internally or externally generated only when the transmitter enable TE 2 0 bit is set 7 3 3 Exceptions ...

Page 156: ...ed when you first read the SSISR and then write to all the transmit data registers of the enabled transmitters or when you write to TSR to clear the pending interrupt n ESSI transmit last slot interrupt Occurs when the ESSI is in Network mode at the start of the last slot of the frame This exception occurs regardless of the transmit mask register setting The transmit last slot interrupt can signal...

Page 157: ...R I1 0 Note The example material to the right of the steps shows register settings for configuring an ESSI0 transmit interrupt using transmitter 0 The order of the steps is optional except that the interrupt trigger configuration must not be completed until the ISR configuration is complete Since step 2c may cause an immediate transmit without generating an interrupt perform the transmit data prel...

Page 158: ...mode has a submode called On Demand mode Set the CRB MOD for Network mode and set the frame rate divider to 0 DC 00000 to select On Demand mode This submode does not generate a periodic frame sync A frame sync pulse is generated only when data is available to transmit The frame sync signal indicates the first time slot in the frame On Demand mode requires that the transmit frame sync be internal o...

Page 159: ...me sync signals from the DSP internal system clock The ESSI clock generator consists of a selectable fixed prescaler with a programmable prescaler for bit rate clock generation and a programmable frame rate divider with a word length divider for frame rate sync signal generation 7 4 3 Frame Sync Selection The transmitter and receiver can operate independently The transmitter can have either a bit ...

Page 160: ...en a bit length frame sync is selected 7 4 7 Frame Sync Polarity The CRB FSP bit controls the polarity of the frame sync n When CRB FSP is cleared the polarity of the frame sync is positive that is the frame sync signal is asserted high The ESSI synchronizes on the leading edge of the frame sync signal n When CRB FSP is set the polarity of the frame sync is negative that is the frame sync is asser...

Page 161: ...he SCD0 bit When SCD0 is set SC0 is configured as output When SCD0 is cleared SC0 is configured as input Similarly the SC1 flag is enabled when transmitter 2 is disabled TE2 0 and the SC1 signal is not configured as the transmitter 0 drive enabled signal Bit SSC1 0 The direction of SC1 is determined by the SCD1 bit When SCD1 is set SC1 is an output flag When SCD1 is cleared SC1 is an input flag Wh...

Page 162: ...ve Slot Mask Registers RSMA RSMB page 7 35 This section discusses the ESSI registers and describes their bits Section 7 6 GPIO Signals and Registers on page 7 36 covers ESSI GPIO 7 5 1 ESSI Control Register A CRA The ESSI Control Register A CRA is one of two 24 bit read write control registers that direct the operation of the ESSI CRA controls the ESSI clock generator bit and frame sync rates word...

Page 163: ...ds transferred via the ESSI Word lengths of 8 12 16 24 or 32 bits can be selected The ESSI data path programming model in Figure 7 12 and Figure 7 13 shows additional information on how to select different lengths for data words The ESSI data registers are 24 bits long The ESSI transmits 32 bit words in one of two ways n by duplicating the last bit 8 times when WL 2 0 100 n by duplicating the firs...

Page 164: ...the ESSI frame sync generator functional block diagram 11 PSR 0 Prescaler Range Controls a fixed divide by eight prescaler in series with the variable prescaler This bit extends the range of the prescaler when a slower bit clock is needed When PSR is set the fixed prescaler is bypassed When PSR is cleared the fixed divide by eight prescaler is operational as in Figure 7 3 This definition is revers...

Page 165: ...lk Async TX clk 0 0 0 255 CRA PSR CRA PM7 0 8 12 16 24 1 2 3 4 5 Flag0 Out Sync Mode CRB OF0 CRB TE1 TX 1 Flag0 In Sync Mode SSISR IF0 1 SYN 0 0 8 12 16 24 1 2 3 4 5 2 CRA WL2 0 TX Word Clock Flag0 Opposite from SSI or Frame Sync Transmit Frame Sync Receive RX Word Clock TX Word Clock CRA DC4 0 Receive Control Logic Transmit Control Logic Sync Type Sync Type CRB SYN 0 SYN Internal Rx Frame Sync CR...

Page 166: ... output flags when transmitting data by transmitter 0 through the STD signal only 1 Wait for TDE TX0 empty to be set 2 Write the flags 3 Write the transmit data to the TX register Bits OF0 and OF1 are double buffered so that the flag states appear on the signals when the TX data is transferred to the transmit shift register The flag bit values are synchronized with the data transfer The timing of ...

Page 167: ...1 RLIE 0 Receive Last Slot Interrupt Enable Enables disables an interrupt after the last slot of a frame ends when the ESSI is in Network mode When RLIE is set the DSP is interrupted after the last slot in a frame ends regardless of the receive mask register setting When RLIE is cleared the receive last slot interrupt is disabled The use of the receive last slot interrupt is documented in Section ...

Page 168: ...d On Demand modes for the ESSI to receive data In Network mode clearing RE and setting it again disables the receiver after reception of the current data word The receiver remains disabled until the beginning of the next data frame NOTE The setting of the RE bit does not affect the generation of a frame sync 16 TE0 0 Transmit 0 Enable Enables the transfer of data from TX0 to Transmit Shift Registe...

Page 169: ...ster Any data present in TX2 is not transmitted If TE2 is cleared data can be written to TX2 the TDE bit is cleared but data is not transferred to transmit shift register 2 If the TE2 bit is kept cleared until the start of the next frame it causes the SC1 signal to act as a serial I O flag from the start of the frame in both Normal mode and Network mode The transmit enable sequence in On Demand mo...

Page 170: ... with the last bit of the previous data word 8 7 FSL 1 0 0 Frame Sync Length Selects the length of frame sync to be generated or recognized as in Figure 7 6 on page 7 24 Figure 7 9 on page 7 27 and Figure 7 10 on page 7 27 FSL1 FSL0 Frame Sync Length RX TX 0 0 word word 0 1 word bit 1 0 bit bit 1 1 bit word 6 SHFD 0 Shift Direction Determines the shift direction of the transmit or receive shift re...

Page 171: ...output when SCD1 is cleared SC1 is an input When TE2 is set the value of SCD1 is ignored and the SC1 signal is always an output 2 SCD0 0 Serial Control Direction 0 In Synchronous mode SYN 1 when transmitter 1 is disabled TE1 0 or in Asynchronous mode SYN 0 SCD0 controls the direction of the SC0 I O signal When SCD0 is set SC0 is an output when SCD0 is cleared SC0 is an input When TE1 is set the va...

Page 172: ...s valid Data Data Serial Clock RX TX Frame SYNC One Bit Length FSL1 1 FSL0 0 RX TX Serial Data NOTE Frame sync occurs for one bit time preceding the data Serial Clock TX Frame SYNC Mixed Frame Length FSL1 0 FSL0 1 RX Frame Sync Serial Clock TX Frame SYNC Mixed Frame Length FSL1 1 FSL0 1 TX Serial Data RX Frame SYNC Data Data Data Data Data Data Data Data Data Data RXSerial Data TX Serial Data RX S...

Page 173: ...mit Frame External Receive Frame Internal Frame SYNC SC0 SCK External Transmit Clock External Receive Clock Internal Clock ESSI Bit Clock NOTE Transmitter and receiver may have different clocks and frame syncs SYNCHRONOUS SYN 1 Transmitter Clock Frame SYNC Receiver Clock Frame SYNC SRD ST SC2 Internal Frame SYNC SCK External Clock Internal Clock ESSI Bit Clock NOTE Transmitter and receiver may hav...

Page 174: ...mitter Interrupt or DMA Request and Receiver Interrupt or DMA Request and Flags NOTE Interrupts occur and data is transferred once per frame sync Network Mode MOD 1 Serial Clock Frame SYNC Transmitter Interrupts or DMA Request and Slot 1 Slot 2 Slot 3 Slot 1 Slot 2 Serial Data Receiver Interrupt or DMA Request and Flags Set NOTE Interrupts occur every time slot and a word may be transferred ...

Page 175: ...l Mode External Frame Sync 8 Bit 1 Word in Frame Figure 7 10 Network Mode External Frame Sync 8 Bit 2 Words in Frame Frame SYNC FSL0 0 FSL1 0 Frame SYNC FSL0 0 FSL1 1 Data Out Flags Slot 0 Slot 0 Wait SLOT 0 SLOT 1 SLOT 1 SLOT 0 Frame SYNC FSL0 0 FSL1 0 Frame SYNC FSL0 0 FSL1 1 Flags Data ...

Page 176: ...mitters or to the TSR The TDE bit is cleared when the DSP writes to all the transmit data registers of the enabled transmitters or when the DSP writes to the TSR to disable transmission of the next time slot If the TIE bit is set a DSP transmit data interrupt request is issued when TDE is set 5 ROE 0 Receiver Overrun Error Flag Set when the serial receive shift register is filled and ready to tran...

Page 177: ...enabled data written to a transmit data register during the time slot when TFS is set is transmitted in Network mode during the second time slot in the frame TFS is useful in Network mode to identify the start of a frame TFS is valid only if at least one transmitter is enabled that is when TE0 TE1 or TE2 is set NOTE In Normal mode TFS is always read as 1 when data is being transmitted because ther...

Page 178: ...4 bit transmit shift registers contain the data being transmitted as in Figure 7 12 and Figure 7 13 Data is shifted out to the serial transmit data signals by the selected whether internal or external bit clock when the associated frame sync I O is asserted The word length control bits in CRA determine the number of bits that must be shifted out before the shift registers are considered empty and ...

Page 179: ...STD ESSI Transmit Data Register ESSI Transmit Shift Register 24 bit Data 0 0 0 16 bit Data 12 bit Data 8 bit Data LSB LSB LSB LSB Least Significant Zero Fill b Transmit Registers Transmit High Byte Transmit Middle Byte Transmit Low Byte Transmit High Byte Transmit Middle Byte Transmit Low Byte 23 16 15 8 7 0 23 16 15 8 7 0 7 0 7 0 7 0 7 0 7 0 7 0 MSB MSB MSB NOTES Data is transmitted MSB first if ...

Page 180: ...t Data LSB LSB LSB LSB MSB MSB MSB MSB Least Significant Zero Fill 16 Bit 12 Bit 8 Bit b Transmit Registers Receive High Byte Receive Middle Byte Receive Low Byte Receive High Byte Receive Middle Byte Receive Low Byte 23 16 15 8 7 0 23 16 15 7 0 7 0 7 7 0 7 0 7 0 7 0 NOTES Data is received MSB first if SHFD 0 24 bit fractional format ALC 0 32 bit mode is not shown Transmit High Byte Transmit Middl...

Page 181: ...a register that prevents data transmission in the current transmit time slot For timing purposes TSR is a write only register that behaves as an alternative transmit data register except that rather than transmitting data the transmit data signals of all the enabled transmitters are in the high impedance state for the current time slot 7 5 9 Transmit Slot Mask Registers TSMA TSMB Both transmit slo...

Page 182: ...en TSn is set the transmit sequence proceeds normally Data transfers from the TX register to the shift register during slot number N and the TDE flag is set The TSM slot mask does not conflict with the TSR Even if a slot is enabled in the TSM you can chose to write to the TSR to tri state the signals of the enabled transmitters during the next transmission slot Setting the bits in the TSM affects ...

Page 183: ... the receive sequence proceeds normally Data is received during slot number N and the RDF flag is set When the bits in the RSM are set their setting affects the next frame transmission The frame being transmitted is not affected by the new RSM setting If the RSM is read it shows the current setting When RSMA or RSMB is read by the internal data bus the register contents occupy the two low order by...

Page 184: ...sponding port signal is configured as an ESSI signal When a PCR i bit is cleared the corresponding port signal is configured as a GPIO signal Either a hardware RESET signal or a software RESET instruction clears all PCR bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCx5 PCx4 PCx3 PCx2 PCx1 PCx0 Note For Px 5 0 a 0 selects Pxn as the signal and a 1 selects the specified ESSI si...

Page 185: ... table summarizes the ESSI port signal configurations 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRx5 PRx4 PRx3 PRx2 PRx1 PRx0 Note For bits 5 0 a 0 configures PRxn as a GPI and a 1 configures PRxn as a GPO For ESSI0 the GPIO signals are PC 5 0 For ESSI1 the GPIO signals are PD 5 0 The corresponding direction bits for Port C GPIOs are PRC 5 0 The corresponding direction bits for...

Page 186: ...on the output signal line Either a hardware RESET signal or a software RESET instruction clears all PDRC and PDRD bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDRx5 PDRx4 PDRx3 PDRx2 PDRx1 PDRx0 Note For bits 5 0 the value represents the level that is written to or read from the associated signal line if it is enabled as a GPIO signal by the respective port control register P...

Page 187: ...als The SCI consists of separate transmit and receive sections that can operate asynchronously with respect to each other A programmable baud rate generator supplies the transmit and receive clocks An enable vector and an interrupt vector are included so that the baud rate generator can function as a general purpose timer when the SCI is not using it or when the interrupt timing is the same as tha...

Page 188: ...ternal circuitry such as a watchdog timer The simplest way to recover synchronization is to reset the SCI 8 1 2 Asynchronous Mode Asynchronous data uses a data format with embedded word sync which allows an unsynchronized data clock to be synchronized with the word if the clock rate and number of bits per word is known Thus the clock can be generated by the receiver rather than requiring a separat...

Page 189: ...ed for other processors The usual operational procedure is for each DSP to suspend SCI reception the DSP can continue processing until the beginning of a message Each DSP compares the address in the message header with the DSP s address If the addresses do not match the SCI again suspends reception until the next address If the address matches the DSP reads and processes the message and then suspe...

Page 190: ...it Data TXD This output signal transmits serial data from the SCI transmit shift register Data changes on the negative edge of the asynchronous transmit clock SCLK if SCKP is cleared This output is stable on the positive edge of the transmit clock TXD can be programmed as a GPIO signal PE1 when the SCI TXD function is not in use 8 2 3 SCI Serial Clock SCLK This bidirectional signal provides an inp...

Page 191: ... are set to their reset state However the contents of the SCR remain unaffected so the DSP program can reset the SCI separately from the other internal peripherals During individual reset internal DMA accesses to the data registers of the SCI are not valid and the data is unknown n Stop processing state reset that is the STOP instruction Executing the STOP instruction halts operation of the SCI un...

Page 192: ... to provide an external clock to the SCI When the SCI is configured in Synchronous mode internal clock and all the SCI pins are simultaneously enabled an extra pulse of one DSP clock length is provided on the SCLK pin SSR R8 FE PE OR IDLE RDRF TDRE TRNE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 TCM 15 0 0 RCM 14 0 0 SCCR SCP 13 0 0 COD 12 0 0 CD 11 0 11 0 0 0 ...

Page 193: ...est if it is programmed to service the SCI transmitter 5 Enable transmitters TE 1 and receiver RE 1 according to use Operation starts as follows n For an internally generated clock the SCLK signal starts operation immediately after the SCI is enabled Step 3 above for Asynchronous modes In Synchronous mode the SCLK signal is active only while transmitting that is a gated clock n Data is received on...

Page 194: ... size is in A0 and the starting address is in A1 The program is then loaded one byte at a time least significant byte first After the program is loaded the operating mode is set to zero the CCR is cleared and the DSP begins execution with the first instruction loaded 8 5 Exceptions The SCI can cause five different exceptions in the DSP discussed here from the highest to the lowest priority 1 SCI r...

Page 195: ...wed as three types of registers n Control SCI Control Register SCR in Figure 8 3 SCI Clock Control Register SCCR in Figure 8 4 n Status SCI Status Register SSR in Figure 8 3 n Data transfer SCI Receive Data Registers SRX in Figure 8 7 SCI Transmit Data Registers STX in Figure 8 7 SCI Transmit Data Address Register STXA in Figure 8 7 The SCI includes the GPIO functions described in Section 8 7 GPIO...

Page 196: ...ta 1 Odd Parity 1 Stop TX SSFTD 1 Start D0 or Data Type Stop Bit Odd Parity Mode 6 11 bit Asynchronous Multidrop 1 Start 8 Data 1 Data Type 1 Stop TX SSFTD 1 Start Stop Bit Data Type D7 D6 D5 D4 D3 D2 D1 D0 WDS2 WDS1 WDS0 0 0 0 Note 1 Modes 1 3 and 7 are reserved 2 D0 LSB D7 MSB 3 Data is transmitted and received LSB first if SSFTD 0 or MSB first if SSFTD 1 0 Data Byte Data Type 1 Address Byte D0 ...

Page 197: ...onous 1 Start 8 Data 1 Odd Parity 1 Stop TX SSFTD 0 Start Bit D7 or Data Type Stop Bit Odd Parity Mode 6 11 bit Asynchronous Multidrop 1 Start 8 Data 1 Data Type 1 Stop TX SSFTD 0 Start Bit Stop Bit Data Type Note 1 Modes 1 3 and 7 are reserved 2 D0 LSB D7 MSB 3 Data is transmitted and received LSB first if SSFTD 0 or MSB first if SSFTD 1 D0 D1 D2 D3 D4 D5 D6 D7 0 1 0 D0 D1 D2 D3 D4 D5 D6 WDS2 WDS...

Page 198: ... Polarity Controls the clock polarity sourced or received on the clock signal SCLK eliminating the need for an external inverter When SCKP is cleared the clock polarity is positive when SCKP is set the clock polarity is negative In Synchronous mode positive polarity means that the clock is normally positive and transitions negative during valid data Negative polarity means that the clock is normal...

Page 199: ...interrupt If RIE is cleared the receive data interrupt is disabled and the RDRF bit in the SCI status register must be polled to determine whether the receive data register is full If both RIE and RDRF are set the SCI requests an SCI receive data interrupt from the interrupt controller Receive interrupts with exception have higher priority than normal receive data interrupts Therefore if an except...

Page 200: ...of the last character of the message including the stop bit 4 Write the first byte of the second message to STX In this sequence if the first byte of the second message is not transferred to STX prior to the finish of the preamble transmission the transmit data line remains idle until STX is finally written 8 RE 0 Receiver Enable When RE is set the receiver is enabled When RE is cleared the receiv...

Page 201: ...mode consecutive ones The transmitter s software must provide this idle string between consecutive messages The idle string cannot occur within a valid message because each word frame there contains a start bit that is 0 When WAKE is set the wakeup on address bit mode is selected In the wakeup on address bit mode the SCI receiver is re enabled when the last eighth or ninth data bit received in a c...

Page 202: ...tter counts the number of ones in the data word If the total is not an odd number the parity bit is set thus producing an odd number If the receiver counts an even number of ones an error in transmission has occurred When even parity is selected an even number must result from the calculation performed at both ends of the line or an error in transmission has occurred WDS2 WDS1 WDS0 Mode Word Forma...

Page 203: ...eceived word is transferred to the SRX However the FE flag inhibits further transfer of data into the SRX until it is cleared FE is cleared when the SCI status register is read followed by a read of the SRX A hardware RESET signal a software RESET instruction an SCI individual reset or a STOP instruction clears FE In 8 bit Synchronous mode FE is always cleared If the byte received causes both fram...

Page 204: ...e is a delay of up to 5 5 serial clock cycles between the time that STX is written until TDRE is set indicating the data has been transferred from the STX to the transmit shift register There is a delay of 2 to 4 serial clock cycles between writing STX and loading the transmit shift register in addition TDRE is set in the middle of transmitting the second bit When using an external serial transmit...

Page 205: ...Selects whether an internal or external clock is used for the receiver If RCM is cleared the internal clock is used If RCM is set the external clock from the SCLK signal is used TCM RCM TX Clock RX Clock SCLK Mode 0 0 Internal Internal Output Synchronous asynchronous 0 1 Internal External Input Asynchronous only 1 0 External Internal Input Asynchronous only 1 1 External External Input Synchronous ...

Page 206: ...clock generation circuitry with the formula to compute the bit rate when the internal clock is used 11 0 CD 11 0 0 Clock Divider Specifies the divide ratio of the prescale divider in the SCI clock generator A divide ratio from 1 to 4096 CD 11 0 000 to FFF can be selected Figure 8 5 SCI Baud Rate Generator Table 8 5 SCI Clock Control Register SCCR Bit Definitions Continued Bit Number Bit Name Reset...

Page 207: ...maximum frequency equal to one eighth of the DSP core operating frequency that is 12 5 MHz for a DSP core frequency of 100 MHz For asynchronous operation the SCI can use the internal and external clocks in any combination as the source clocks for the TX clock and RX clock If an external clock is used for the SCLK input it must be sixteen times the desired bit rate designated as the 16 clock as ind...

Page 208: ...nce the programmer can save and process the previous word while the current word is being received The SRX can be read at three locations as SRXL SRXM and SRXH When SRXL is read the contents of the SRX are placed in the lower byte of the data bus and the remaining bits on Figure 8 7 SCI Programming Model Data Registers SRX SRX SRX RXD SCI Receive Data Shift Register Note SRX is the same register d...

Page 209: ...d STXH are used When STXL is written the low byte on the data bus is transferred to the STX When STXM is written the middle byte is transferred to the STX When STXH is written the high byte is transferred to the STX This structure makes it easy for the programmer to unpack the bytes in a 24 bit word for transmission TDXA should be written in 11 bit asynchronous multidrop mode when the data is an a...

Page 210: ...is written to a peripheral device there is a two cycle pipeline delay until any status bits affected by this operation are updated If you read any of those status bits within the next two cycles the bit does not reflect its current status For details see the DSP56300 Family Manual 8 7 GPIO Signals and Registers Three registers control the GPIO functionality of the SCI pins Port E control register ...

Page 211: ...ured as an output GPO a value written to the corresponding PDRE i bit is reflected as a value on the output signal line Either a hardware RESET signal or a software RESET instruction clears all PDR bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRRE2 PRRE1 PRRE0 Note For bits 2 0 a 0 configures PEn as a GPI and a 1 configures PEn as a GPO For the SCI the GPIO signals are PE 2 0...

Page 212: ...GPIO Signals and Registers 8 26 DSP56303 User s Manual ...

Page 213: ...its own register set Each timer has the following capabilities n Uses internal or external clocking n Interrupts the DSP56303 after a specified number of events clocks or signals an external device after counting internal events n Triggers DMA transfers after a specified number of events clocks occurs n Connects to the external world through one bidirectional signal designated TIO 0 2 for timers 0...

Page 214: ...n the X data memory space The three timers are identical in structure and function Either standard polled or interrupt programming techniques can be used to service the timers A single generic timer is discussed in this chapter Each timer includes the following n 24 bit counter n 24 bit read write Timer Control and Status Register TCSR n 24 bit read only Timer Count Register TCR n 24 bit write onl...

Page 215: ...tions 9 2 1 Timer After Reset A hardware RESET signal or software RESET instruction clears the Timer Control and Status Register for each timer thus configuring each timer as a GPIO A timer is active only if the timer enable bit 0 TCSR TE in the specific timer TCSR is set Figure 9 2 Timer Module Block Diagram GDB Control Status Register TCSR Counter Timer interrupt DMA request Timer Control CLK 2 ...

Page 216: ...urs when the timer counter reaches the value given in the Timer Compare Register TCPR for all modes except measurement modes In measurement modes 4 6 a compare exception occurs when the appropriate transition occurs on the TIO signal The Compare exception sets the TCF bit TCF is cleared when a value of one is written to it or when the timer compare interrupt is serviced To configure a timer except...

Page 217: ... mode 0 Internal timer interrupt generated by the internal clock Pulse mode 1 External timer pulse generated by the internal clock Toggle mode 2 Output timing signal toggled by the internal clock Event counter mode 3 Internal timer interrupt generated by an external clock n Measurement Input width mode 4 Input pulse width measurement Input period mode 5 Input signal period measurement Capture mode...

Page 218: ...n read the counter contents at any time from the Timer Count Register TCR 9 3 1 1 Timer GPIO Mode 0 In Mode 0 the timer generates an internal interrupt when a counter value is reached if the timer compare interrupt is enabled see Figure 9 3 and Figure 9 4 When the counter equals the TCPR value TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is set If the TCSR TRM bit is s...

Page 219: ...pare TE Clock CLK 2 or prescale CLK TLR TCPR TCF Compare Interrupt if TCIE 1 Counter TCR first event last event M 0 N N 1 M N N 1 N Mode 0 internal clock no timer output TRM 0 N write preload M write compare TE Clock CLK 2 or prescale CLK TLR TCPR TCF Compare Interrupt if TCIE 1 Counter TCR first event last event M 0 N N 1 M 0 1 N M 1 TOF Overflow Interrupt if TCIE 1 ...

Page 220: ...continues to increment on each timer clock This process repeats until TCSR TE is cleared disabling the timer The TLR value in the TCPR sets the delay between starting the timer and generating the output pulse To generate successive output pulses with a delay of X clock cycles between signals set the TLR value to X 2 and set the TCSR TRM bit This process repeats until the timer is disabled Bit Sett...

Page 221: ...Mode 1 internal clock TRM 0 N write preload M write compare TE CLK 2 or prescale CLK TLR TCPR TCF Compare Interrupt if TCIE 1 first event M 1 N pulse width timer clock period TIO pin INV 0 TIO pin INV 1 TOF Overflow Interrupt if TCIE 1 Counter TCR 0 N N 1 M 0 M 1 Clock ...

Page 222: ...ter continues to increment on each timer clock This process repeats until the timer is cleared disabling the timer The TCPR TLR value sets the delay between starting the timer and toggling the TIO signal To generate output signals with a delay of X clock cycles between toggles set the TLR value to X 2 and set the TCSR TRM bit This process repeats until the timer is disabled that is TCSR TE is clea...

Page 223: ... TRM 0 N write preload M write compare TE TLR TCPR TCF Compare Interrupt if TCIE 1 first event M N First toggle M N clock periods Second and later toggles 2 24 clock periods TIO pin INV 0 TIO pin INV 1 1 Counter TCR 0 N N 1 M 0 M 1 TOF Overflow Interrupt if TCIE 1 CLK 2 or prescale CLK Clock ...

Page 224: ...nsitions increment the counter When the counter matches the value contained in the TCPR TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is set If the TCSR TRM bit is set the counter is loaded with the value of the TLR when the next timer clock is received and the count is resumed If the TCSR TRM bit is cleared the counter continues to increment on each timer clock This pr...

Page 225: ...e preload M write compare TE TIO pin or prescale CLK TLR TCPR TCF Compare Interrupt if TCIE 1 first event M N if clock source is from TIO pin TIO CPUCLK 4 Clock 1 Counter TCR 0 N N 1 M 0 M 1 TOF Overflow Interrupt if TCIE 1 NOTE If INV 1 counter is clocked on 1 to 0 clock transitions instead of 0 to 1 transitions ...

Page 226: ...with the TLR value If TCSR INV is set the timer starts on the first high to low 1 to 0 signal transition on the TIO signal If the INV bit is cleared the timer starts on the first low to high that is 0 to 1 transition on the TIO signal When the first transition opposite in polarity to the INV bit setting occurs on the TIO signal the counter stops TCSR TCF is set and a compare interrupt is generated...

Page 227: ...eing measured stops the counter and loads TCR with the count M N clock periods Next 0 to 1 edge on TIO loads counter and process repeats Mode 4 internal clock TRM 1 N write preload M write compare TE Clock CLK 2 or prescale CLK TLR TCR Counter first event M 0 N N 1 M N 1 N Interrupt Service reads TCR for NOTE If INV 1 a 1 to 0 edge on TIO loads the counter and a 0 to 1 edge on TIO TCF Compare Inte...

Page 228: ...ad into the TCR The TCR then contains the value of the time that elapsed between the two signal transitions on the TIO signal After the second signal transition if the TCSR TRM bit is set the TCSR TE bit is set to clear the counter and enable the timer The counter is repeatedly loaded and incremented until the timer is disabled If the TCSR TRM bit is cleared the counter continues to increment unti...

Page 229: ...rescale CLK TLR TCR Counter first event M 0 N N 1 M M 1 N 1 N NOTE If INV 1 a 1 to 0 edge on TIO loads the counter and a 0 to 1 edge on TIO TCF Compare Interrupt if TCIE 1 TIO pin period being measured loads TCR with count and the counter with N Interrupt Service reads TCR period M N clock periods Counter continues counting does not stop Overflow may occur TOF 1 ...

Page 230: ... a high to low 1 to 0 or low to high 0 to 1 transition of the external clock signals the end of the timing period If the INV bit is set a high to low transition signals the end of the timing period If INV is cleared a low to high transition signals the end of the timing period Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 Mode Name Function TIO Clock 0 1 1 0 6 Capture Measurement Input Interna...

Page 231: ...TCSR TE bit is set and the counter starts the TIO signal assumes the value of INV On each subsequent toggle of the TIO signal the polarity of the TIO signal is reversed For example if the INV bit is set the TIO signal generates the following signal 1010 If the INV bit is cleared the TIO signal generates the following signal 0101 The value of the TLR determines the output period FFFFFF TLR 1 The ti...

Page 232: ...M 1 N write preload M write compare TE Clock CLK 2 or prescale CLK TLR TCPR TCF Compare Interrupt if TCIE 1 Counter TCR first event M 0 N M N N 1 N Period FFFFFF TLR 1 Duty cycle FFFFFF TCPR Ensure that TCPR TLR for correct functionality 0 M 1 TCF Overflow Interrupt if TDIE 1 TIO pin INV 0 TIO pin INV 1 Pulse width Period ...

Page 233: ... compare TE Clock CLK 2 or prescale CLK TLR TCPR TCF Compare Interrupt if TCIE 1 Counter TCR first event M 0 N M 1 2 N Period FFFFFF TLR 1 Duty cycle FFFFFF TCPR Ensure that TCPR TLR for correct functionality 0 M 1 TCF Overflow Interrupt if TDIE 1 TIO pin INV 0 TIO pin INV 1 Pulse width Period NOTE On overflow TCR is loaded with the value of TLR ...

Page 234: ...ach subsequent timer clock This process repeats until the timer is disabled that is TCSR TE is cleared If the counter overflows a pulse is output on the TIO signal with a pulse width equal to the timer clock period If the INV bit is set the pulse polarity is high logical 1 If INV is cleared the pulse polarity is low logical 0 The counter reloads when the TLR is written with a new value while the T...

Page 235: ... TCR first event M 0 N M 1 N TRM 1 is not useful for watchdog function 0 M 1 TOF Overflow Interrupt if TOIE 1 TIO pin INV 0 TIO pin INV 1 Software does not reset watchdog timer watchdog times out N 1 pulse width timer clock period float float low high TIO can connect to the RESET pin internal hardware preserves the TIO value and direction for an additional 2 5 clocks to ensure a reset of valid len...

Page 236: ...hile the TCSR TE bit is set This process repeats until the timer is disabled In Mode 10 internal logic preserves the TIO value and direction for an additional 2 5 internal clock cycles after the hardware RESET signal is asserted This convention ensures that a valid reset signal is generated when the TIO signal resets the DSP56303 Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 Mode Name Function...

Page 237: ...e correct operation disable the timers before the DSP56303 is placed in stop state 9 3 6 DMA Trigger Each timer can also trigger DMA transfers if a DMA channel is programmed to be triggered by a timer event The timer issues a DMA trigger on every event in all modes of operation To ensure that all DMA triggers are serviced provide for the preceding DMA trigger to be serviced before the DMA channel ...

Page 238: ...Write with 0 for future compatibility 23 0 Timer Load Register TLR 23 22 21 20 19 18 17 16 23 0 Timer Compare Register TCPR PCE TRM TCF TOF TOIE TC2 23 0 Timer Count Register TCR TC3 TCSR0 FFFF8F TCSR1 FFFF8B TCSR2 FFFF87 TLR0 FFFF8E TLR1 FFFF8A TLR2 FFFF86 TCR0 FFFF8C TCR1 FFFF88 TCR2 FFFF84 TCPR0 FFFF8D TCPR1 FFFF89 TCPR2 FFFF85 23 0 Timer Prescaler Load Register TPLR TPLR FFFF83 23 0 Timer Pres...

Page 239: ... use of a TIO signal is not affected by the TCSR settings of the timer of the corresponding TIO signal If the prescaler source clock is external the prescaler counter is incremented by signal transitions on the TIO signal The external clock is internally synchronized to the internal clock The external clock frequency must be lower than the DSP56303 internal operating frequency divided by 4 that is...

Page 240: ... 0 for future compatibility Figure 9 22 Timer Prescaler Count Register TPCR Table 9 2 Timer Prescaler Count Register TPCR Bit Definitions Bit Number Bit Name Reset Value Description 23 21 0 Reserved Write to zero for future compatibility 20 0 PC 20 0 0 Prescaler Counter Value Contain the current value of the prescaler counter 23 22 21 20 19 18 17 16 15 14 13 12 TCF TOF PCE DO DI 11 10 9 8 7 6 5 4 ...

Page 241: ...he timer 19 16 0 Reserved Write to zero for future compatibility 15 PCE 0 Prescaler Clock Enable Selects the prescaler clock as the timer source clock When PCE is cleared the timer uses either an internal CLK 2 signal or an external TIO signal as its source clock When PCE is set the prescaler output is the timer source clock for the counter regardless of the timer operating mode To ensure proper o...

Page 242: ...loaded each time counter overflow occurs In measurement 4 5 modes if the TRM and the TCSR TE bits are set the counter is preloaded with the TLR value on each appropriate edge of the input signal If the TRM bit is cleared the counter operates as a free running counter and is incremented on each incoming event 8 INV 0 Inverter Affects the polarity definition of the incoming signal on the TIO signal ...

Page 243: ... 4 Bit Settings Mode Characteristics TC3 TC2 TC1 TC0 Mode Number Mode Function TIO Clock 0 0 0 0 0 Timer and GPIO GPIO 1 Internal 0 0 0 1 1 Timer pulse Output Internal 0 0 1 0 2 Timer toggle Output Internal 0 0 1 1 3 Event counter Input External 0 1 0 0 4 Input width measurement Input Internal 0 1 0 1 5 Input period measurement Input Internal 0 1 1 0 6 Capture event Input Internal 0 1 1 1 7 Pulse ...

Page 244: ...imer control TC 3 0 bit values When clear TE bit disables the timer NOTE When all three timers are disabled and the signals are not in GPIO mode all three TIO signals are tri stated To prevent undesired spikes on the TIO signals when you switch from tri state into active state these signals should be tied to the high or low signal state by pull up or pull down resistors Table 9 4 Inverter INV Bit ...

Page 245: ...d the new event occurs In this mode the counter is also reloaded whenever the TLR is written with a new value while TCSR TE is set n In all modes if TCSR TRM is cleared TRM 0 the counter operates as a free running counter 4 Width of the high input pulse is measured Width of the low input pulse is measured 5 Period is measured between the rising edges of the input signal Period is measured between ...

Page 246: ...hat is the timer compare interrupt enable bit in the TCSR is set The TCPR is ignored in measurement modes 9 4 7 Timer Count Register TCR The TCR is a 24 bit read only register In timer and watchdog modes the contents of the counter can be read at any time from the TCR register In measurement modes the TCR is loaded with the current value of the counter on the appropriate edge of the input signal a...

Page 247: ...xternal memory of SRAM type is used The accesses will be performed using 31 wait states with no address attributes selected default area If MC MB MA 001 then it loads a program RAM segment from consecutive byte wide P memory locations starting at P D00000 bits 7 0 The memory is selected by the Address Attribute AA1 and is accessed with 31 wait states The EPROM bootstrap code expects to read 3 byte...

Page 248: ... program execution starts from the same address where loading started The Host Interface bootstrap load program may be stopped by setting the Host Flag 0 HF0 This will start execution of the loaded program from the specified starting address If MC MB MA 101 then it loads the program RAM from the Host Interface programmed to operate in the HC11 non multiplexed mode The HOST HC11 bootstrap code expe...

Page 249: ...aded The program words will be stored in contiguous PRAM memory locations starting at the specified starting address After reading the program words program execution starts from the same address where loading started The Host Interface bootstrap load program may be stopped by setting the Host Flag 0 HF0 This will start execution of the loaded program from the specified starting address BOOT equ D...

Page 250: ...ownloading is terminated the program will start execution of the loaded program from the specified starting address The HI08 boot ROM program enables the following busses to download programs through the HI08 port 1 ISA Dual strobes non multiplexed bus with negative strobe pulses dual positive request 2 HC11 Single strobe non multiplexed bus with positive strobe pulse single negative request 4 i80...

Page 251: ...d HA9EN 0 address 9 enable bit has no meaning in non multiplexed bus HA8EN 0 address 8 enable bit has no meaning in non multiplexed bus HGEN 0 Host GPIO pins are disabled bra HI08CONT I8051HOSTLD movep 0001110000011110 x M_HPCR Configure the following conditions HAP 0 Negative host acknowledge HRP 0 Negative host request HCSP 0 Negative chip select input HD HS 1 Dual strobes bus RD and WR strobes ...

Page 252: ... non multiplexed bus HGEN 0 Host GPIO pins are disabled HI08CONT bset HEN x M_HPCR Enable the HI08 to operate as host interface set HEN 1 jclr HRDF x M_HSR wait for the program length to be written movep x M_HRX a0 jclr HRDF x M_HSR wait for the program starting address to be written movep x M_HRX r0 move r0 r1 do a0 HI08LOOP set a loop with the downloaded length counts HI08LL jset HRDF x M_HSR HI...

Page 253: ...ived byte asr 8 a a _LOOP8 movem a1 p r0 Store 24 bit result in P mem _LOOP7 bra FINISH Boot from SCI done This is the routine that loads from external EPROM MC MB MA 001 EPROMLD move BOOT r2 r2 address of external EPROM movep AARV X M_AAR1 aar1 configured for SRAM types of access do 6 _LOOP9 read number of words and starting address movem p r2 a2 Get the 8 LSB from ext P mem asr 8 a a Shift 8 bit...

Page 254: ...EQUATES for I O Port Programming Register Addresses M_HDR EQU FFFFC9 Host port GPIO data Register M_HDDR EQU FFFFC8 Host port GPIO direction Register M_PCRC EQU FFFFBF Port C Control Register M_PRRC EQU FFFFBE Port C Direction Register M_PDRC EQU FFFFBD Port C GPIO Data Register M_PCRD EQU FFFFAF Port D Control register M_PRRD EQU FFFFAE Port D Direction Data Register M_PDRD EQU FFFFAD Port D GPIO...

Page 255: ...Host Flag 3 HSR bits definition M_HRDF EQU 0 Host Receive Data Full M_HTDE EQU 1 Host Receive Data Empty M_HCP EQU 2 Host Command Pending M_HF0 EQU 3 Host Flag 0 M_HF1 EQU 4 Host Flag 1 HPCR bits definition M_HGEN EQU 0 Host Port GPIO Enable M_HA8EN EQU 1 Host Address 8 Enable M_HA9EN EQU 2 Host Address 9 Enable M_HCSEN EQU 3 Host Chip Select Enable M_HREN EQU 4 Host Request Enable M_HAEN EQU 5 Ho...

Page 256: ...QU 2 Word Select 2 M_SSFTD EQU 3 SCI Shift Direction M_SBK EQU 4 Send Break M_WAKE EQU 5 Wakeup Mode Select M_RWU EQU 6 Receiver Wakeup Enable M_WOMS EQU 7 Wired OR Mode Select M_SCRE EQU 8 SCI Receiver Enable M_SCTE EQU 9 SCI Transmitter Enable M_ILIE EQU 10 Idle Line Interrupt Enable M_SCRIE EQU 11 SCI Receive Interrupt Enable M_SCTIE EQU 12 SCI Transmit Interrupt Enable M_TMIE EQU 13 Timer Inte...

Page 257: ...B SSI1 Transmit Data Register 1 M_TX12 EQU FFFFAA SSI1 Transmit Data Register 2 M_TSR1 EQU FFFFA9 SSI1 Time Slot Register M_RX1 EQU FFFFA8 SSI1 Receive Data Register M_SSISR1 EQU FFFFA7 SSI1 Status Register M_CRB1 EQU FFFFA6 SSI1 Control Register B M_CRA1 EQU FFFFA5 SSI1 Control Register A M_TSMA1 EQU FFFFA4 SSI1 Transmit Slot Mask Register A M_TSMB1 EQU FFFFA3 SSI1 Transmit Slot Mask Register B M...

Page 258: ...Transmit Last Slot Interrupt Enable M_SRLIE EQU 21 SSI Receive Last Slot Interrupt Enable M_STEIE EQU 22 SSI Transmit Error Interrupt Enable M_SREIE EQU 23 SSI Receive Error Interrupt Enable SSI Status Register Bit Flags M_IF EQU 3 Serial Input Flag Mask M_IF0 EQU 0 Serial Input Flag 0 M_IF1 EQU 1 Serial Input Flag 1 M_TFS EQU 2 Transmit Frame Sync Flag M_RFS EQU 3 Receive Frame Sync Flag M_TUE EQ...

Page 259: ...RQD Mode Trigger Mode M_D0L EQU 3000 DMA0 Interrupt priority Level Mask M_D0L0 EQU 12 DMA0 Interrupt Priority Level low M_D0L1 EQU 13 DMA0 Interrupt Priority Level high M_D1L EQU C000 DMA1 Interrupt Priority Level Mask M_D1L0 EQU 14 DMA1 Interrupt Priority Level low M_D1L1 EQU 15 DMA1 Interrupt Priority Level high M_D2L EQU 30000 DMA2 Interrupt priority Level Mask M_D2L0 EQU 16 DMA2 Interrupt Prio...

Page 260: ...re Register M_TCR0 EQU FFFF8C TIMER0 Count Register Register Addresses Of TIMER1 M_TCSR1 EQU FFFF8B TIMER1 Control Status Register M_TLR1 EQU FFFF8A TIMER1 Load Reg M_TCPR1 EQU FFFF89 TIMER1 Compare Register M_TCR1 EQU FFFF88 TIMER1 Count Register Register Addresses Of TIMER2 M_TCSR2 EQU FFFF87 TIMER2 Control Status Register M_TLR2 EQU FFFF86 TIMER2 Load Reg M_TCPR2 EQU FFFF85 TIMER2 Compare Regis...

Page 261: ... Offset Register 3 Register Addresses Of DMA0 M_DSR0 EQU FFFFEF DMA0 Source Address Register M_DDR0 EQU FFFFEE DMA0 Destination Address Register M_DCO0 EQU FFFFED DMA0 Counter M_DCR0 EQU FFFFEC DMA0 Control Register Register Addresses Of DMA1 M_DSR1 EQU FFFFEB DMA1 Source Address Register M_DDR1 EQU FFFFEA DMA1 Destination Address Register M_DCO1 EQU FFFFE9 DMA1 Counter M_DCR1 EQU FFFFE8 DMA1 Cont...

Page 262: ...1 M_DAM EQU 3f0 DMA Address Mode Mask DAM5 DAM0 M_DAM0 EQU 4 DMA Address Mode 0 M_DAM1 EQU 5 DMA Address Mode 1 M_DAM2 EQU 6 DMA Address Mode 2 M_DAM3 EQU 7 DMA Address Mode 3 M_DAM4 EQU 8 DMA Address Mode 4 M_DAM5 EQU 9 DMA Address Mode 5 M_D3D EQU 10 DMA Three Dimensional Mode M_DRS EQU F800 DMA Request Source Mask DRS0 DRS4 M_DCON EQU 16 DMA Continuous Mode M_DPR EQU 60000 DMA Channel Priority ...

Page 263: ...1 DMA Active Channel 2 A 9 Phase Locked Loop PLL equates EQUATES for Phase Locked Loop PLL Register Addresses Of PLL M_PCTL EQU FFFFFD PLL Control Register PLL Control Register M_MF EQU FFF Multiplication Factor Bits Mask MF0 MF11 M_DF EQU 7000 Division Factor Bits Mask DF0 DF2 M_XTLR EQU 15 XTAL Range select bit M_XTLD EQU 16 XTAL Disable Bit M_PSTP EQU 17 STOP Processing State Bit M_PEN EQU 18 P...

Page 264: ...H EQU 22 Bus Lock Hold M_BRH EQU 23 Bus Request Hold DRAM Control Register M_BCW EQU 3 In Page Wait States Bits Mask BCW0 BCW1 M_BRW EQU C Out Of Page Wait States Bits Mask BRW0 BRW1 M_BPS EQU 300 DRAM Page Size Bits Mask BPS0 BPS1 M_BPLE EQU 11 Page Logic Enable M_BME EQU 12 Mastership Enable M_BRE EQU 13 Refresh Enable M_BSTR EQU 14 Software Triggered Refresh M_BRF EQU 7F8000 Refresh Rate Bits M...

Page 265: ...its in SR M_CP1 EQU 23 bit 1 of priority bits in SR control and status bits in OMR M_CDP EQU 300 mask for CORE DMA priority bits in OMR M_MA EQU0 Operating Mode A M_MB EQU1 Operating Mode B M_MC EQU2 Operating Mode C M_MD EQU3 Operating Mode D M_EBD EQU 4 External Bus Disable bit in OMR M_SD EQU 6 Stop Delay M_MS EQU 7 Memory Switch bit in OMR M_CDP0 EQU 8 bit 0 of priority bits in OMR M_CDP1 EQU ...

Page 266: ...I_TRAP EQU I_VEC 08 Trap I_NMI EQU I_VEC 0A Non Maskable Interrupt Interrupt Request Pins I_IRQA EQU I_VEC 10 IRQA I_IRQB EQU I_VEC 12 IRQB I_IRQC EQU I_VEC 14 IRQC I_IRQD EQU I_VEC 16 IRQD DMA Interrupts I_DMA0 EQU I_VEC 18 DMA Channel 0 I_DMA1 EQU I_VEC 1A DMA Channel 1 I_DMA2 EQU I_VEC 1C DMA Channel 2 I_DMA3 EQU I_VEC 1E DMA Channel 3 I_DMA4 EQU I_VEC 20 DMA Channel 4 I_DMA5 EQU I_VEC 22 DMA C...

Page 267: ... Data With Exception Status I_SI1RLS EQU I_VEC 44 ESSI1 Receive last slot I_SI1TD EQU I_VEC 46 ESSI1 Transmit data I_SI1TDE EQU I_VEC 48 ESSI1 Transmit Data With Exception Status I_SI1TLS EQU I_VEC 4A ESSI1 Transmit last slot SCI Interrupts I_SCIRD EQU I_VEC 50 SCI Receive Data I_SCIRDE EQU I_VEC 52 SCI Receive Data With Exception Status I_SCITD EQU I_VEC 54 SCI Transmit Data I_SCIIL EQU I_VEC 56 ...

Page 268: ...Interrupt Equates A 22 DSP56303 User s Manual ...

Page 269: ... bit and the hexadecimal value for each register You can photocopy these sheets and reuse them for each application development project For details on the instruction set of the DSP56300 family of DSPs see the DSP56300 Family Manual n Table B 2 Internal I O Memory Map X Data Memory on page B 3 lists the memory addresses of all on chip peripherals n Table B 3 Interrupt Sources on page B 8 lists the...

Page 270: ... Port Control Registers page 22 Figure B 12 Host Control Register page 23 Figure B 13 Interrupt Control and Command Vector Registers page 24 Figure B 14 Interrupt Vector and Host Transmit Data Registers page 25 ESSI Figure B 15 ESSI Control Register A CRA page 26 Figure B 16 ESSI Control Register B CRB page 27 Figure B 17 ESSI Transmit and Receive Slot Mask Registers TSM RSM page 28 SCI Figure B 1...

Page 271: ...er 2 AAR2 FFF6 FFFFF6 Address Attribute Register 3 AAR3 FFF5 FFFFF5 ID Register IDR DMA FFF4 FFFFF4 DMA Status Register DSTR FFF3 FFFFF3 DMA Offset Register 0 DOR0 FFF2 FFFFF2 DMA Offset Register 1 DOR1 FFF1 FFFFF1 DMA Offset Register 2 DOR2 FFF0 FFFFF0 DMA Offset Register 3 DOR3 DMA0 FFEF FFFFEF DMA Source Address Register DSR0 FFEE FFFFEE DMA Destination Address Register DDR0 FFED FFFFED DMA Cou...

Page 272: ...DSR5 FFDA FFFFDA DMA Destination Address Register DDR5 FFD9 FFFFD9 DMA Counter DCO5 FFD8 FFFFD8 DMA Control Register DCR5 FFD7 FFFFD7 Reserved FFD6 FFFFD6 Reserved FFD5 FFFFD5 Reserved FFD4 FFFFD4 Reserved FFD3 FFFFD3 Reserved FFD2 FFFFD2 Reserved FFD1 FFFFD1 Reserved FFD0 FFFFD0 Reserved FFCF FFFFCF Reserved FFCE FFFFCE Reserved FFCD FFFFCD Reserved FFCC FFFFCC Reserved FFCB FFFFCB Reserved FFCA ...

Page 273: ...gister 1 TX01 FFBA FFFFBA ESSI 0 Transmit Data Register 2 TX02 FFB9 FFFFB9 ESSI 0 Time Slot Register TSR0 FFB8 FFFFB8 ESSI 0 Receive Data Register RX0 FFB7 FFFFB7 ESSI 0 Status Register SSISR0 FFB6 FFFFB6 ESSI 0 Control Register B CRB0 FFB5 FFFFB5 ESSI 0 Control Register A CRA0 FFB4 FFFFB4 ESSI 0 Transmit Slot Mask Register A TSMA0 FFB3 FFFFB3 ESSI 0 Transmit Slot Mask Register B TSMB0 FFB2 FFFFB2...

Page 274: ...ot Mask Register B RSMB1 FFA0 FFFFA0 Reserved Port E FF9F FFFF9F Port E Control Register PCRE FF9E FFFF9E Port E Direction Register PRRE FF9D FFFF9D Port E GPIO Data Register PDRE SCI FF9C FFFF9C SCI Control Register SCR FF9B FFFF9B SCI Clock Control Register SCCR FF9A FFFF9A SCI Receive Data Register High SRXH FF99 FFFF99 SCI Receive Data Register Middle SRXM FF98 FFFF98 SCI Receive Data Register...

Page 275: ...ister TLR1 FF89 FFFF89 Timer 1 Compare Register TCPR1 FF88 FFFF88 Timer 1 Count Register TCR1 FF87 FFFF87 Timer 2 Control Status Register TCSR2 FF86 FFFF86 Timer 2 Load Register TLR2 FF85 FFFF85 Timer 2 Compare Register TCPR2 FF84 FFFF84 Timer 2 Count Register TCR2 FF83 FFFF83 Timer Prescaler Load Register TPLR FF82 FFFF82 Timer Prescaler Count Register TPCR FF81 FFFF81 Reserved FF80 FFFF80 Reserv...

Page 276: ...12 0 2 IRQB VBA 14 0 2 IRQC VBA 16 0 2 IRQD VBA 18 0 2 DMA Channel 0 VBA 1A 0 2 DMA Channel 1 VBA 1C 0 2 DMA Channel 2 VBA 1E 0 2 DMA Channel 3 VBA 20 0 2 DMA Channel 4 VBA 22 0 2 DMA Channel 5 VBA 24 0 2 Timer 0 Compare VBA 26 0 2 Timer 0 Overflow VBA 28 0 2 Timer 1 Compare VBA 2A 0 2 Timer 1 Overflow VBA 2C 0 2 Timer 2 Compare VBA 2E 0 2 Timer 2 Overflow VBA 30 0 2 ESSI0 Receive Data VBA 32 0 2 ...

Page 277: ...Slot VBA 4C 0 2 Reserved VBA 4E 0 2 Reserved VBA 50 0 2 SCI Receive Data VBA 52 0 2 SCI Receive Data With Exception Status VBA 54 0 2 SCI Transmit Data VBA 56 0 2 SCI Idle Line VBA 58 0 2 SCI Timer VBA 5A 0 2 Reserved VBA 5C 0 2 Reserved VBA 5E 0 2 Reserved VBA 60 0 2 Host Receive Data Full VBA 62 0 2 Host Transmit Data Empty VBA 64 0 2 Host Command Default VBA 66 0 2 Reserved VBA FE 0 2 Reserved ...

Page 278: ...upt IRQD External Interrupt DMA Channel 0 Interrupt DMA Channel 1 Interrupt DMA Channel 2 Interrupt DMA Channel 3 Interrupt DMA Channel 4 Interrupt DMA Channel 5 Interrupt Host Command Interrupt Host Transmit Data Empty Host Receive Data Full ESSI0 RX Data with Exception Interrupt ESSI0 RX Data Interrupt ESSI0 Receive Last Slot Interrupt ESSI0 TX Data With Exception Interrupt ESSI0 Transmit Last S...

Page 279: ... Exception Interrupt Lowest SCI Receive Data Highest SCI Transmit Data SCI Idle Line SCI Timer Timer0 Overflow Interrupt Timer0 Compare Interrupt Timer1 Overflow Interrupt Timer1 Compare Interrupt Timer2 Overflow Interrupt Lowest Timer2 Compare Interrupt Table B 4 Interrupt Source Priorities Within an IPL Continued Priority Interrupt Source ...

Page 280: ...0 Exceptions Masked 00 01 10 11 None IPL 0 IPL 0 1 IPL 0 1 2 Carry Overflow Zero Negative Unnormalized U Acc 47 xnor Acc 46 Extension Limit FFT Scaling S Acc 46 xor Acc 45 Sixteen Bit Compatibilitity Double Precision Multiply Mode Loop Flag DO Forever Flag Sixteen Bit Arithmetic Instruction Cache Enable Arithmetic Saturation Rounding Mode Core Priority CP 1 0 Core Priority 00 01 10 11 0 lowest 1 2...

Page 281: ...p from MC68302 host Application Date Programmer Sheet 2 of 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EBD MC MB MA 19 18 17 16 23 22 21 20 SD BRT TAS SEN CDP1 CDP0 WRP EOV EUN XYS BE MD Core DMA Priority CDP 1 0 Core DMA Priority 00 01 10 11 Core vs DMA Priority DMA accesses Core DMA accesses Core DMA accesses Core 0 0 0 0 Chip Operating Mode Register COM System Stack Control Status Register SCS Exte...

Page 282: ...ge IRQC Mode ICL1 ICL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 IDL2 Trigger 0 Level 1 Neg Edge IRQD Mode IDL1 IDL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 Interrupt Priority Register IPRC X FFFFFF Read Write Reset 000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 23 22 21 20 DMA5 IPL D5L1 D5L0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 DMA4 IPL D4L1 D4L0 Enabled IPL ...

Page 283: ... 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 Host IPL S0L1 S0L0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 ESSI0 IPL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S1L1 S1L0 S0L1 S0L0 HPL1 HPL0 23 22 21 20 19 18 16 17 SCL0 SCL1 TOL0 TOL1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S1L1 S1L0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 ESSI1 IPL SCL1 SCL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 SCI IPL TO...

Page 284: ...al Oscillator 1 EXTAL Driven From An External Source Clock Output Disable COD 0 50 Duty Cycle Clock 1 Pin Held In High State Crystal Range Bit XTLR 0 External Xtal Freq 200KHz 1 External Xtal Freq 200KHz Predivision Factor Bits PD0 PD3 PD3 PD0 Predivision Factor PDF 0 1 2 F 1 2 3 16 Multiplication Factor Bits MF0 MF11 MF11 MF0 Multiplication Factor MF 000 001 002 FFF FFF 1 2 3 4095 4096 PSTP and P...

Page 285: ...st Hold Bit 23 0 BR pin is asserted only for attempted 1 BR pin is always asserted or pending access NOTE All BCR bits are read write control bits These read write control bits define the number of wait states inserted into each external SRAM access to the designated area The value of these bits should not be programmed as zero Area 1 Wait Control Bits 9 5 Application Date Programmer Sheet 1 of 3 ...

Page 286: ... 19 18 17 16 23 22 21 20 BRP BRF 7 0 BPS 1 0 BCW 1 0 X FFFFFA Read Write BRW 1 0 BSTR BREN BME BPLE if the refresh counter is enabled i e BREN 1 Bus Software Triggered 0 Refresh complete reset 1 Software triggered refresh request Bus Refresh 0 Disable 1 Enable Bus Mastership 0 Disable 1 Enable Bus Page Logic 0 Disable 1 Enable Reserved Program as 0 0 0 0 0 0 Bus DRAM Page Size Bits 9 8 00 9 bit co...

Page 287: ...a space accesses 0 Disable AA pin and logic during 1 Enable AA pin and logic during Bus X Data Memory Enable Bit 4 external X data space accesses external X data space accesses 0 Disable AA pin and logic during 1 Enable AA pin and logic during Bus Program Memory Enable Bit 3 external program space accesses external program space accesses Bus Address Attribute Polarity Bit 2 0 AA RAS signal is acti...

Page 288: ...Y Memory Space 10 P Memory Space 11 Reserved DMA Destination Space Bits 3 2 DSS 1 0 DMA Destination Memory 00 X Memory Space 01 Y Memory Space 10 P Memory Space 11 Reserved DMA Request Source Bits 15 11 DRS 4 0 Requesting Device 00000 00011 External IRQA IRQB IRQC IRQD 00100 01001 Transfer done from channel 0 1 2 3 4 5 01010 01011 ESSI0 Receive Transmit Data 01100 01101 ESSI1 Receive Transmit Data...

Page 289: ...gister Application Date Programmer Sheet 1 of 5 HOST 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 23 22 21 20 Transmit High Byte Transmit Middle Byte Transmit Low Byte Host Transmit Data usually Loaded by program Host Transmit Data Register HTX X FFFFC7 Write Only Reset empty ...

Page 290: ...0 1 HCS HA10 HC10 if HMUX 1 Host Address Line 9 Enable 0 HA9 GPIO 1 HA9 HA9 Host Address Line 8 Enable 0 HA8 GPIO 1 HA8 HA8 Host GPIO Port Enable 0 GPIO Pins Disable 1 GPIO Pin Enable Host Acknowledge Priority 0 HACK Active Low 1 HACK Active High Host Chip Select Polarity 0 HCS Active Low Host Dual Data Strobe 0 Singles Stroke 1 Dual Stoke Host Multiplexed Bus 0 Nonmultiplexed 1 Multiplexed Host A...

Page 291: ... Reserved Program as 0 7 6 5 4 3 2 1 0 15 0 0 0 Host Receive Interrupt Enable 1 Enable 0 Disable HCIE HRIE HF3 HTIE HF2 Host Flag 2 Host Command Interrupt Enable Host Transmit Interrupt Enable 1 Enable 0 Disable 0 Host Control Register HCR X FFFFC2 Read Write Reset 0 if HRDF 1 if HTDE 1 1 Enable 0 Disable if HCP 1 Host Flag 3 ...

Page 292: ...1 Host DSP Host Flags Write Only Initialize Write Only Host Little Endian Receive Request Enable DMA Off 0 Interrupts Disabled 1 Interrupts Enabled DMA On 0 Host DSP 1 DSP Host 0 No Action 1 Initialize DMA HDRQ 0 HDRQ HREQ HTRQ HACK HRRQ 0 HREQ HACK 1 HTRQ HRRQ Reset 00 Reserved Program as 0 7 6 5 4 3 2 1 0 HC0 HC4 HC1 HC3 HC7 HC5 Command Vector Register CVR HC2 Reset 32 Contains the host command ...

Page 293: ...nsmit Byte Registers Host Addresses 7 6 5 4 Write Only Reset 00 7 0 7 0 0 7 Host Transmit Data usually loaded by program 6 5 4 0 0 0 0 0 0 0 0 0 7 7 Transmit Middle Byte Transmit High Byte Not Used Transmit Low Byte 7 6 5 4 3 2 1 0 IV0 IV4 IV1 IV3 IV7 IV5 Interrupt Vector Register IVR IV2 Reset 0F Contains the interrupt vector or number IV6 Host Address 3 Read Write ...

Page 294: ...s 1 1 0 Reserved 1 1 1 Reserved Select SC1 as Tx 0 drive enable 0 SC1 functions as serial I O flag 1 functions as driver enable of Tx 0 external buffer Frame Rate Divider Control DC4 0 00 1F 1 to 32 Divide ratio for Normal mode of time slots for Network Prescaler Range 0 divide by 8 1 divide by 1 Prescale Modulus Select PM 7 0 00 FF divide by 1 to 256 The combination of PSR 1 and PM 7 0 00 is forb...

Page 295: ...ve Last Slot Interrupt Enable 0 Disable 1 Enable Transmit Exception Interrupt Enable 0 Disable 1 Enable Transmit 0 Enable 0 Disable 1 Enable Receiver Enable 0 Disable 1 Enable Clock Polarity 0 out on rising in on falling 1 in on rising out on falling Sync Async Control 0 Asynchronous 1 Synchronous Frame Sync Polarity 0 high level positive 1 low level negative Frame Sync Relative Timing 0 with firs...

Page 296: ...Receive Slot Mask A RSMA 0 1 ESSI Receive Slot Mask B RSMB 0 1 ESSI Transmit Slot Mask A TSMA 0 1 ESSI Transmit Slot Mask B TSMB 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RS7 RS5 RS4 RS3 RS2 RS1 RS0 16 23 RS6 0 RS15 RS14 RS13 RS12 RS11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TS23 TS21 TS20 TS19 TS18 TS17 TS16 16 23 TS22 0 TS31 TS30 TS29 TS28 TS27 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TS7 TS5 TS4 TS3...

Page 297: ... bit Asynchronous 1 Start 8 Data 1 Stop 0 1 1 Reserved 1 0 0 11 bit Asynchronous 1 Start 8 Data Even Parity 1 Stop 1 0 1 11 bit Asynchronous 1 Start 8 Data Odd Parity 1 Stop 1 1 0 11 bit Multidrop 1 Start 8 Data Data Type 1 Stop 1 1 1 Reserved Transmitter Enable 0 Transmitter Disable 1 Transmitter Enable Transmit Interrupt Enable 0 Transmit Interrupts Disabled 1 Transmit Interrupts Enabled Idle Li...

Page 298: ...095 FFF Icyc 4096 SCI Clock Prescaler 0 1 1 8 Clock Out Divider 0 Divide clock by 16 before feed to SCLK 1 Feed clock to directly to SCLK TCM RCM TX Clock RX Clock SCLK Pin Mode 0 0 Internal Internal Output Synchronous Asynchronous 0 1 Internal External Input Asynchronous only 1 0 External Internal Input Asynchronous only 1 1 External External Input Synchronous Asynchronous Receiver Clock Mode Sou...

Page 299: ...on Date Programmer Sheet 1 of 3 Timers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 23 22 21 20 PS0 PS1 0 Prescaler Preload Value PL 20 0 Reserved Program as 0 Timer Prescaler Load Register TPLR X FFFF83 Read Write Reset 000000 PS 1 0 Prescaler Clock Source 00 Internal CLK 2 01 TIO0 10 TIO1 11 TIO2 ...

Page 300: ... Mode Bit 9 1 Timer is reloaded when selected condition occurs 0 Timer operates as a free running counter Timer Overflow Flag Bit 20 0 1 has been written to TCSR TOF or timer Overflow interrupt serviced 1 Counter wraparound has occurred Direction Bit 11 0 TIO pin is input 1 TIO pin is output Data Output Bit 13 0 Zero written to TIO pin 1 One written to TIO pin Data Input Bit 12 0 Zero read on TIO ...

Page 301: ... Load Registers TLR Application Date Programmer Sheet 3 of 3 Timers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 23 22 21 20 Timer Reload Value Timer Load Register TLR 0 2 TLR0 X FFFF8E Write Only Reset 000000 TLR1 X FFFF8A Write Only TLR2 X FFFF86 Write Only ...

Page 302: ... DR5 DR4 DR3 DR2 DR1 DR0 DR6 DR15 DR14 DR13 DR12 DR8 DR11 DR9 DR10 X FFFFC8 Write Reset 00 Host Data Direction Register HDDR DRx 0 HIx is Input DRx 1 HIx is Output 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D5 D4 D3 D2 D1 D0 D6 D15 D14 D13 D12 D8 D11 D9 D10 X FFFFC9 Write Reset Undefined Host Data Register HDR DRx holds value of corresponding HI08 GPIO pin DR7 D7 Function depends on HDDR Port B HI08 ...

Page 303: ...gured as ESSI PCn 0 Port Pin configured as GPIO Port C ESSI0 23 6 5 4 3 2 1 0 PRC5 PRC4 PRC3 PRC2 PRC1 PRC0 Port C Direction Register PRRC X FFFFBE Read Write Reset 000000 0 0 PDCn 1 Port Pin is Output PDCn 0 Port Pin is Input 23 6 5 4 3 2 1 0 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 Port C GPIO Data Register PDRC X FFFFBD Read Write Reset 000000 0 0 if port pin n is GPIO input then PDn reflects the value on...

Page 304: ...ESSI PCn 0 Port Pin configured as GPIO 23 6 5 4 3 2 1 0 PRD5 PRD4 PRD3 PRD2 PRD1 PRD0 Port D Direction Register PRRD X FFFFAE Read Write Reset 000000 0 0 PDCn 1 Port Pin is Output PDCn 0 Port Pin is Input 23 6 5 4 3 2 1 0 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 Port D GPIO Data Register PDRD X FFFFAD Read Write Reset 000000 0 0 if port pin n is GPIO input then PDn reflects the value on port pin n if port pi...

Page 305: ... Pin configured as ESSI PCn 0 Port Pin configured as GPIO 23 6 5 4 3 2 1 0 PRE2 PRE1 PRE0 Port E Direction Register PRRE X FFFF9E Read Write Reset 000000 0 0 PDCn 1 Port Pin is Output PDCn 0 Port Pin is Input 23 6 5 4 3 2 1 0 PDE2 PDE1 PDE0 Port E GPIO Data Register PDRE X FFFF9D Read Write Reset 000000 0 0 if port pin n is GPIO input then PDn reflects the value on port pin n if port pin n is GPIO...

Page 306: ...Programming Sheets B 38 DSP56303 User s Manual ...

Page 307: ... internal 1 10 multiplexed 2 2 non multiplexed 2 2 Bus Access Type BAT bits 4 32 Bus Address Attribute Polarity BAAP bit 4 31 Bus Address to Compare BAC bits 4 30 Bus Area 0 Wait State Control BA0W bits 4 27 Bus Area 1 Wait State Control BA1W bits 4 27 Bus Area 2 Wait State Control BA2W bits 4 26 Bus Area 3 Wait State Control BA3W bits 4 26 Bus Column In Page Wait State BCW bit 4 29 Bus Control Re...

Page 308: ...rrupt Enable REIE 7 19 Receive Interrupt Enable RIE 7 19 Receive Last Slot Interrupt Enable RLIE 7 19 Serial Control Direction 0 SCD0 7 23 Serial Control Direction 1 SCD1 7 23 Serial Control Direction 2 SCD2 7 23 Serial Output Flag 0 OF0 7 23 Serial Output Flag 1 OF1 7 23 Shift Directions SHFD 7 22 Synchronous Asynchronous SYN 7 21 Transmit 0 Enable TE0 7 20 Transmit 1 Enable TE1 7 21 Transmit 2 E...

Page 309: ...11 7 17 Clock Sources 7 3 codec 7 13 control and time slot registers 7 6 control direction of SC2 I O signal 7 23 Control Register A CRA Alignment Control ALC 7 16 Frame Rate Divider Control DC 7 16 Prescale Modulus Select PM 7 16 Prescaler Range PSR 7 16 programming sheet B 26 Select SCK SSC1 7 15 Word Length Control WL 7 15 Control Register B CRB Clock Polarity CKP 7 22 Clock Source Directions S...

Page 310: ...PI protocol 7 2 Synchronous mode 7 4 7 11 7 13 Synchronous Serial Interface Status Register SSISR 7 14 7 28 bit definitions 7 28 Receive Data Register Full RDF 7 28 Receiver Frame Sync Flag RFS 7 29 Receiver Overrun Error Flag ROE 7 28 Serial Input Flag 0 IF0 7 29 Serial Input Flag 1 IF1 7 29 Transmit Data Register Empty TDE 7 28 Transmit Frame Sync Flag TFS 7 29 Transmitter Underrun Error Flag TU...

Page 311: ...it 6 19 Host Enable HEN bit 6 19 Host Flag 0 HF0 bit 6 25 Host Flag 1 HF1 bit 6 25 Host Flag 2 HF2 bit 6 28 Host Flag 3 HF3 bit 6 28 Host Flags 0 1 HF bits 6 15 Host Flags 2 3 HF bits 6 14 Host GPIO Port Enable HGEN bit 6 20 Host Interface HI08 2 2 2 10 2 11 2 13 2 14 6 1 chip select logic 6 17 Command Vector Register CVR 6 8 6 23 Host Command HC 6 27 Host Vector HV 6 27 programming sheet B 24 con...

Page 312: ...host side Command Vector Register CVR 6 26 Interface Control Register ICR 6 24 Interface Status Register ISR 6 27 Interface Vector Register IVR 6 29 Receive Byte Registers RXH RXM RXL 6 30 Transmit Byte Registers TXH TXM TXL 6 30 host side registers after reset 6 31 Host Status Register HSR 6 13 6 15 6 33 Host Command Pending HCP 6 15 Host Flags 0 1 HF 6 15 Host Receive Data Full HRDF 6 16 Host Tr...

Page 313: ...2 2 enabling 6 9 single 2 2 Host Request HREQ bit 6 28 Host Request Enable HREN bit 6 20 host request line 6 4 Host Request Open Drain HROD bit 6 19 host request pins 6 10 Host Request Polarity HRP bit 6 18 Host Status Register HSR 6 13 6 15 6 33 Host Command Pending HCP 6 15 Host Flags 0 1 HF 6 15 Host Receive Data Full HRDF 6 16 Host Transmit Data Empty HTDE 6 15 Host Transmit HTX register 6 7 6...

Page 314: ...6 manual conventions 1 2 mapping control registers 5 2 MC68000 family 6 29 MC68681 DUART 8 16 memory allocation switching 3 2 configuration 3 5 dynamic switching 3 5 expansion 3 1 external expansion port 1 10 maps 3 7 on chip 1 9 Memory Expansion Port 1 5 memory map internal I O B 3 Memory Switch mode 3 2 X data Memory 3 3 X data memory 3 4 Memory Switch Mode MS bit 4 17 MODD MODC MODB and MODA 8 ...

Page 315: ...egister PCRC 7 36 programming sheet B 35 Port C Data Register PDRC 7 38 programming sheet B 35 Port C Direction Register PRRC 7 37 programming sheet B 35 Port D 2 2 control registers 7 36 ESSI1 5 8 Port D Control Register PCRD 7 36 programming sheet B 36 Port D Data Register PDRD 7 38 programming sheet B 36 Port D Direction Register PRRD 7 37 programming sheet B 36 Port E 2 19 5 9 Port E Control R...

Page 316: ...efinitions 8 12 Idle Line Interrupt Enable ILIE 8 13 programming sheet B 29 Receive with Exception Interrupt Enable REIE 8 12 Receiver Enable RE 8 14 Receiver Wakeup Enable RWU 8 15 SCI Clock Polarity SCKP 8 12 SCI Receive Interrupt Enable RIE 8 13 SCI Shift Direction SSFTD 8 15 SCI Transmit Interrupt Enable TIE 8 13 Send Break SBK 8 15 Timer Interrupt Enable TMIE 8 13 Timer Interrupt Rate STIR 8 ...

Page 317: ... Parity Error PE 8 17 Receive Data Register Full RDRF 8 18 Received Bit 8 R8 8 17 Transmit Data Register Empty TDRE 8 18 Transmitter Empty TRNE 8 18 SCI Transmit Data Address Register STXA 8 9 SCI Transmit Data Register STX 8 9 select wakeup on idle line mode 8 15 Serial Clock SCLK 8 4 8 21 state after reset 8 5 Synchronous mode 8 2 transmission priority preamble break and data 8 7 transmit and re...

Page 318: ... 17 Test Access Port TAP 1 5 1 9 Time Slot Register TSR 7 33 timer 2 2 2 20 after Reset 9 3 enabling 9 4 exception 9 4 Compare 9 4 Overflow 9 4 GPIO 5 9 initialization 9 3 operating modes 9 5 Capture mode 6 9 5 9 14 9 18 Event Counter mode 3 9 5 9 12 GPIO mode 0 9 5 9 6 Input Period mode 5 9 5 9 14 9 16 Input Width mode 4 9 5 9 14 overview 9 6 Pulse mode 1 9 5 9 8 Pulse Width Modulation PWM mode 7...

Page 319: ...0 Transmit Clock Source TDM bit 8 19 Transmit Data Empty TDE bit 6 7 Transmit Data Register Empty TDE bit 7 28 Transmit Data Register Empty TDRE bit 8 18 Transmit Data Register Empty TXDE bit 6 29 Transmit Data Registers TX0 TX2 7 14 7 33 Transmit Data Registers TXH TXM TXL 6 5 Transmit Data signal TXD 8 4 Transmit Enable TE bits 7 18 Transmit Exception Interrupt Enable TEIE bit 7 19 Transmit Fram...

Page 320: ...Index 14 DSP56303 User s Manual ...

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