Motorola DSP56009, User Manual

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Signal Descriptions
External Memory Interface (EMI)
MOTOROLA DSP56009 User’s Manual 2-7
2.5 EXTERNAL MEMORY INTERFACE (EMI)
PCAP Input Input PLL Filter Capacitor —This input is used to connect a
high-quality (high “Q” factor) external capacitor needed
for the PLL filter. The capacitor should be as close as
possible to the DSP with heavy, short traces connecting
one terminal of the capacitor to PCAP and the other
terminal to V
CCP
. The required capacitor value is
specified in the
DSP56009 Technical Data
sheets.
When short lock time is critical, low dielectric absorption
capacitors such as polystyrene, polypropylene, or teflon
are recommended.
If the PLL is not used (i.e., it remains disabled at all
times), there is no need to connect a capacitor to the
PCAP pin. It may remain unconnected, or be tied to
either V
cc
or GND.
PINIT Input Input PLL Initialization (PINIT) —During the assertion of
hardware reset, the value on the PINIT line is written into
the PEN bit of the PCTL register. When set, the PEN bit
enables the PLL by causing it to derive the internal clocks
from the PLL voltage controlled oscillator output. When
the bit is cleared, the PLL is disabled and the DSP’s
internal clocks are derived from the clock connected to
the EXTAL signal. After hardware RESET is deasserted,
the PINIT signal is ignored.
Table 2-5 External Memory Interface (EMI) Signals
Signal Name
Signal
Type
State
during
Reset
Signal Description
MA0–MA14 Output Table 2-6 Memory Address Lines 0–14 —MA0–MA10
provide the multiplexed row/column
addresses for DRAM accesses and MA0–MA14
provide the non-multiplexed address lines 0–14
for SRAM accesses.
Table 2-4 Clock and PLL Signals (Continued)
Signal
Name
Signal
Type
State
during
Reset
Signal Description