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Motorola DSP56009, User Manual

The Motorola DSP56009 is a powerful digital signal processor that offers exceptional performance and versatility. Unlock its full potential with the comprehensive User Manual, available for free download at manualshive.com. This manual provides detailed instructions, allowing you to maximize your experience with this highly advanced technology.

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Serial Host Interface

Serial Host Interface Programming Model

 

MOTOROLA

DSP56009 User’s Manual 

5-11

used in conjunction with the CPOL bit to select the desired clock-to-data relationship. 
The CPHA bit, in general, selects the clock edge that captures data and allows it to 
change states. It has its greatest impact on the first bit transmitted (MSB) in that it 
does or does not allow a clock transition before the data capture edge.

When in Slave mode and CPHA = 0, the SS line must be deasserted and asserted by 
the external master between each successive word transfer. SS must remain asserted 
between successive bytes within a word. The DSP core should write the next data 
word to HTX when HTDE = 1, clearing HTDE. However, the data will be transferred 
to the shift register for transmission only when SS is deasserted. HTDE is set when 
the data is transferred from HTX to the shift register.

When in Slave mode and CPHA = 1, the SS line may remain asserted between 
successive word transfers. The SS must remain asserted between successive bytes 
within a word. The DSP core should write the next data word to HTX when 
HTDE = 1, clearing HTDE. The HTX data will be transferred to the shift register for 
transmission as soon as the shift register is empty. HTDE is set when the data is 
transferred from HTX to the shift register. 

When in Master mode and CPHA = 0, the DSP core should write the next data word 
to HTX when HTDE = 1, clearing HTDE; the data is transferred immediately to the 
shift register for transmission. HTDE is set only at the end of the data word 
transmission. 

Note:

The master is responsible for deasserting and asserting the slave device SS line 
between word transmissions.

When in Master mode and CPHA = 1, the DSP core should write the next data word 
to HTX when HTDE = 1, clearing HTDE. The HTX data will be transferred to the shift 
register for transmission as soon as the shift register is empty. HTDE is set when the 
data is transferred from HTX to the shift register.

The clock phase and polarity should be identical for both the master and slave SPI 
devices. CPHA and CPOL are functional only when the SHI operates in the SPI 
mode, and are ignored in the I

2

C mode. The CPHA bit is set and the CPOL bit is 

cleared during hardware reset and software reset.

5.3.5.2

HCKR Prescaler Rate Select (HRS)—Bit 2

The HRS bit controls a prescaler in series with the clock generator divider. This bit is 
used to extend the range of the divider when slower clock rates are desired. When 

Summary of Contents for DSP56009

Page 1: ...DSP56009 24 Bit Digital Signal Processor User s Manual Motorola Incorporated Semiconductor Products Sector DSP Division 6501 William Cannon Drive West Austin TX 78735 8598 ...

Page 2: ... Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life Buyer agrees to no...

Page 3: ...ONS MEMORY OPERATING MODES AND INTERRUPTS EXTERNAL MEMORY INTERFACE SERIAL HOST INTERFACE SERIAL AUDIO INTERFACE GENERAL PURPOSE I O BOOTSTRAP CODE CONTENTS PROGRAMMING REFERENCE APPLICATION EXAMPLES INDEX 1 2 3 4 6 7 5 I A B C ...

Page 4: ...IONS MEMORY OPERATING MODES AND INTERRUPTS EXTERNAL MEMORY INTERFACE SERIAL HOST INTERFACE SERIAL AUDIO INTERFACE GENERAL PURPOSE I O BOOTSTRAP CODE CONTENTS PROGRAMMING SHEETS APPLICATION EXAMPLES INDEX 1 2 3 4 6 7 5 I A B C ...

Page 5: ... 1 3 2 3 Program Control Unit 1 12 1 3 2 4 Data Buses 1 12 1 3 2 5 Address Buses 1 12 1 3 2 6 Phase Lock Loop PLL 1 12 1 3 2 7 On Chip Emulation OnCE Port 1 13 1 3 3 Memories 1 13 1 3 3 1 Program Memory 1 13 1 3 3 2 X Data Memory 1 15 1 3 3 3 Y Data Memory 1 15 1 3 3 4 On Chip Memory Configuration Bits 1 15 1 3 3 5 Bootstrap ROM 1 15 1 3 3 6 External Memory 1 16 1 3 3 7 Reserved Memory Spaces 1 16...

Page 6: ...NTERRUPTS 3 1 3 1 INTRODUCTION 3 3 3 2 DSP56009 DATA AND PROGRAM MEMORY 3 3 3 2 1 X Data ROM 3 4 3 2 2 Y Data ROM 3 4 3 2 3 Program ROM 3 4 3 2 4 Bootstrap ROM 3 4 3 2 5 Reserved Memory Spaces 3 5 3 3 DSP56009 DATA AND PROGRAM MEMORY MAPS 3 5 3 3 1 Dynamic Switching of Memory Configurations 3 8 3 3 2 Internal I O Memory Map 3 9 3 4 OPERATING MODE REGISTER OMR 3 11 3 4 1 DSP Operating Mode MC MB MA...

Page 7: ...ad EINR Bit 7 4 16 4 2 7 5 EMI Increment EBAR After Write EINW Bit 8 4 16 4 2 7 6 EMI Interrupt Select EIS 1 0 Bits 9 10 4 17 4 2 7 7 EMI Memory Wrap Interrupt Enable EMWIE Bit 11 4 17 4 2 7 8 EMI Data Write Register Empty EDWE Bit 12 4 18 4 2 7 9 EMI Data Read Register Full EDRF Bit 13 4 18 4 2 7 10 EMI Data Register Buffer and Data Read Register Full EBDF Bit 14 4 18 4 2 7 11 EMI Busy EBSY Bit 1...

Page 8: ...ine Refresh 4 33 4 4 3 2 Off Line Refresh 4 34 4 4 4 Software Controlled Refresh 4 34 4 4 5 DRAM Refresh Timing 4 35 4 5 EMI OPERATING CONSIDERATIONS 4 38 4 5 1 EMI Triggering and Pipelining 4 38 4 5 2 Read Data Transfer 4 40 4 5 3 Write Data Transfer 4 43 4 5 4 EMI Operation During Stop 4 45 4 5 5 EMI Operation During Wait 4 45 4 6 DATA DELAY STRUCTURE 4 46 4 7 EMI TO MEMORY CONNECTION 4 48 4 8 E...

Page 9: ... 5 HCKR Filter Mode HFM 1 0 Bits 13 12 5 12 5 3 6 SHI Control Status Register HCSR DSP Side 5 13 5 3 6 1 HCSR Host Enable HEN Bit 0 5 13 5 3 6 2 HCSR I2C SPI Selection HI2C Bit 1 5 13 5 3 6 3 HCSR Serial Host Interface Mode HM 1 0 Bits 3 2 5 14 5 3 6 4 HCSR Reserved Bits Bits 23 18 16 and 4 5 14 5 3 6 5 HCSR FIFO Enable Control HFIFO Bit 5 5 14 5 3 6 6 HCSR Master Mode HMST Bit 6 5 14 5 3 6 7 HCSR...

Page 10: ...e Data in I2C Master Mode 5 29 5 6 4 2 Transmit Data In I2C Master Mode 5 30 5 6 5 SHI Operation During Stop 5 31 SECTION 6 SERIAL AUDIO INTERFACE 6 1 6 1 INTRODUCTION 6 3 6 2 SERIAL AUDIO INTERFACE INTERNAL ARCHITECTURE 6 4 6 2 1 Baud Rate Generator 6 4 6 2 2 Receive Section Overview 6 5 6 2 3 SAI Transmit Section Overview 6 6 6 3 SERIAL AUDIO INTERFACE PROGRAMMING MODEL 6 8 6 3 1 Baud Rate Contr...

Page 11: ... 17 6 3 4 2 TCS Transmitter 1 Enable T1EN Bit 1 6 17 6 3 4 3 TCS Transmitter 2 Enable T2EN Bit 2 6 18 6 3 4 4 TCS Transmitter Master TMST Bit 3 6 18 6 3 4 5 TCS Transmitter Word Length Control TWL 1 0 Bits 4 5 6 18 6 3 4 6 TCS Transmitter Data Shift Direction TDIR Bit 6 6 18 6 3 4 7 TCS Transmitter Left Right Selection TLRS Bit 7 6 19 6 3 4 8 TCS Transmitter Clock Polarity TCKP Bit 8 6 19 6 3 4 9 ...

Page 12: ...Bits GC 3 0 Bits 19 16 7 4 APPENDIX A BOOTSTRAP ROM CONTENTS A 1 A 1 INTRODUCTION A 3 A 2 BOOTSTRAPPING THE DSP A 3 A 3 BOOTSTRAP PROGRAM LISTING A 4 A 4 BOOTSTRAP FLOW CHART A 7 APPENDIX B PROGRAMMING REFERENCE B 1 B 1 INTRODUCTION B 3 B 2 PERIPHERAL ADDRESSES B 3 B 3 INTERRUPT ADDRESSES B 3 B 4 INTERRUPT PRIORITIES B 3 B 5 INSTRUCTION SET SUMMARY B 3 B 6 PROGRAMMING SHEETS B 3 APPENDIX C APPLICA...

Page 13: ...ure 3 7 PLL Configuration 3 18 Figure 4 1 EMI Registers 4 6 Figure 4 2 EMI Control Status Register ECSR 4 8 Figure 4 3 EMI Refresh Control Register ERCR 4 21 Figure 4 4 EMI Address Generation Block Diagram 4 23 Figure 4 5 Refresh Timer Functional Diagram 4 33 Figure 4 6 Timing Diagram of a DRAM Refresh Cycle Fast 4 37 Figure 4 7 Timing Diagram Of a DRAM Refresh Cycle Slow 4 37 Figure 4 8 EMI Pipel...

Page 14: ...Timing 1 4 58 Figure 4 20 Slow Read or Write DRAM Access Timing 2 4 59 Figure 4 21 Slow Read or Write DRAM Access Timing 3 4 60 Figure 4 22 Slow Read or Write DRAM Access Timing 4 4 61 Figure 4 23 Slow Read or Write DRAM Access Timing 5 4 62 Figure 4 24 Slow Read or Write DRAM Access Timing 6 4 63 Figure 4 25 SRAM Read Write Timing 4 64 Figure 5 1 Serial Host Interface Block Diagram 5 4 Figure 5 2...

Page 15: ...gure 6 6 Receiver Left Right Selection RLRS Programming 6 12 Figure 6 7 Receiver Clock Polarity RCKP Programming 6 13 Figure 6 8 Receiver Relative Timing RREL Programming 6 14 Figure 6 9 Receiver Data Word Truncation RDWT Programming 6 14 Figure 6 10 Transmitter Data Shift Direction TDIR Programming 6 19 Figure 6 11 Transmitter Left Right Selection TLRS Programming 6 19 Figure 6 12 Transmitter Clo...

Page 16: ... and PLL Signals 2 6 Table 2 5 External Memory Interface EMI Signals 2 7 Table 2 6 EMI Operating States 2 9 Table 2 7 Interrupt and Mode Control Signals 2 10 Table 2 8 Serial Host Interface SHI signals 2 14 Table 2 9 Serial Audio Interface SAI Receiver signals 2 18 Table 2 10 Serial Audio Interface SAI Transmitter signals 2 20 Table 2 11 General Purpose I O GPIO Signals 2 21 Table 2 12 On Chip Emu...

Page 17: ...t 4 17 Table 4 10 EMI DRAM Timing clock cycles per word transfer 4 19 Table 4 11 EMI SRAM Timing clock cycles per word transfer 4 20 Table 4 12 Relative Addressing Extension Bits 4 24 Table 4 13 Word Address to Physical Address Mapping for SRAM 4 26 Table 4 14 Word Address to Physical Address Mapping for DRAM 4 28 Table 4 15 Address Generation For DRAM Relative Addressing 4 29 Table 4 16 Word to P...

Page 18: ... Vectors 5 7 Table 5 2 SHI Internal Interrupt Priorities 5 7 Table 5 3 SHI Noise Reduction Filter Mode 5 12 Table 5 4 SHI Data Size 5 14 Table 5 5 HREQ Function In SHI Slave Modes 5 15 Table 5 6 HCSR Receive Interrupt Enable Bits 5 17 Table 6 1 SAI Interrupt Vector Locations 6 9 Table 6 2 SAI Internal Interrupt Priorities 6 9 Table 6 3 Receiver Word Length Control 6 11 Table 6 4 Transmitter Word L...

Page 19: ...MOTOROLA DSP56009 User s Manual 1 1 SECTION 1 OVERVIEW ...

Page 20: ...1 2 DSP56009 User s Manual MOTOROLA Overview 1 1 INTRODUCTION 1 3 1 2 DSP56009 FEATURES 1 6 1 3 DSP56009 ARCHITECTURAL OVERVIEW 1 8 ...

Page 21: ...ecause of its processing power and large memory capacity it supports a variety of digital audio decompression functions such as Dolby AC 3 Surround MPEG1 Layer 2 and Digital Theater Systems DTS The DSP56009 also provides the following on chip peripherals to support these audio functions External Memory Interface EMI interfaces DRAM SRAM and EPROM the DRAM interface is specifically designed to prov...

Page 22: ...nd its controls Section 5 Serial Host Interface describes the operation registers and control of the Serial Host Interface SHI Section 6 Serial Audio Interface describes the operation of the Serial Audio Interface SAI its registers and its controls Section 7 General Purpose I O describes the four dedicated General Purpose Input Output GPIO pins the GPIO registers and GPIO control Appendix A Bootst...

Page 23: ...ed as cleared its value is 0 Hex hexadecimal values are indicated with a dollar sign preceding the hex value as in FFFB is the X memory address for the Interrupt Priority Register IPR Code examples are displayed in a monospaced font as shown in Example 1 1 Pins or signals listed in code examples that are asserted low have a tilde in front of their names The word assert means that a high true activ...

Page 24: ... 4096 and power saving clock divider 2i where i 0 to 15 for reduced clock noise On Chip Emulation OnCE port for unobtrusive comprehensive processor speed independent hardware software debugging Stop and Wait low power standby modes Efficient object code compatible 24 bit 56000 family DSP engine Table 1 1 High True Low True Signal Conventions Signal Symbol Logic State Signal State Voltage PIN1 True...

Page 25: ...c Quad Flat Pack surface mount package 14 14 2 45 mm 0 65 mm lead pitch Highly parallel instruction set with unique DSP addressing modes Two 56 bit accumulators including extension byte Parallel 24 24 bit multiply accumulate in 1 instruction cycle 2 clock cycles Double precision 48 48 bit multiply with 96 bit result in 6 instruction cycles 56 bit addition subtraction in 1 instruction cycle Fractio...

Page 26: ...wo receivers and three transmitters master or slave capability and implementation of Philips Sony and Matsushita audio protocols two complete sets of SAI interrupt vectors Four independent programmable GPIO lines 1 3 DSP56009 ARCHITECTURAL OVERVIEW The DSP56009 is a member of the 24 bit DSP56000 family The DSP is composed of the 24 bit DSP56000 core memory and a set of peripheral modules as shown ...

Page 27: ...r 48 bit data words This is a significant advantage for audio over 16 bit and 32 bit architectures 16 bit DSP architectures have insufficient precision for CD quality sound and while 32 bit DSP architectures possess the necessary precision with extra silicon and cost overhead they are not suitable for high volume cost driven audio applications Figure 1 1 DSP56009 Block Diagram Y Data Memory X Data...

Page 28: ...Serial Peripheral Interface SPI bus and the Philips Inter Integrated circuit Control I2C bus The SHI will operate with 8 16 and 24 bit words and the receiver has an optimal 10 word FIFO register to reduce the receive interrupt rate Serial Audio Interface SAI The SAI provides a synchronous serial interface that allows the DSP56009 to communicate using a wide range of standard serial data formats us...

Page 29: ... data shifters are capable of shifting data one bit to the left or to the right as well as passing the data unshifted Each data shifter has a 24 bit output with overflow indication The data shifters are controlled by scaling mode bits These shifters permit no overhead dynamic scaling of fixed point data by simply programming the scaling mode bits This permits block floating point algorithms to be ...

Page 30: ...h as I O transfers to internal peripherals occur over the GDB Instruction word pre fetches take place over the PDB in parallel with data transfers Transfers between buses are accomplished through the internal bus switch 1 3 2 5 Address Buses Addresses are specified for internal X data memory and Y data memory using two unidirectional 16 bit buses the X Address Bus XAB and the Y Address Bus YAB pro...

Page 31: ...gic usually the Program Counter over the Program Address Bus PAB Program memory may be written using MOVEM instructions The interrupt vectors are located in the bottom 128 locations of program memory Table 1 2 lists the interrupt vector addresses and indicates the Interrupt Priority Level IPL of each interrupt source Program RAM has many advantages It provides a means to develop code efficiently P...

Page 32: ... P 0024 0 2 SHI Receive FIFO Not Empty P 0026 Reserved P 0028 0 2 SHI Receive FIFO Full P 002A 0 2 SHI Receive Overrun Error P 002C 0 2 SHI Bus Error P 002E Reserved P 0030 0 2 EMI Write Data P 0032 0 2 EMI Read Data P 0034 0 2 EMI EBAR0 Memory Wrap P 0036 0 2 EMI EBAR1 Memory Wrap P 0038 Reserved P 003A Reserved P 003C Reserved P 003E 3 Illegal Instruction P 0040 0 2 SAI Left Channel Transmitter ...

Page 33: ...0 31 0 1F and 256 287 100 11F in two areas in the memory map on the DSP56009 The bootstrap ROM is factory programmed to perform the bootstrap operation following hardware reset it either jumps to the user s ROM starting address P 2000 or downloads up to 512 words of user program from either the EMI port or the SHI port in SPI or I2C format The bootstrap ROM activity is controlled by the bits MA MB...

Page 34: ...pace and 2700 in Y memory space and values from the reserved area of program memory space return the value 000005 which is the opcode for the ILLEGAL instruction If a read access is performed from the reserved area below address 2000 in X or Y data memory the resulting data will be undetermined If an instruction fetch is attempted from addresses in the reserved area the value returned is 000005 wh...

Page 35: ...gister HSAR X FFF1 SHI Host Control Status Register HCSR X FFF0 SHI Host Clock Control Register HCKR X FFEF EMI Refresh Control Register ERCR X FFEE EMI Data Register 1 EDRR1 EDWR1 X FFED EMI Offset Register 1 EOR1 X FFEC EMI Base Address Register 1 EBAR1 X FFEB EMI Control Status Register ECSR X FFEA EMI Data Register 0 EDRR0 EDWR0 X FFE9 EMI Offset Register 0 EOR0 X FFE8 EMI Base Address Registe...

Page 36: ...12 16 20 or 24 bits may be stored and retrieved via the EMI with automatic packing and unpacking In addition the EMI may be selected to operate in the SRAM EPROM absolute addressing mode This allows connection to external memory devices for program bootstrap and data storage as well as general parallel access to peripheral devices 1 3 4 2 Serial Host Interface SHI The Serial Host Interface SHI pro...

Page 37: ...ntrolled by one transmitter controller This enables simultaneous data transmission to as many as three stereo audio devices or transmission of three separate stereo pairs of audio channels The receiver consists of two receivers and a single receive controller This enables simultaneous data reception from up to two stereo audio devices The transmit and receive sections are fully asynchronous and ma...

Page 38: ...1 20 DSP56009 User s Manual MOTOROLA Overview DSP56009 Architectural Overview ...

Page 39: ...MOTOROLA DSP56009 User s Manual 2 1 SECTION 2 SIGNAL DESCRIPTIONS ...

Page 40: ... 2 3 2 2 POWER 2 5 2 3 GROUND 2 5 2 4 CLOCK AND PLL SIGNALS 2 6 2 5 EXTERNAL MEMORY INTERFACE EMI 2 7 2 6 INTERRUPT AND MODE CONTROL 2 10 2 7 SERIAL HOST INTERFACE SHI 2 14 2 8 SERIAL AUDIO INTERFACE SAI 2 18 2 9 GENERAL PURPOSE I O 2 21 2 10 ON CHIP EMULATION OnCETM PORT 2 22 ...

Page 41: ... DSP56009 Functional Group Signal Allocations Functional Group Number of Signals Detailed Description Power VCC 9 Table 2 2 Ground GND 13 Table 2 3 Phase Lock Loop PLL 3 Table 2 4 External Memory Interface EMI 29 Table 2 5 and Table 2 6 Interrupt and Mode Control 4 Table 2 7 Serial Host Interface SHI 5 Table 2 8 Serial Audio Interface SAI 9 Table 2 9 and Table 2 10 General Purpose Input Output GPI...

Page 42: ... SCK SCL GNDS VCCS WSR SCKR SDI0 DSCK OS1 DSI OS0 DSO DR OnCE Port C Port B Port A External Memory Mode Interrupt 80 signals Serial Host Rec0 SDO1 Tran1 WST SCKT SDO0 Tran0 Interface MRD MCS0 Serial Audio Interface Interface MOSI HA0 SDO2 Tran2 SDI1 Rec1 GPIO0 GPIO3 GPIO HREQ VCCP GNDP PCAP PLL PINIT MA15 MCS3 EXTAL GNDA VCCA GNDD VCCD Reset AA0249G Port Power Inputs Ground Control 2 2 3 3 4 2 3 8...

Page 43: ...ut must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors VCCS Serial Interface Power VCCS provides isolated power for the SHI and SAI This input must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors Table 2 3 Grounds Ground Name Description GNDP PLL Ground GNDP is ground de...

Page 44: ...ser must provide adequate external decoupling capacitors GNDS Serial Interface Ground GNDS provides isolated ground for the SHI and SAI This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors Table 2 4 Clock and PLL Signals Signal Name Signal Type State during Reset Signal Description EXTAL Input Input External Cloc...

Page 45: ...ay remain unconnected or be tied to either Vcc or GND PINIT Input Input PLL Initialization PINIT During the assertion of hardware reset the value on the PINIT line is written into the PEN bit of the PCTL register When set the PEN bit enables the PLL by causing it to derive the internal clocks from the PLL voltage controlled oscillator output When the bit is cleared the PLL is disabled and the DSP ...

Page 46: ...1 for SRAM accesses This line also functions as the Memory Row Address Strobe during DRAM accesses MCS0 Output Table 2 6 Memory Chip Select 0 This line functions as memory chip select 0 for SRAM accesses MWR Output Table 2 6 Memory Write Strobe This line is asserted when writing to external memory MRD Output Table 2 6 Memory Read Strobe This line is asserted when reading external memory MD0 MD7 Bi...

Page 47: ... DRAM refresh enabled Driven High Driven High Driven High Driven High Driven High Driven High Driven High Driven High Previous State Driven High Driven High Driven Low Previous State Driven High Driven High Driven High MA17 MCS1 MRAS MA17 MCS1 MRAS DRAM refresh disabled DRAM refresh enabled Driven High Driven High Driven High Driven High Driven High Driven High Driven High Driven High Previous Sta...

Page 48: ...y latched in the DSP when the processor exits the Reset state The logic state present on the MODA MODB and MODC pins selects the initial DSP operating mode Several clock cycles after leaving the Reset state the MODA signal changes to the external interrupt request IRQA The DSP operating mode can be changed by software after reset External Interrupt Request A IRQA The IRQA input is a synchronized e...

Page 49: ... Reset state the MODB signal changes to the external interrupt request IRQB The DSP operating mode can be changed by software after reset External Interrupt Request B IRQB The IRQB input is a synchronized external interrupt request It may be programmed to be level sensitive or negative edge triggered When the signal is edge triggered triggering occurs at a voltage level and is not directly related...

Page 50: ...ck cycles after leaving the Reset state the MODC signal changes to the Non Maskable Interrupt request NMI The DSP operating mode can be changed by software after reset Non Maskable Interrupt Request The NMI input is a negative edge triggered external interrupt request This is a level 3 interrupt that can not be masked out Triggering occurs at a voltage level and is not directly related to the fall...

Page 51: ... the PINIT signal and writes its status into the PEN bit of the PLL Control Register When the DSP comes out of the Reset state deassertion occurs at a voltage level and is not directly related to the rise time of the RESET signal However the probability that noise on RESET will generate multiple resets increases with increasing rise time of the RESET signal For proper hardware reset to occur the c...

Page 52: ...synchronizes the data transfer The SCK signal is ignored by the SPI if it is defined as a slave and the Slave Select SS signal is not asserted In both the master and slave SPI devices data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable Edge polarity is determined by the SPI transfer protocol I2C Serial Clock SCL SCL carries the clock for bus trans...

Page 53: ...rain output when transmitting SDA should be connected to VCC through a pull up resistor SDA carries the data for I2C transactions The data in SDA must be stable during the high period of SCL The data in SDA is only allowed to change when SCL is low When the bus is free SDA is high The SDA line is only allowed to change during the time SCL is high in the case of Start and Stop events A high to low ...

Page 54: ...t no need for external pull up in this state SS HA2 Input Input Tri stated SPI Slave Select SS This signal is an active low Schmitt trigger input when configured for the SPI mode When configured for the SPI Slave mode this signal is used to enable the SPI slave for transfer When configured for the SPI Master mode this signal should be kept deasserted If it is asserted while configured as SPI maste...

Page 55: ... first clock pulse of the new data word transfer When configured for the Master mode HREQ is an input and when asserted by the external slave device it will trigger the start of the data word transfer by the master After finishing the data word transfer the master will await the next assertion of HREQ to proceed to the next transfer Note This signal is tri stated during hardware software individua...

Page 56: ...or while the DSP is in the Stop state SDI1 Input Tri stated Serial Data Input 1 While in the high impedance state the internal input buffer is disconnected from the pin and no external pull up is necessary SDI1 is the serial data input for receiver 1 Note This signal is high impedance during hardware or software reset while receiver 1 is disabled R1EN 0 or while the DSP is in the Stop state SCKR I...

Page 57: ...ize the data word and to select the left right portion of the data sample Note WSR is high impedance if all receivers are disabled individual reset during hardware reset during software reset or while the DSP is in the Stop state While in the high impedance state the internal input buffer is disconnected from the signal and no external pull up is necessary Table 2 9 Serial Audio Interface SAI Rece...

Page 58: ...gh Serial Data Output 2 SDO2 SDO2 is the serial output for transmitter 2 SDO2 is driven high if transmitter 2 is disabled during individual reset hardware reset and software reset or when the DSP is in the Stop state SCKT Input or Output Tri stated Serial Clock Transmit SCKT This signal provides the clock for the SAI SCKT can be an output if the transmit section is configured as a master or a Schm...

Page 59: ...nput buffer is disconnected from the pin and no external pull up is necessary Table 2 11 General Purpose I O GPIO Signals Signal Name Signal Type State during Reset Signal Description GPIO0 GPIO3 Standard Output Open drain Output or Input Disconnected GPIO lines can be used for control and handshake functions between the DSP and external circuitry Each GPIO line can be configured individually as d...

Page 60: ...ontroller The data received on the DSI signal will be recognized only when the DSP has entered the Debug mode of operation Data must have valid TTL logic levels before the serial clock falling edge Data is always shifted into the OnCE port Most Significant Bit MSB first Operating Status 0 OS0 When the DSP is not in the Debug mode the OS0 signal provides information about the DSP status if it is an...

Page 61: ... on the rising edge Operating Status 1 OS1 If the OS1 signal is an output and used in conjunction with the OS0 signal it provides information about the DSP status when the DSP is not in the Debug mode The debug serial clock frequency must be no greater than 1 8 of the processor clock frequency The signal is tri stated when it is changing from input to output Note If the OnCE port is in use an exte...

Page 62: ...d controller When the DSP enters the Debug mode the DSO line will be pulsed low to indicate that the OnCE port is waiting for commands After receiving a read command the DSO line will be pulsed low to indicate that the requested data is available and the OnCE port is ready to receive clock pulses in order to deliver the data After receiving a write command the DSO line will be pulsed low to indica...

Page 63: ...wledge pulse on DSO and then deasserting DR It may be necessary to reset the OnCE port controller in cases where synchronization between the OnCE port controller and external circuitry is lost Asserting DR when the DSP is in the Wait or the Stop mode and keeping it asserted until an acknowledge pulse in the DSP is produced puts the DSP into the Debug mode After receiving the acknowledge pulse DR m...

Page 64: ...2 26 DSP56009 User s Manual MOTOROLA Signal Descriptions On Chip Emulation OnCETM Port ...

Page 65: ...SECTION 3 MEMORY OPERATING MODES AND INTERRUPTS ...

Page 66: ...INTRODUCTION 3 3 3 2 DSP56009 DATA AND PROGRAM MEMORY 3 3 3 3 DSP56009 DATA AND PROGRAM MEMORY MAPS 3 5 3 4 OPERATING MODE REGISTER OMR 3 11 3 5 OPERATING MODES 3 12 3 6 INTERRUPT PRIORITY REGISTER 3 14 3 7 PHASE LOCK LOOP PLL CONFIGURATION 3 18 3 8 HARDWARE RESET OPERATION 3 19 ...

Page 67: ...emory configurations are possible to provide appropriate memory sizes for a variety of applications see Table 3 1 This section also includes details of the interrupt vectors and priorities and describes the effect of a hardware reset on the PLL Multiplication Factor MF 3 2 DSP56009 DATA AND PROGRAM MEMORY External memory cannot be accessed as a direct extension of the internal memory The internal ...

Page 68: ...trap ROM The bootstrap ROM occupies locations 0 31 0 1F and 256 287 100 11F in two areas in the bootstrap memory map The bootstrap ROM is factory programmed to perform the bootstrap operation following hardware reset It either jumps to the user s ROM starting address P 2000 or downloads up to 512 words of user program from an external Erasable Programmable ROM EPROM attached to the EMI port or fro...

Page 69: ...ceive operation The OnCE port is enabled by the bootstrap code The contents of the bootstrap ROM are provided in Appendix A 3 2 5 Reserved Memory Spaces The reserved memory spaces should not be accessed by the user They are reserved for future expansion Write operations to the reserved range are ignored Read operations from addresses in the reserved range return the value 000005 If an instruction ...

Page 70: ...1100 2000 2700 FFFF 11FF 1FFF 2BFF FFBF 10FF 1FFF 26FF Program Internal ROM Reserved FFFF 4800 0000 47FF Reserved Internal RAM 01FF 0200 1FFF 2000 AA0287 X Data Internal RAM Y Data Internal ROM Internal I O Reserved Reserved Reserved Reserved Internal ROM Internal RAM FFFF FFC0 2C00 2000 1200 0000 0000 1100 2000 2700 FFFF 11FF 1FFF 2BFF FFBF 10FF 1FFF 26FF Program Internal ROM Reserved FFFF 4800 0...

Page 71: ...al RAM FFFF FFC0 2C00 2000 0000 0000 0E00 2000 2700 FFFF 1FFF 2BFF FFBF 0DFF 1FFF 26FF Program Internal ROM Reserved FFFF 4800 0000 47FF Reserved 0EFF 0F00 0800 07FF Internal RAM 2000 1FFF AA0289 X Data Internal RAM Y Data Internal ROM Internal I O Reserved Reserved Reserved Reserved Internal ROM Internal RAM FFFF FFC0 2C00 2000 0000 0000 0E00 2000 2700 FFFF 1FFF 2BFF FFBF 0DFF 1FFF 26FF Program I...

Page 72: ...ifies PEA PEB bits Any sequence that complies with the switch conditions is valid For example if the program flow executes in the address range that is not affected by the switch other than P 0200 0AFF the switch conditions can be met very easily In this case a switch can be accomplished by just changing PEA PEB bits in OMR in the regular program flow assuming no accesses to X 0C00 11FF or Y 0E00 ...

Page 73: ...ctions can be replaced by one two word instruction ANDI F3 OMR Clear PEA PEB bit in OMR ANDI FC MR Allow a delay for remapping meanwhile re enable interrupts JMP Next_Address 2 word long jump instruction uninterruptable Note Next_Address is any valid program address in the new memory configuration after the switch The 2 word instruction JMP Next_Address can be replaced by a sequence of an NOP foll...

Page 74: ...ss Register HSAR X FFF1 SHI Host Control Status Register HCSR X FFF0 SHI Host Clock Control Register HCKR X FFEF EMI Refresh Control Register ERCR X FFEE EMI Data Register 1 EDRR1 EDWR1 X FFED EMI Offset Register 1 EOR1 X FFEC EMI Base Address Register 1 EBAR1 X FFEB EMI Control Status Register ECSR X FFEA EMI Data Register 0 EDRR0 EDWR0 X FFE9 EMI Offset Register 0 EOR0 X FFE8 EMI Base Address Re...

Page 75: ...ves the reset state MC MB and MA can be changed under software control 3 4 2 Program RAM Enable A PEA Bit 2 The Program RAM Enable A PEA bit is used to map 768 words of the internal X data memory into internal Program RAM When PEA is set 768 words of X data RAM locations 0C00 0EFF are mapped into the program memory space locations 0800 0AFF The internal memory maps as controlled by the PEA bit X F...

Page 76: ...set SD 1 the delay before continuation of the STOP instruction cycle is set as eight clock cycles 16 T states When the DSP is driven by a stable external clock source setting the SD bit before executing the STOP instruction will allow a faster start up of the DSP 3 5 OPERATING MODES The DSP56009 operating modes are defined as described below and summarized in Table 3 3 on page 3 13 The operating m...

Page 77: ...ode 4 Reserved Mode 5 In this mode the bootstrap ROM is enabled and the bootstrap program is executed after hardware reset The internal Program RAM is loaded with up to 512 words from the Serial Host Interface SHI The SHI operates in the SPI Slave mode with 24 bit word width Mode 5 bootstrap terminates by setting the operating mode to 0 and jumping to the reset vector at address 0000 Mode 6 Reserv...

Page 78: ...ation is shown in Figure 3 6 Bits 0 5 of the IPR are used by the DSP56000 core for two of the external interrupt request inputs IRQA IAL 2 0 and IRQB IBL 2 0 Assuming the same IPL IRQA has higher priority than IRQB Bits 6 9 and 16 23 are reserved for future use Bits 10 15 are available for determining IPLs for each peripheral EMI SHI SAI Two IPL bits are required for each peripheral interrupt grou...

Page 79: ...k Error Trace SWI Levels 0 1 2 Maskable Highest Lowest IRQA IRQB SAI Receiver Exception SAI Transmitter Exception SAI Left Channel Receiver SAI Left Channel Transmitter SAI Right Channel Receiver SAI Right Channel Transmitter SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty EMI EBAR0 Memory Wrap EMI EBAR1 Memory ...

Page 80: ...el Transmitter if TXIL 0 P 0014 SAI Transmitter Exception if TXIL 0 P 0016 SAI Left Channel Receiver if RXIL 0 P 0018 SAI Right Channel Receiver if RXIL 0 P 001A SAI Receiver Exception if RXIL 0 P 001C Reserved P 001E NMI P 0020 SHI Transmit Data P 0022 SHI Transmit Underrun Error P 0024 SHI Receive FIFO Not Empty P 0026 Reserved P 0028 SHI Receive FIFO Full P 002A SHI Receive Overrun Error P 002C...

Page 81: ...0 SAI Left Channel Transmitter if TXIL 1 P 0042 SAI Right Channel Transmitter if TXIL 1 P 0044 SAI Transmitter Exception if TXIL 1 P 0046 SAI Left Channel Receiver if RXIL 1 P 0048 SAI Right Channel Receiver if RXIL 1 P 004A SAI Receiver Exception if RXIL 1 P 004C Reserved P 007E Reserved Table 3 5 Interrupt Vectors Continued Address Interrupt Source ...

Page 82: ...LPD and then used as the internal DSP clock if CSRC is cleared The DSP56009 PLL multiplication factor is set to 3 during hardware reset which means that the Multiplication Factor bits MF 11 0 in the PCTL are set to 002 The PLL may be disabled PEN 0 upon reset by pulling the PINIT pin low The DSP will subsequently operate at the frequency of the clock applied to the EXTAL pin until the PEN bit is s...

Page 83: ...ty Register IPR clears the Stack Pointer SP clears the Scaling mode S 1 0 Trace mode T Loop Flag LF Double precision Multiply mode DM and Condition Code Register CCR bits in the Status Register SR and sets the Interrupt mask I 1 0 bits and clears the Stop Delay SD bit and the Program RAM Enable PEA and PEB bits in the OMR The DSP remains in the Reset state until the RESET pin is deasserted When th...

Page 84: ...3 20 DSP56009 User s Manual MOTOROLA Memory Operating Modes and Interrupts Hardware Reset Operation ...

Page 85: ...MOTOROLA DSP56009 User s Manual 4 1 SECTION 4 EXTERNAL MEMORY INTERFACE ...

Page 86: ...l Memory Interface 4 1 INTRODUCTION 4 3 4 2 EMI PROGRAMMING MODEL 4 5 4 3 EMI ADDRESS GENERATION 4 23 4 4 DRAM REFRESH 4 31 4 5 EMI OPERATING CONSIDERATIONS 4 38 4 6 DATA DELAY STRUCTURE 4 46 4 7 EMI TO MEMORY CONNECTION 4 48 4 8 EMI TIMING 4 50 ...

Page 87: ...y devices for program bootstrap and data storage as well as general parallel access to external memory mapped peripheral devices 4 1 1 Theory of Operation The DSP views the EMI as a memory mapped peripheral The EMI functions as a memory mapped peripheral in which data transfers are performed by moving data to from data registers and control is exercised by polling status flags in the control statu...

Page 88: ...r 8 bits wide Data words can be 8 12 16 20 or 24 bits long Automatic data pack unpack to fit and orient external bus width and external word length to internal 24 bit word format Programmable timing features Independently selectable timing for SRAM or DRAM Automatic DRAM refresh by internal refresh timer Two timing modes for DRAM sixteen timing modes for SRAM Address Features Relative Addressing f...

Page 89: ... sections The interrupt vector table for the EMI is shown in Table 4 1 The interrupts generated by the EMI are prioritized as shown in Table 4 2 Since either a read condition or a write condition but not both can trigger an interrupt the read data and write data interrupts share the same level of priority Table 4 1 EMI Interrupt Vector Address Interrupt Source P 0030 EMI Write Data P 0032 EMI Read...

Page 90: ...gister ECSR 0 23 X FFEB To EMI Data Bus Base Address Register 0 EBAR0 0 23 X FFE8 Data Read Register EDRR 0 23 EDRR0 X FFEA Data Register Buffer EDRB 0 23 Refresh Control Register ERCR 0 23 X FFEF Base Address Register 1 EBAR1 0 23 X FFEC Offset Register EOR 0 23 Data Write Register EDWR 0 23 EDWR1 X FFEE EDRR1 X FFEE EDWR0 X FFEA Write Offset Register EWOR 0 23 X FFF6 ...

Page 91: ... memory access The increment operates on all 24 bits of EBARx The base address is stored in 24 bit unsigned integer format 4 2 2 EMI Write Offset Register EWOR The read write 24 bit EMI Write Offset Register EWOR is used by the EMI to calculate the address in external memory of the word to be accessed during write operations The address is formed by subtracting the contents of the EWOR from the co...

Page 92: ...Trigger Select ERTS bit see Figure 4 2 is cleared writing to EOR0 triggers an EMI memory read operation that will use the value in the EOR and the value in the EBAR0 for address calculation Writing to EOR1 when the ERTS bit is cleared triggers an EMI memory read operation that will use the values in the EOR and the EBAR1 for address calculation The EOR is cleared by hardware reset and software res...

Page 93: ...at the end of a memory read if the EDRR is empty All transfers to from the EDRR are 24 bit transfers Reading EDRR0 FFEA when the ERTS bit in the ECSR is set triggers an EMI memory read operation that will use EBAR0 and EOR to generate the word address Reading EDRR1 when the ERTS bit in the ECSR is set triggers an EMI memory read operation that will use EBAR1 and EOR to generate the word address Se...

Page 94: ...trol bits are changed while the EMI is busy with the exception of the ECSR interrupt controls EMWIE EIS 1 0 and the read trigger select ERTS improper operation can result 4 2 7 1 EMI Data Bus Width EBW Bit 0 The read write control bit EMI Data Bus Width EBW defines the width of the EMI data bus When EBW is cleared EBW 0 the data bus is 4 bits wide When EBW is set EBW 1 the data bus is 8 bits wide ...

Page 95: ...2 2 2 Relative 8 16 2 2 Relative 8 20 4 3 Relative 8 24 4 3 Relative 8 16 Data 24 Address 4 2 Absolute 4 8 2 2 Absolute 4 12 3 3 Absolute 4 16 4 4 Absolute 4 20 5 5 Absolute 4 24 6 6 Absolute 4 16 Data 24 Address 4 4 Absolute 8 8 1 1 Absolute 8 12 2 2 Absolute 8 16 2 2 Absolute 8 20 3 3 Absolute 8 24 3 3 Absolute 8 16 Data 24 Address 2 2 Table 4 4 EMI Word Length EWL2 EWL1 EWL0 Word Length 0 0 0 8...

Page 96: ...ord 0 1 1 16 bit data word 24 bit data addressing 1 0 0 Reserved 1 0 1 12 bit data word 1 1 0 20 bit data word 1 1 1 Reserved Table 4 5 EMI Addressing Modes EAM 3 0 Type Addressing Address Lines Chip Select RAS CAS Address Range 00001 2 SRAM Absolute MA 14 0 None Refresh only 32 K 0001 SRAM Relative MA 17 0 MCS0 n a 256 K 0010 SRAM Relative MA 16 0 MCS 1 0 n a 256 K 0011 SRAM Relative MA 14 0 MCS ...

Page 97: ...des 11012 DRAM Absolute MA 8 0 na yes 256 K 11102 DRAM Absolute MA 9 0 na yes 1 M 11112 DRAM Absolute MA 10 0 na yes 4 M Note 1 In this mode MCS0 and MA15 are held high MRAS and MCAS if enabled are active only during DRAM refresh cycles Devices to be addressed using this mode should be enabled with some hardware external to the EMI such as a GPIO pin 2 In the Absolute Addressing modes if post incr...

Page 98: ...4 K 0011 8 20 or 24 32 K Table 4 7 EMI Maximum DRAM Size Relative Addressing EAM 3 0 Bus Width Word Length DRAM devices Number of Words 0100 4 8 64 K 4 32 K 0100 4 12 or 16 64 K 4 16 K 0100 4 20 or 24 64 K 4 8 K 0100 8 8 2 64 K 4 64 K 0100 8 12 or 16 2 64 K 4 32 K 0100 8 20 or 24 2 64 K 4 16 K 0101 4 8 256 K 4 128 K 0101 4 12 or 16 256 K 4 64 K 0101 4 20 or 24 256 K 4 32 K 0101 8 8 2 256 K 4 256 K...

Page 99: ...12 or 16 2 4 M 4 2 M 0111 8 20 or 24 2 4 M 4 1 M Table 4 8 EMI Maximum DRAM Size Absolute Addressing EAM 3 0 Bus Width Word Length DRAM devices Number of Words 1100 4 8 64 K 4 32 K 1100 4 12 64 K 4 21 845 1100 4 16 64 K 4 16 K 1100 4 20 64 K 4 13 107 1100 4 24 64 K 4 10 922 1100 8 8 2 64 K 4 64 K 1100 8 12 or 16 2 64 K 4 32 K 1100 8 20 or 24 2 64 K 4 21 845 1101 4 8 256 K 4 128 K 1101 4 12 256 K 4...

Page 100: ...Write EINW Bit 8 The read write control bit EMI Increment EBAR after Write EINW enables the function of incrementing the contents of the relevant EBARx after a write operation 1101 4 24 256 K 4 43 690 1101 8 8 2 256 K 4 256 K 1101 8 12 or 16 2 256 K 4 128 K 1101 8 20 or 24 2 256 K 4 87 381 1110 4 8 1 M 4 512 K 1110 4 12 1 M 4 349 525 1110 4 16 1 M 4 256 K 1110 4 20 1 M 4 209 715 1110 4 24 1 M 4 17...

Page 101: ...tware reset Note Clearing EIS 1 0 will mask pending EMI interrupts but after a one instruction cycle delay If EIS 1 0 are cleared in a long interrupt service routine it is recommended that at least one other instruction should separate the instruction that clears EIS 1 0 and the RTI instruction at the end of the interrupt service routine 4 2 7 7 EMI Memory Wrap Interrupt Enable EMWIE Bit 11 The re...

Page 102: ... Bit 12 The EMI Data Write Register Empty EDWE read only status bit indicates the state of the EDWR EDWE is set EDWR empty by the EMI controller when transferring a data word from the EDWR to the EDBR during a memory write operation EDWE is cleared EDWR full when data is written into the EDWR when starting a memory write operation Note EDWE is set by hardware reset software reset individual reset ...

Page 103: ...ggered by reading the EDRR Note ERTS is cleared by hardware reset and software reset 4 2 7 13 EMI DRAM Memory Timing EDTM Bit 18 The read write EMI DRAM Memory Timing EDTM control bit selects the EMI DRAM Timing mode of operation When EDTM is set EMI DRAM mode accesses and DRAM refresh cycles operate in the Slow Timing mode When EDTM is cleared EMI DRAM mode accesses and DRAM refresh cycles operat...

Page 104: ... and software reset Absolute 12 4 3 12 36 3 8 24 Absolute 16 4 4 12 48 4 8 32 Absolute 12 or 16 8 2 12 24 2 8 16 Absolute 20 4 5 12 60 5 8 40 Absolute 24 4 6 12 72 6 8 48 Absolute 20 or 24 8 3 12 36 3 8 24 Refresh Cycle 13 9 Table 4 11 EMI SRAM Timing clock cycles per word transfer Word Length Bus Width Clock Cycles 8 4 2 4 ESTM 8 8 1 4 ESTM 12 4 3 4 ESTM 16 4 4 4 ESTM 12 or 16 8 2 4 ESTM 20 4 5 4...

Page 105: ...ring EME DRAM refresh operation if previously enabled will continue while the EMI is in the individual reset state Note EME is cleared by hardware reset and software reset 4 2 8 EMI Refresh Control Register ERCR The EMI Refresh Control Register ERCR is a 24 bit read write register used to control the refresh of DRAM memories Refresh can only occur while the EMI is set to work with DRAM memories EA...

Page 106: ...ith the refresh clock divider When EPS 1 0 10 the prescaler is bypassed EPS 1 0 11 is reserved for future expansion Note The EPS 1 0 bits are cleared by hardware reset and software reset 4 2 8 4 EMI One Shot Refresh EOSR Bit 20 The read write EMI One Shot Refresh EOSR bit is used to trigger one DRAM refresh cycle under software control When EOSR is set one Column Address Strobe CAS before Row Addr...

Page 107: ...done by the EMI in the Address Generation Unit AGU A block diagram of the AGU is shown in Figure 4 4 The AGU forms a word address for a read operation by subtracting the contents of the EOR from the contents of the appropriate EBAR For a write operation the word address is formed by subtracting the contents of the EWOR from the contents of the appropriate EBAR The word address must then be transfo...

Page 108: ...A15 and MCS0 are held high If more than one physical address must be accessed to complete the word transfer EBARx must be post incremented by one after each physical address access otherwise the same physical address will be accessed more than once In this case it is required that the appropriate control bit be set in the ECSR EINR for reads EINW for writes The EMI will execute the series of acces...

Page 109: ...ed in the ERCR 4 3 2 SRAM Relative Addressing The SRAM Relative Addressing modes EAM 3 0 0001 0010 0011 are used to implement data delay buffers in SRAM In this addressing mode the physical addresses required are formed by taking some LSBs of the calculated word address and appending from 0 to 3 extension bits to the right of the word address forming the LSBs of the physical address The extension ...

Page 110: ...h A 14 0 0001 1 256 K 000 0 Low A16 A15 A14 A 13 0 C0 1 Low A17 A16 A15 A 14 0 X01 0 Low A15 A14 A13 A 12 0 C0 C1 1 Low A16 A15 A14 A 13 0 C0 X1X 0 Low A14 A13 A12 A 11 0 C0 C1 C2 1 Low A15 A14 A13 A 12 0 C0 C1 0010 2 128 K 000 0 MCS0 C0 MCS1 C0 A16 A15 A 14 0 1 MCS0 A0 MCS1 A0 A17 A16 A 15 1 X01 0 MCS0 C1 MCS1 C1 A15 A14 A 13 0 C0 1 MCS0 C0 MCS1 C0 A16 A15 A 14 0 X1X 0 MCS0 C2 MCS1 C2 A14 A13 A 1...

Page 111: ...he number of rows in the DRAM The column addresses are generated by taking the remaining bits of the word address and appending from 0 to 3 extension bits to the right forming the LSBs of the column addresses The extension bits are then used to generate the number of column addresses required Address pins that are not required are kept at the 0011 4 32 K 000 0 A 15 1 1 A 16 2 X01 0 A 14 0 1 A 15 1...

Page 112: ... C1 C2 C 1 0 0 0 A13 A 12 9 A8 C0 C1 101 256 K R 00 0 0 0 A8 A7 A 6 3 A2 A1 A0 C 0 0 A16 A15 A 14 11 A10 A9 C0 C 1 0 0 A17 A16 A 15 12 A11 A10 A9 C 01 0 0 0 A15 A14 A 13 10 A9 C0 C1 C 1 0 0 A16 A15 A 14 11 A10 A9 C0 C 1X 0 0 0 A14 A13 A 12 9 C0 C1 C2 C 1 0 0 A15 A14 A 13 10 A9 C0 C1 110 1 M R 00 0 0 A9 A8 A7 A 6 3 A2 A1 A0 C 0 A18 A17 A16 A 15 12 A11 A10 C0 C 1 0 A19 A18 A17 A 16 13 A12 A11 A10 C ...

Page 113: ...C0 C 1 0 0 A17 A16 A 15 12 A11 A10 A9 C X01 0 0 0 A15 A14 A 13 10 A9 C0 C1 C 1 0 0 A16 A15 A 14 11 A10 A9 C0 C X1X 0 0 0 A14 A13 A 12 9 C0 C1 C2 C 1 0 0 A15 A14 A 13 10 A9 C0 C1 0110 1 M R 0 A9 A8 A7 A 6 3 A2 A1 A0 C 000 0 0 A18 A17 A16 A 15 12 A11 A10 C0 C 1 0 A19 A18 A17 A 16 13 A12 A11 A10 C X01 0 0 A17 A16 A15 A 14 11 A10 C0 C1 C 1 0 A18 A17 A16 A 15 12 A11 A10 C0 C X1X 0 0 A16 A15 A14 A 13 10...

Page 114: ...d address A 21 0 into the MA 10 0 address pins The row address is formed by the least significant part A 10 0 and the column address is formed by the remaining bits of the word address A 21 11 If more than one physical address must be accessed to complete the word transfer EBARx must be post incremented by one after each physical address access otherwise the same physical address will be accessed ...

Page 115: ...h the refresh is achieved has a major influence on the EMI real time performance and on the EMI channel bandwidth 4 4 1 DRAM Refresh Without Using The Internal Refresh Timer It is possible to refresh the DRAM by data access itself if a sufficient number of accesses are performed in the required refresh time and all rows are accessed This however must be assured The EMI address translation is perfo...

Page 116: ...R see Section 4 2 8 EMI Refresh Control Register ERCR Refresh cycles will then be initiated by the internal refresh timer according to the ERCR setting Example 4 1 Refresh Cycle Assume that A 44 1 KHz audio sampling frequency is used and the main code loops once every sample period The external memory has 512 rows 256 K 4 or 8 and needs to refresh all of its rows every 8 ms Two data delay buffers ...

Page 117: ...e The selected refresh cycle rate must take into account the DSP clock frequency and the DRAM device refresh requirements The refresh timer block diagram is illustrated in Figure 4 5 The DSP clock is first divided by a factor ranging between 1 and 256 according to the ECD bits in ERCR and then by 1 8 or 64 using a prescaler selected by bits EPS 1 0 to achieve the required refresh rate 4 4 3 1 On L...

Page 118: ...not affect the internal refresh timer No special consideration is necessary when using the on line refresh method If using the off line refresh method however the execution can stop when the refresh timer is off and data stored in the DRAM can be lost In order to avoid this situation the user should set the ERCR ERED bit and refresh cycles will be initiated by the internal refresh timer according ...

Page 119: ...rescaler value 1 8 or 64 If the refresh cycles are to be executed in a single burst it is possible to program the refresh timer for the highest refresh request rate possible Table 4 18 shows the timings and bit settings for continuous refresh cycles cross referenced with appropriate clock frequencies Note For the continuous method the DRAMs require a certain time between the refresh of each row Th...

Page 120: ...15 6 µs 124 8 µs 01 00 96 96 15 52 µs 124 2 µs 66 MHz 15 6 µs 124 8 µs 01 00 127 127 15 52 µs 124 2 µs 81 MHz 15 6 µs 124 8 µs 01 00 157 157 15 6 µs 124 8 µs Note Timer resolution is for a prescaling of 8 The refresh timer initiates a refresh request every ECD set 1 prescale Table 4 19 Burst Refresh Timings And Settings For EPS 1 0 And ECD 7 0 DSP Clock Frequency Fast Timing Mode Slow Timing Mode ...

Page 121: ...ates a refresh request every ECD set 1 prescale Figure 4 6 Timing Diagram of a DRAM Refresh Cycle Fast Figure 4 7 Timing Diagram Of a DRAM Refresh Cycle Slow CLK MRAS MCAS During a Refresh Cycle MCSx MRD and MWR are deasserted high data lines remain high impedance and address lines remain unchanged 2 3 4 5 6 7 8 9 1 1 AA0298k 2 CLK MRAS MCAS During a Refresh Cycle MCSx MRD and MWR are deasserted h...

Page 122: ...s the highest priority Write and read transfers have the same priority and are serviced according to the arrival order When the EMI is idle two consecutive operations can be triggered without the need to check status bits for any combination of read and write triggers As long as a trigger is pending any additional trigger will override and replace the pending one For better reference to the DSP co...

Page 123: ...DRAM mode at the last Icyc of the external access Slow DRAM mode at the Icyc after the last Icyc of the external access Special consideration should be given when triggering a new access after two read accesses since the EMI Data Register Buffer EDRB can be full if the EMI Data Read Register EDRR is also full In this case the new trigger will remain pending and the new access will not take place u...

Page 124: ...ing the offset stored in the EOR from the base address stored in one of the EBARx After obtaining the word address it is transformed into one or more physical addresses for the actual read accesses A data word read can require one two three four or six memory accesses as specified by the bits EWL 1 0 and EBW The nibbles or bytes read are held in the EDRB until the whole word is formed After comple...

Page 125: ...This procedure utilizes the pipeline property for better performance movep RAM X ECSR define memory access mode movep BAR0 X EBAR0 define base address movep OFF_1 X EOR0 trigger first memory read transfer using EBAR0 movep OFF_2 X EOR0 initiate the second read transfer pipelined this will be pending until the previous transfer terminates perform other operations or poll EDRF for EDRR full or wait ...

Page 126: ... EOR0 initiate the second read transfer pipelined typically OFF_1 OFF_2 bset ERTS X ECSR change trigger mode set ERTS 1 perform other operations or poll EDRF for EDRR full or wait a sufficient number of Icyc and then movep X EDRR0 X0 read the data triggered by writing OFF_1 perform other operations or poll EDRF for EDRR full or wait a sufficient number of Icyc and then movep X EDRR0 X0 read the da...

Page 127: ... can be stored in EDWR triggering a pending pipelined write operation A pending write operation will proceed as soon as the EDRB is empty permitting the transfer of the contents of EDWR to the buffer The DSP programmer can interrogate the EDWE status bit or optionally the write interrupt can be generated when EDWE is set Alternatively the DSP programmer can choose to write to EDWR after a minimum ...

Page 128: ...e same physical addresses will be written movep RAM X ECSR define the memory transfer mode movep OFF X EWOR store address offset to be used movep BAR0 X EBAR0 store base address movep DATA_1 X EDWR0 trigger first memory write transfer movep DATA_2 X EDWR0 trigger the second write transfer pipelined this will be pending until the previous transfer terminates perform other operations or poll EDWE fo...

Page 129: ...core after the device exits the Wait state No control or status bits in the ECSR and ERCR are affected by the Wait state Example 4 5 Block Transfer from Internal to External Memory The following procedure performs a block data transfer of N words N 1 from internal DSP memory to external memory without checking status flags or using interrupts Using this method it is necessary to know how much time...

Page 130: ...by means of windows that move over all the memory address range The base address points to the latest stored newest data sample and offset values are subtracted from the base address to generate addresses that point to delayed data samples The amount of the delay is defined by the offset value Normally the base address of each data delay buffer is incremented every time a new data sample is stored...

Page 131: ... value To summarize the data delay buffer is normally handled in the steady state after initialization and buffer filling stage as follows Upon receiving a new data sample the data sample is temporarily saved in an internal memory location It might be used in many audio algorithms as the most recent data sample Any number of random delayed samples are read from the specific buffer in the external ...

Page 132: ...c memory device if one of the GPIO pins or another external source is used as device select for the device and if the device is accessed using the Absolute Addressing mode The Absolute Addressing mode is useful for program bootstrap or overlays Figure 4 10 shows how to connect two 256 K 4 DRAM devices for the data buffers and an SRAM for program bootstrap or overlays Figure 4 10 DRAM for Data Dela...

Page 133: ...an 256 K 8 physical locations it is possible to use the DRAM Addressing modes with a large array of SRAM devices An external latch must be used to demultiplex the row and column addresses and in this way to obtain the SRAM address Figure 4 11 SRAM for Data Delay Buffers and for Bootstrap MA 14 0 MD 7 0 A 14 0 DQ 7 0 SRAM MCM60256A E W G GPIO3 SRAM Relative Addressing Absolute Addressing MWR MRD MC...

Page 134: ...requencies while using typical DRAM devices Figure 4 12 Replacing DRAMs with SRAMs for Large Arrays Table 4 20 Maximum DSP Clock Frequencies When Using DRAM DRAM Max Freq EDTM MCM54400A 60 ns 66 MHz 81 MHz 0 1 MCM54400A 70 ns 50 MHz 81 MHz 0 1 MA 14 0 MD 7 0 D 9 0 CLK A 18 0 DQ 7 0 IDTMP4008S W G CS DRAM Relative Addressing MRAS MRD MCAS D FF IDT74FCT821A MWR MA 9 0 Q 9 0 DSP EMI AA0262k ...

Page 135: ...ming Diagrams for DRAM Addressing Modes When operating in the DRAM modes the timing is defined by the ECSR EDTM bit The timing is classified as Fast EDTM 0 or Slow EDTM 1 Table 4 21 Maximum DSP Clock Frequencies When Using SRAM SRAM Max Freq ESTM 3 0 MCM6226 25 ns 81 MHz 0000 MCM6206 35 ns 66 MHz 0000 Table 4 22 Maximum DSP Clock Frequencies When Using EPROM EPROM Max Freq ESTM 3 0 WS57C256 35 ns ...

Page 136: ...rectly below Data accesses are left justified such that the 8 bit word is read from and written into the upper most byte of the 24 bit word bits 23 16 Figure 4 13 Fast Read or Write DRAM Access Timing 1 8 bit word 8 bit bus Relative Addressing or each physical access in the Absolute Addressing modes Set up row address 1 2 3 R W Bits 23 16 4 5 6 Finish last R W cycle 7 8 Start new memory cycle 1 2 ...

Page 137: ...d is read from and written into the upper most two bytes of the 24 bit word bits 23 8 Data is transferred one byte at a time for 16 bit words or four bits at time for 8 bit words Figure 4 14 Fast Read or Write DRAM Access Timing 2 16 bit word 8 bit bus or 8 bit word 4 bit bus Relative Addressing Set up row address 1 2 3 R W Bits 23 16 23 20 4 5 6 R W Bits 15 8 19 16 7 8 9 Finish last R W cycle 10 ...

Page 138: ... that the 16 bit word is read from and written into the upper most two bytes of the 24 bit word bits 23 8 Figure 4 15 Fast Read or Write DRAM Access Timing 3 16 bit word 4 bit bus Relative Addressing Set up row address 1 2 3 R W Bits 23 16 4 5 6 R W Bits 19 16 7 8 9 R W Bits 15 12 10 11 12 R W Bits 11 8 13 14 15 Finish last R W cycle 16 17 New memory cycle 1 2 Last Column Address Column Address Ro...

Page 139: ... 12 bit word is read from and written into the upper most 20 24 or 12 bits of the 24 bit word Data is transferred one byte at a time for 16 and 20 bit words or four bits at time for 12 bit words Figure 4 16 Fast Read or Write DRAM Access Timing 4 20 bit or 24 bit word 8 bit bus or 12 bit word 4 bit bus Relative Addressing Set up row address 1 2 3 R W Bits 23 16 4 5 6 R W Bits 15 8 7 8 9 R W Bits 7...

Page 140: ...20 bit word is read from and written into the upper most portion of the 24 bit word bits 23 4 Figure 4 17 Fast Read or Write DRAM Access Timing 5 20 bit word 4 bit bus Relative Addressing Set up row address 1 2 3 R W Bits 23 20 4 5 6 R W Bits 19 16 7 8 9 R W Bits 15 12 10 11 12 R W Bits 11 8 13 14 15 R W Bits 7 4 16 17 18 Finish last R W cycle 19 20 New memory cycle 1 2 Last Column Address Column ...

Page 141: ...ectly below Figure 4 18 Fast Read or Write DRAM Access Timing 6 24 bit word 4 bit bus Relative Addressing Set up row address 1 2 3 R W Bits 23 20 4 5 6 R W Bits 19 16 7 8 9 R W Bits 15 12 10 11 12 R W Bits 11 8 13 14 15 R W Bits 7 4 16 17 18 R W Bits 3 0 19 20 21 Finish last R W cycle 22 23 New memory cycle 1 2 Last Column Address Column Address Row Address CLK Address MRAS MCAS MWR MRD Row Addres...

Page 142: ...tly below Data accesses are left justified such that the 8 bit word is read from and written into the upper most byte of the 24 bit word bits 23 16 Figure 4 19 Slow Read or Write DRAM Access Timing 1 Column Address Row Address Valid Data CLK Address MRAS MCAS MWR MRD Data In Row Address Data Out Valid Data MWR MRD Read Write 8 bit word 8 bit bus Relative Addressing or each physical access in the A...

Page 143: ... from and written into the upper most two bytes of the 24 bit word bits 23 8 Data is transferred one byte at a time for 16 bit words or four bits at time for 8 bit words Figure 4 20 Slow Read or Write DRAM Access Timing 2 Last Column Address Column Address Row Address Valid Data Valid Data CLK Address MRAS MCAS MWR MRD Data In Row Address Data Out Valid Data Valid Data MWR MRD Read Write 16 bit wo...

Page 144: ...6 bit word is read from and written into the upper most two bytes of the 24 bit word bits 23 8 Figure 4 21 Slow Read or Write DRAM Access Timing 3 Last Column Address Column Address Row Address Valid Data Valid Data CLK Address MRAS MCAS MWR MRD Data In Row Address Data Out Valid Data Valid Data MWR MRD Read Write 16 bit word 4 bit bus Relative Addressing Set up row address 1 2 3 4 R W Bits 23 20 ...

Page 145: ...m and written into the upper most 20 bits 24 bits or 12 bits of the 24 bit word Data is transferred one byte at a time for 16 bit and 12 bit words or four bits at time for 12 bit words Figure 4 22 Slow Read or Write DRAM Access Timing 4 Last Column Address Column Address Row Address Valid Data Valid Data CLK Address MRAS MCAS MWR MRD Data In Row Address Data Out Valid Data Valid Data MWR MRD Read ...

Page 146: ...is read from and written into the upper most portion of the 24 bit word bits 23 4 Figure 4 23 Slow Read or Write DRAM Access Timing 5 Last Column Address Column Address Row Address Valid Data Valid Data CLK Address MRAS MCAS MWR MRD Data In Row Address Data Out Valid Data Valid Data MWR MRD Read Write 20 bit word 4 bit bus Relative Addressing Set up row address 1 2 3 4 R W Bits 23 20 5 6 7 8 R W B...

Page 147: ...igure 4 24 Slow Read or Write DRAM Access Timing 6 Last Column Address Column Address Row Address Valid Data Valid Data CLK Address MRAS MCAS MWR MRD Data In Row Address Data Out Valid Data Valid Data MWR MRD Read Write 24 bit word 4 bit bus Relative Addressing Set up row address 1 2 3 4 R W Bits 23 20 5 6 7 8 R W Bits 19 16 9 10 11 12 R W Bits 15 12 13 14 15 16 R W Bits 11 8 17 18 19 20 R W Bits ...

Page 148: ...m SRAM memory The cycle timing is shown at the top there are two clock cycles to set up the transfer and then from 1 to 16 cycles as determined by the ESTM bits followed by the last cycle This completes one memory access There can be from one to six memory accesses needed to transfer one word as shown in Table 4 11 on page 4 20 Figure 4 25 SRAM Read Write Timing Valid Data CLK Address MCS MCAS MWR...

Page 149: ...MOTOROLA DSP56009 User s Manual 5 1 SECTION 5 SERIAL HOST INTERFACE ...

Page 150: ...Interface 5 1 INTRODUCTION 5 3 5 2 SERIAL HOST INTERFACE INTERNAL ARCHITECTURE 5 4 5 3 SERIAL HOST INTERFACE PROGRAMMING MODEL 5 5 5 4 CHARACTERISTICS OF THE SPI BUS 5 19 5 5 CHARACTERISTICS OF THE I2C BUS 5 20 5 6 SHI PROGRAMMING CONSIDERATIONS 5 23 ...

Page 151: ...e the SHI can Identify its slave selection in Slave mode Simultaneously transmit shift out and receive shift in serial data Directly operate with 8 16 and 24 bit words Generate vectored interrupts separately for receive and transmit events and update status bits Generate a separate vectored interrupt in the event of a receive exception Generate a separate vectored interrupt in the event of a bus e...

Page 152: ...sfers without going through an intermediate register The single master configuration allows the DSP to directly connect to dumb peripheral devices For that purpose a programmable baud rate generator is included to generate the clock signal for serial transfers The host side invokes the SHI for communication and data transfer with the DSP through a shift register that may be accessed serially using...

Page 153: ...ponsibility to select the proper clock rate within the range as defined in the I2C and SPI bus specifications 5 3 SERIAL HOST INTERFACE PROGRAMMING MODEL The Serial Host Interface programming model is divided in two parts Host side see Figure 5 3 below and Section 5 3 1 on page 5 8 DSP side see Figure 5 4 on page 5 6 and Sections 5 3 2 on page 5 8 through 5 3 6 on page 5 13 for detailed informatio...

Page 154: ...5 6 DSP56009 User s Manual MOTOROLA Serial Host Interface Serial Host Interface Programming Model ...

Page 155: ... 7 Table 5 1 SHI Interrupt Vectors Address Interrupt Source P 0020 SHI Transmit Data P 0022 SHI Transmit Underrun Error P 0024 SHI Receive FIFO Not Empty P 0026 Reserved P 0028 SHI Receive FIFO Full P 002A SHI Receive Overrun Error P 002C SHI Bus Error Table 5 2 SHI Internal Interrupt Priorities Priority Interrupt Highest SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Rece...

Page 156: ...controlled by the SHI controller logic 5 3 2 SHI Host Transmit Data Register HTX DSP Side The Host Transmit data register HTX is used for DSP to Host data transfers The HTX register is 24 bits wide Writing to the HTX register clears the HTDE flag The DSP may program the HTIE bit to cause a Host transmit data interrupt when HTDE is set see 5 3 6 10 HCSR Transmit Interrupt Enable HTIE Bit 11 on page...

Page 157: ...s ignored in the other operational modes HSAR holds five bits of the 7 bit slave address of the device The SHI also acknowledges the general call address all 0s 7 bit address and a 0 R W bit specified by the I2C protocol HSAR cannot be accessed by the host processor 5 3 4 1 HSAR Reserved Bits Bits 17 0 19 These bits are reserved and unused They read as 0s and should be written with 0s for future c...

Page 158: ... Clock Phase and Polarity CPHA and CPOL Bits 1 0 The programmer may select any of four combinations of Serial Clock SCK phase and polarity when operating in the SPI mode refer to Figure 5 6 on page 5 10 The clock polarity is determined by the Clock Polarity CPOL control bit which selects an active high or active low clock When CPOL is cleared it produces a steady state low value at the SCK pin of ...

Page 159: ...HTX data will be transferred to the shift register for transmission as soon as the shift register is empty HTDE is set when the data is transferred from HTX to the shift register When in Master mode and CPHA 0 the DSP core should write the next data word to HTX when HTDE 1 clearing HTDE the data is transferred immediately to the shift register for transmission HTDE is set only at the end of the da...

Page 160: ...he operational mode of the noise reduction filters as described in Table 5 3 on page 5 12 The filters are designed to eliminate undesired spikes that might occur on the clock and data in lines and allow the SHI to operate in noisy environments when required One filter is located in the input path of the SCK SCL line and the other is located in the input path of the data line i e the SDA line when ...

Page 161: ...eration and reflects its status Each bit is described in one of the following paragraphs When in the Stop state or during individual reset the HCSR status bits are reset to their hardware reset state while the control bits are not affected 5 3 6 1 HCSR Host Enable HEN Bit 0 The read write control bit Host Enable HEN enables the overall operation of the SHI When HEN is set SHI operation is enabled ...

Page 162: ...le level When HFIFO is set the FIFO has 10 levels It is recommended that an SHI individual reset be generated HEN cleared before changing HFIFO HFIFO is cleared during hardware reset and software reset 5 3 6 6 HCSR Master Mode HMST Bit 6 The read write control bit HCSR Master HMST determines the operating mode of the SHI If HMST is set the interface operates in the Master mode If HMST is cleared t...

Page 163: ... correct transmission of the slave device address byte HIDLE should be set only when HTX is empty HTDE 1 After HIDLE is set a write to HTX will clear HIDLE and cause the generation of a Stop event a Start event and then the transmission of the eight MSBs of the data as the slave device address byte While HIDLE is cleared data written to HTX will be transmitted as is If the SHI completes transmitti...

Page 164: ...pt service routine 5 3 6 10 HCSR Transmit Interrupt Enable HTIE Bit 11 The read write HCSR Transmit Interrupt Enable HTIE control bit is used to enable the SHI transmit data interrupts If HTIE is cleared transmit interrupts are disabled and the HTDE status bit must be polled to determine if the SHI transmit data register is empty If both HTIE and HTDE are set and HTUE is cleared the SHI will reque...

Page 165: ...In this case the SHI will retransmit the previously transmitted word When operating in the SPI mode HTUE is set at the first clock edge if CPHA 1 it is set at the assertion of SS if CPHA 0 If a transmit interrupt occurs with HTUE set the transmit underrun interrupt vector will be generated If a transmit interrupt occurs with HTUE cleared the regular transmit data interrupt vector will be generated...

Page 166: ...rror HROE indicates that a data receive overrun error occurred Receive overrun errors can not occur when operating in the I2C Master mode since the clock is suspended if the receive FIFO is full HROE is set when the shift register IOSR is filled and ready to transfer the data word to the HRX FIFO and the FIFO is already full HRFF is set When a receive overrun error occurs the shift register is not...

Page 167: ...ected together in a circular manner where one shift register is located on the master side and the other on the slave side Thus the data bytes in the master device and slave device are effectively exchanged The MISO and MOSI data pins are used for transmitting and receiving serial data When the SPI is configured as a master MISO is the master data input line and MOSI is the master data output line...

Page 168: ...ifications a low speed mode 2 kHz clock rate and a high speed mode 100 kHz clock rate are defined The SHI operates in the high speed mode only 5 5 1 Overview The I2C bus protocol must conform to the following rules Data transfer may be initiated only when the bus is not busy During data transfer the data line must remain stable whenever the clock line is high Changes in the data line when the cloc...

Page 169: ...al The data on the line may be changed during the low period of the clock signal There is one clock pulse per bit of data Each 8 bit word is followed by one acknowledge bit This acknowledge bit is a high level put on the bus by the transmitter when the master device generates an extra acknowledge related clock pulse A slave receiver that is addressed is obliged to generate an acknowledge after the...

Page 170: ...ts this feature when operating as a master device and will wait until the slave device releases the SCL line before proceeding with the data transfer 5 5 2 I2 C Data Transfer Formats I2C bus data transfers follow the following format after the Start event a slave device address is sent This address is 7 bits wide the eighth bit is a data direction bit R W 0 indicates a transmission write and 1 ind...

Page 171: ... external device by receiving and or transmitting data Before changing the SHI operational mode an SHI individual reset should be generated by clearing the HEN bit The following paragraphs describe programming considerations for each operational mode Figure 5 10 I2C Bus Protocol For Host Write Cycle Figure 5 11 I2C Bus Protocol For Host Read Cycle S A A 0 Slave Address R W S P A Start Start or Bit...

Page 172: ...transmit to receive data If a write to HTX occurs its contents are transferred to IOSR between data word transfers The IOSR data is shifted out via MISO and received data is shifted in via MOSI The DSP may write HTX if the HTDE status bit is set If no writes to HTX occurred the contents of HTX are not transferred to IOSR so the data that is shifted out when receiving is the same as the data presen...

Page 173: ...S input pin of the SPI master device should be held deasserted high for proper operation If the SPI master device SS pin is asserted the Host Bus Error status bit HBER is set If the HBIE bit is also set the SHI issues a request to the DSP interrupt controller to service the SHI Bus Error interrupt In the SPI Master mode the DSP must write to HTX to receive transmit or perform a full duplex data tr...

Page 174: ... the SCL serial clock input MISO SDA is the SDA open drain serial data line MOSI HA0 is the HA0 slave device address input SS HA2 is the HA2 slave device address input HREQ is the Host Request output When the SHI is enabled and configured in the I2C Slave mode the SHI controller inspects the SDA and SCL lines to detect a Start event Upon detection of the Start event the SHI receives the slave devi...

Page 175: ...hat the next received data word will be stored in the FIFO HREQ is deasserted at the first clock pulse of the next received word The HREQ line may be used to interrupt the external I2C master device Connecting the HREQ line between two SHI equipped DSPs one operating as an I2C master device and the other as an I2C slave device enables full hardware handshaking 5 6 3 2 Transmit Data In I2C Slave Mo...

Page 176: ...ardware handshaking 5 6 4 I2C Master Mode The I2C Master mode is entered by enabling the SHI HEN 1 selecting the I2C mode HI2C 1 and selecting the master mode of operation HMST 1 Before enabling the SHI as an I2C master the programmer should program the appropriate clock rate in HCKR When configured in the I2C Master mode the SHI external pins operate as follows SCK SCL is the SCL serial clock out...

Page 177: ...nsfer When deasserted HREQ will prevent the clock generation of the next data word transfer until it is asserted again Connecting the HREQ line between two SHI equipped DSPs one operating as an I2C master device and the other as an I2C slave device enables full hardware handshaking 5 6 4 1 Receive Data in I2C Master Mode A receive session is initiated if the R W direction bit of the transmitted sl...

Page 178: ... transmitted byte was acknowledged ACK 0 the SHI controller continues transmitting the next byte However if it was not acknowledged ACK 1 the HBER status bit is set to inform the DSP side that a bus error or overrun or any other exception in the slave device has occurred Consequently the I2C master device generates a Stop event and terminates the session HTX contents are transferred to the IOSR wh...

Page 179: ... the Stop state the SHI will remain in the individual reset state While in the individual reset state SHI input pins are inhibited Output and bidirectional pins are disabled high impedance The HCSR status bits and the transmit receive paths are reset to the same state produced by hardware reset or software reset The HCSR and HCKR control bits are not affected Note Motorola recommends that the SHI ...

Page 180: ...5 32 DSP56009 User s Manual MOTOROLA Serial Host Interface SHI Programming Considerations ...

Page 181: ...MOTOROLA DSP56009 User s Manual 6 1 SECTION 6 SERIAL AUDIO INTERFACE ...

Page 182: ...6009 User s Manual MOTOROLA Serial Audio Interface 6 1 INTRODUCTION 6 3 6 2 SERIAL AUDIO INTERFACE INTERNAL ARCHITECTURE 6 4 6 3 SERIAL AUDIO INTERFACE PROGRAMMING MODEL 6 8 6 4 PROGRAMMING CONSIDERATIONS 6 24 ...

Page 183: ... the serial clock and the word select lines are driven internally according to the baud rate generator programming In the Slave mode these signals are supplied from an external source The transmitter consists of three transmit data registers three fully synchronized output shift registers and three serial data output lines controlled by one transmitter controller This permits data transmission to ...

Page 184: ...ntly or separately The following paragraphs describe the operation of these sections 6 2 1 Baud Rate Generator The baud rate generator produces the internal serial clock for the SAI if either or both of the receiver and transmitter sections are configured in the Master mode The baud rate generator is disabled if both receiver and transmitter sections are configured as slaves Figure 6 1 illustrates...

Page 185: ...l pins are tri stated The block diagram of the receiver section is shown in Figure 6 2 The 24 bit shift registers receive the incoming data from the Serial Data In pins SDI0 and SDI1 or SDIx Data is shifted in at the transitions of the serial receive clock SCKR Data is assumed to be received MSB first if RDIR is cleared and LSB first if RDIR is set Data is transferred to the SAI receive data regis...

Page 186: ...ection equally affect all three transmitters The transmit section can be configured as a master driving its bit clock and word select lines from the internal baud rate generator or as a slave receiving these signals from an external source Each of the three transmitters can be enabled separately When a transmitter is disabled its associated Serial Data Out SDO pin goes to high level When all trans...

Page 187: ...r is considered empty and ready to be reloaded can be 16 24 or 32 bits as determined by the TWL1 and TWL0 control bits in the TCS register A special control mechanism is used to emulate a 32 bit shift register if the word length is defined as 32 bits This is done by enabling eight data shifts at the beginning end of the data word transfer according to the TDWE bit in the TCS register These shift r...

Page 188: ...ns for the SAI are shown in Table 6 1 The interrupts generated by the SAI are prioritized as shown in Table 6 2 Figure 6 4 SAI Registers PM0 0 1 PM2 2 PM3 3 PM4 4 5 PM6 6 PM7 7 PSR 8 9 10 11 12 13 14 15 Baud Rate Control Register BRC R0EN 0 1 RMST 2 RWL0 3 RWL1 4 5 RDIR 6 RLRS 7 RCKP 8 RREL 9 RDWT 10 RXIE 11 12 13 RLDF 14 RRDF 15 Receive Control Status Register RCS T0EN 0 1 TMST 2 TWL0 3 TWL1 4 5 ...

Page 189: ...are defined as slaves or when both are in the individual reset state otherwise improper operation may result When read by the DSP the BRC appears on the two low order bytes of the 24 bit word and the high order byte is read as 0s The BRC is cleared during hardware reset and software reset Table 6 1 SAI Interrupt Vector Locations Interrupt TXIL 0 TXIL 1 RXIL 0 RXIL 1 Left Channel Transmit P 0010 P ...

Page 190: ...S is a 16 bit read write control status register used to direct the operation of the receive section in the SAI see Figure 6 4 on page 6 8 The control bits in the RCS determine the serial format of the data transfers whereas the status bits of the RCS are used by the DSP programmer to interrogate the status of the receiver Receiver enable and interrupt enable bits are also provided in the RCS When...

Page 191: ...igured as a master In the Master mode the receiver drives the SCKR and WSR pins When RMST is cleared the SAI receiver section is configured as a slave In the Slave mode the SCKR and WSR pins are driven from an external source The RMST bit is cleared during hardware reset and software reset 6 3 2 5 RCS Receiver Word Length Control RWL 1 0 Bits 4 and 5 The read write Receiver Word Length RWL 1 0 con...

Page 192: ...nt bit first see Figure 6 5 The RDIR bit is cleared during hardware reset and software reset 6 3 2 7 RCS Receiver Left Right Selection RLRS Bit 7 The read write Receiver Left Right Selection RLRS control bit selects the polarity of the Receiver Word Select WSR signal that identifies the Left or Right word in the input bit stream When RLRS is cleared WSR low identifies the Left data word and WSR hi...

Page 193: ...he positive edge of the clock and are considered valid during negative transitions of the clock see Figure 6 7 The RCKP bit is cleared during hardware reset and software reset 6 3 2 9 RCS Receiver Relative Timing RREL Bit 9 The read write Receiver Relative timing RREL control bit selects the relative timing of the Word Select Receive WSR signal as referred to the serial data input lines SDIx When ...

Page 194: ...egister When RDWT is set the last 24 bits received are transferred to the data register The RDWT bit is ignored if RWL 1 0 are set for a word length other than 32 bits see Figure 6 9 on page 6 14 The RDWT bit is cleared during hardware reset and software reset Figure 6 8 Receiver Relative Timing RREL Programming Figure 6 9 Receiver Data Word Truncation RDWT Programming MSB LSB LSB MSB SDI WSR MSB ...

Page 195: ...RRDF 1 This means that the previous data in the receive data register was lost and an overrun occurred To clear RLDF or RRDF during Left or Right channel interrupt service the receive data registers of the enabled receivers must be read Clearing RLDF or RRDF will clear the respective interrupt request If the Receive interrupt with exception indication is signaled RLDF RRDF 1 then RLDF and RRDF are...

Page 196: ...st will depend on the state of the receive overrun condition The RLDF bit is cleared during hardware reset and software reset 6 3 2 14 RCS Receiver Right Data Full RRDF Bit 15 Receiver Right Data Full RRDF is a read only status bit which in conjunction with RLDF indicates the status of the enabled receive data register RRDF is set when the right data word as indicated by the WSR pin and the RLRS b...

Page 197: ... the bits in TCS When the T0EN T1EN and T2EN bits are cleared the SAI transmitter section is disabled and it enters the individual reset state after a one instruction cycle delay While in the Stop or individual reset state the status bits in TCS are cleared Stop or individual reset do not affect the TCS control bits The programmer should change TCS control bits except for TXIE only while the trans...

Page 198: ...Bits 4 5 The read write control bits Transmitter Word Length TWL 1 0 are used to select the length of the data words transmitted by the SAI The data word length is defined by the number of serial clock cycles between two edges of the word select signal Word lengths of 16 24 or 32 bits may be selected as shown in Table 6 4 If the 16 bit word length is selected the 16 MSBs of the transmit data regis...

Page 199: ...KP control bit switches the polarity of the transmitter serial clock When TCKP is cleared the transmitter clock polarity is negative Negative polarity means that the Word Select Transmit WST and Serial Data Out SDOx lines change synchronously with the negative edge of the clock and are considered valid during positive transitions of the clock When TCKP is set the transmitter clock polarity is posi...

Page 200: ...together with the last bit of the previous data word as required by the I2 S format see Figure 6 13 The TREL bit is cleared during hardware reset and software reset 6 3 4 10 TCS Transmitter Data Word Expansion TDWE Bit 10 The read write Transmitter Data Word Expansion TDWE control bit selects the method used to expand a 24 bit data word to 32 bits during transmission When TDWE is cleared after tra...

Page 201: ... Clearing TXIE will mask a pending transmitter interrupt only after a one instruction cycle delay If TXIE is cleared in a long interrupt service routine it is recommended that at least one other instruction should be inserted between the instruction that clears TXIE and the RTI instruction at the end of the interrupt service routine There are three different transmit data interrupts that have sepa...

Page 202: ...t is cleared during hardware reset and software reset Refer to Table 6 1 on page 6 9 6 3 4 13 TCS Reserved Bit Bit 13 Bit 13 in TCS is reserved and unused It is read as 0s and should be written with 0 for future compatibility 6 3 4 14 TCS Transmitter Left Data Empty TLDE Bit 14 Transmitter Left Data Empty TLDE is a read only status bit that in conjunction with TRDE indicates the status of the enab...

Page 203: ...TLDE and TRDE are set TRDE is cleared when the DSP writes to the transmit data register of the enabled transmitters provided that When a transmit underrun condition occurs the previous data which is still present in the data registers will be re transmitted In this case TRDE is cleared by first reading the TCS register followed by writing the transmit data registers of the enabled transmitters If ...

Page 204: ...he Left word is detected on the WST pin if operating in the Slave mode Note that even though the TRDE and TLDE status flags are always cleared while the transmitter section is in the individual reset state the transmit data registers may be written in this state The data will remain in the transmit data registers while the transmitter section is in the individual reset state and will be transferre...

Page 205: ... unexpected operation might result In particular this can happen when SCKR SCKT runs freely and WSR WST transitions occur earlier or later than expected in terms of complete bit clock cycles In order to explore the SAI reaction in such irregular conditions the operation of the SAI state machine is described here After completion of a data word transfer or upon exiting the individual reset state th...

Page 206: ...t Likewise when the WSR WST transition appears later than expected in the time period between the completion of the previous word and the appearance of the late WSR WST transition the data bits being received are ignored and no data is transmitted These characteristics can be used to disable reception or transmission of undesired data words by keeping SCKR SCKT running freely and gating WSR WST fo...

Page 207: ...MOTOROLA DSP56009 User s Manual 7 1 SECTION 7 GENERAL PURPOSE INPUT OUTPUT ...

Page 208: ...7 2 DSP56009 User s Manual MOTOROLA General Purpose Input Output 7 1 INTRODUCTION 7 3 7 2 GPIO PROGRAMMING MODEL 7 3 7 3 GPIO REGISTER GPIOR 7 3 ...

Page 209: ...IOR which is illustrated in Figure 7 1 The register is described in the following paragraphs 7 3 GPIO REGISTER GPIOR The GPIO Register GPIOR is a 24 bit read write control data register used to operate and configure the GPIO pins The control bits in the GPIOR select the direction of data transfer for each pin whereas the data bits in the GPIOR are used to read from or write to the GPIO pins Hardwa...

Page 210: ...bility 7 3 3 GPIOR Data Direction Bits GDD 3 0 Bits 11 8 The read write GPIO Data Direction bits GDD 3 0 select the direction of data transfer for each of the GPIO 3 0 pins see Table 7 1 When the GDDx bit is cleared the corresponding GPIOx pin is defined as an input When the GDDx bit is set the corresponding GPIOx pin is defined as an output The GDD 3 0 bits are cleared during hardware reset and s...

Page 211: ...fer is connected to the pin see Table 7 1 and Figure 7 2 When the GCx bit is cleared and the GDDx bit is set the pin is defined as output the corresponding GPIOx pin output buffer is defined as a standard active high active low type see Table 7 1 and Figure 7 2 When the GCx bit is set and the GDDx bit is set the pin is defined as output the corresponding GPIOx pin output buffer is defined as an op...

Page 212: ...7 6 DSP56009 User s Manual MOTOROLA General Purpose Input Output GPIO Register GPIOR ...

Page 213: ...1 1 0 1 1 0 1 0 0 0 0 1 1 0 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1 0 0 0 0 1 1 0 1 1 0 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 ...

Page 214: ...A 2 DSP56009 User s Manual MOTOROLA Bootstrap ROM Contents A 1 INTRODUCTION A 3 A 2 BOOTSTRAPPING THE DSP A 3 A 3 BOOTSTRAP PROGRAM LISTING A 4 A 4 BOOTSTRAP FLOW CHART A 7 ...

Page 215: ...rnal Program RAM is loaded with 1 536 consecutive bytes from an EPROM connected to the EMI The EPROM is located at the EMI address 0 when operating the EMI in the Absolute Addressing SRAM mode EAM2 EAM0 000 It is assumed that the EPROM is selected enabled through the GPIO3 pin which is driven low in this Bootstrap mode The GPIO3 output is programmed to be of the active high active low type The byt...

Page 216: ...or0 equ ffe9 EMI Offset Register edrf equ 13 EMI EDRR Full flag hrne equ 17 SHI FIFO Not Empty flag hrx equ fff3 SHI HRX FIFO hcsr equ fff1 SHI Control Status Register hi2c equ 1 SHI IIC Enable Control Bit ma equ 0 OMR Mode A mb equ 1 OMR Mode B mc equ 4 OMR Mode C org p 0 bootstrap code starts at 0 start clr a 0 r0 r0 points to internal Program RAM bset 13 a0 Program ROM starting address 2000 jcl...

Page 217: ...2 EAM0 000 EINR 1 EINW 0 EIS1 EIS0 00 ERTS 0 ETDM 1 ESTM3 ESTM0 1111 EME 1 bset gdd3 x gpior enable EPROM GPIO3 0 GD 3 0 0000 GDD 3 0 1000 GC 3 0 0000 do 512 _loop1 movep a1 x eor0 trigger read jclr edrf x ecsr wait for EDRR full movep x edrr0 p r0 store in Program RAM _loop1 bset gd3 x gpior disable EPROM GPIO3 1 GD 3 0 1000 GDD 3 0 1000 GC 3 0 0000 jmp exit Exit bootstrap ROM This is the routine...

Page 218: ...e x hcsr wait for HRX not empty movep x hrx p r0 store in Program RAM exit Exit bootstrap ROM clr a a0 r0 r0 points to destination address andi ec omr set operating mode to 0 and trigger an exit from Bootstrap mode movep a1 x bcr Delay needed for Op Mode change used to clear BCR jmp r0 Then go to destination address ...

Page 219: ... 4 BOOTSTRAP FLOW CHART Figure A 1 Bootstrap Flow Chart RESET Wake up on Bootstrap Mode with OnCE Enabled Mode A Mode C Mode B Download Download Download SHI SPI SHI I2 C EMI Switch to Go to P 0 0 0 0 1 1 No Normal Mode Switch to Go to P 2000 Normal Mode AA0443k ...

Page 220: ...A 8 DSP56009 User s Manual MOTOROLA Bootstrap ROM Contents ...

Page 221: ...MOTOROLA DSP56009 User s Manual B 1 APPENDIX B PROGRAMMING REFERENCE ...

Page 222: ...9 User s Manual MOTOROLA Programming Reference B 1 INTRODUCTION B 3 B 2 PERIPHERAL ADDRESSES B 3 B 3 INTERRUPT ADDRESSES B 3 B 4 INTERRUPT PRIORITIES B 3 B 5 INSTRUCTION SET SUMMARY B 3 B 6 PROGRAMMING SHEETS B 3 ...

Page 223: ...n photocopy these sheets and reuse them for each application development project B 2 PERIPHERAL ADDRESSES Figure B 1 is a memory map of the on chip peripherals showing their addresses in memory B 3 INTERRUPT ADDRESSES Table B 1 on page B 5 lists the interrupt starting addresses and sources B 4 INTERRUPT PRIORITIES Table B 2 on page B 6 lists the priorities of specific interrupts within interrupt p...

Page 224: ...Address Register 1 EBAR1 X FFEB EMI Control Status Register ECSR X FFEA EMI Data Register 0 EDRR0 EDWR0 X FFE9 EMI Offset Register 0 EOR0 X FFE8 EMI Base Address Register 0 EBAR0 X FFE7 SAI TX2 Data Register TX2 X FFE6 SAI TX1 Data Register TX1 X FFE5 SAI TX0 Data Register TX0 X FFE4 SAI TX Control Status Register TCS X FFE3 SAI RX1 Data Register RX1 X FFE2 SAI RX0 Data Register RX0 X FFE1 SAI RX ...

Page 225: ...0018 0 2 SAI Right Channel Receiver if RXIL 0 P 001A 0 2 SAI Receiver Exception if RXIL 0 P 001C Reserved P 001E 3 NMI P 0020 0 2 SHI Transmit Data P 0022 0 2 SHI Transmit Underrun Error P 0024 0 2 SHI Receive FIFO Not Empty P 0026 Reserved P 0028 0 2 SHI Receive FIFO Full P 002A 0 2 SHI Receive Overrun Error P 002C 0 2 SHI Bus Error P 002E Reserved P 0030 0 2 EMI Write Data P 0032 0 2 EMI Read Da...

Page 226: ...ce Lowest SWI Levels 0 1 2 Maskable Highest IRQA External Interrupt IRQB External Interrupt SAI Receiver Exception SAI Transmitter Exception SAI Left Channel Receiver SAI Left Channel Transmitter SAI Right Channel Receiver SAI Right Channel Transmitter SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty EMI EBAR0 Me...

Page 227: ... AND I xx D 1 2 ASL D parallel move 1 mv 2 mv ASR D parallel move 1 mv 2 mv 0 BCHG n X aa 1 ea 4 mvb n X pp n X ea n Y aa n Y pp n Y ea n D BCLR n X aa 1 ea 4 mvb n X pp n X ea n Y aa n Y pp n Y ea n D BSET n X aa 1 ea 4 mvb n X pp n X ea n Y aa n Y pp n Y ea n D indicates that the bit is unaffected by the operation indicates that the bit may be set according to the definition depending on paralle...

Page 228: ...1 ea 4 jx JCLR n X ea xxxx 2 6 jx n X aa xxxx n X pp xxxx n Y ea xxxx n Y aa xxxx n Y pp xxxx n S xxxx Table B 3 Instruction Set Summary Sheet 2 of 7 Mnemonic Syntax Parallel Moves Instruction Program Words Osc Clock Cycles Status Request Bits S L E U N Z V C indicates that the bit is unaffected by the operation indicates that the bit may be set according to the definition depending on parallel mo...

Page 229: ...move 1 mv 2 mv 0 LSR D parallel move 1 mv 2 mv 0 LUA ea D 1 4 MAC S2 S1 D parallel move 1 mv 2 mv S1 S2 D parallel move Table B 3 Instruction Set Summary Sheet 3 of 7 Mnemonic Syntax Parallel Moves Instruction Program Words Osc Clock Cycles Status Request Bits S L E U N Z V C indicates that the bit is unaffected by the operation indicates that the bit may be set according to the definition dependi...

Page 230: ... A B X ea X0 B Y memory data move Y ea D mv mv Y aa D S Y ea S Y aa xxxxxx D Register and Y memory data move S1 D1 Y ea D2 mv mv S1 D1 S2 Y ea S1 D1 xxxxxx D2 Y0 A A Y ea Y0 B B Y ea Table B 3 Instruction Set Summary Sheet 4 of 7 Mnemonic Syntax Parallel Moves Instruction Program Words Osc Clock Cycles Status Request Bits S L E U N Z V C indicates that the bit is unaffected by the operation indica...

Page 231: ...pp D 1 ea 2 mvp X pp X ea X pp Y ea X pp P ea S X pp xxxxxx X pp X ea X pp Table B 3 Instruction Set Summary Sheet 5 of 7 Mnemonic Syntax Parallel Moves Instruction Program Words Osc Clock Cycles Status Request Bits S L E U N Z V C indicates that the bit is unaffected by the operation indicates that the bit may be set according to the definition depending on parallel move conditions indicates that...

Page 232: ...2 mv 0 OR S D parallel move 1 mv 2 mv 0 ORI xx D 1 2 REP X ea 1 4 mv X aa Y ea Y aa S xxx RESET 1 4 RND D parallel move 1 mv 2 mv Table B 3 Instruction Set Summary Sheet 6 of 7 Mnemonic Syntax Parallel Moves Instruction Program Words Osc Clock Cycles Status Request Bits S L E U N Z V C indicates that the bit is unaffected by the operation indicates that the bit may be set according to the definiti...

Page 233: ... mv TST S parallel move 1 mv 2 mv 0 WAIT 1 n a Table B 3 Instruction Set Summary Sheet 7 of 7 Mnemonic Syntax Parallel Moves Instruction Program Words Osc Clock Cycles Status Request Bits S L E U N Z V C indicates that the bit is unaffected by the operation indicates that the bit may be set according to the definition depending on parallel move conditions indicates that the bit is set according to...

Page 234: ...tension Limit FFT Scaling Interrupt Mask Scaling Mode Reserved Trace Mode Double Precision Multiply Mode Loop Flag 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF T S1 S0 I1 I0 L E U N Z V C Status Register SR Read Write Reset 0300 DM S Mode Register MR Condition Code Register CCR Reserved write as 0 0 Note The operation and function of the Status Register is detailed in the DSP56000 Family Manual ...

Page 235: ... IBL1 IBL0 IAL2 IAL1 IAL0 Interrupt Priority X FFFF Read Write SHL1 SHL0 Reset 000000 Register IPR 23 22 21 20 19 18 16 17 0 0 0 0 0 0 0 0 0 0 0 0 EML1 0 0 SAI IPL SHL1 SHL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 SHI IPL EML1 EML0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 EMI IPL ILA2 Trigger 0 Level 1 Neg Edge IRQB Mode IBL1 IBL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 I...

Page 236: ...0 0 0 0 0 0 0 0 0 0 0 19 18 17 16 0 0 0 0 23 22 21 20 0 0 0 0 0 0 Stop Delay 0 128K T Stabilization 1 16 T Stabilization Bits 5 and 7 through 23 are reserved write as 0 Mode M M M C B A Operating Mode 0 0 0 0 Normal operation bootstrap disabled 1 0 0 1 Bootstrap from EMI 2 0 1 0 Wake up in PROM address 2000 3 0 1 1 Reserved 4 1 0 0 Reserved 5 1 0 1 Bootstrap from SHI SPI 6 1 1 0 Reserved 7 1 1 1 B...

Page 237: ...7 16 23 22 21 20 0 MF8 MF9 PSTP PEN CSRC Multiplication Factor Bits MF0 MF11 MF11 MF0 Multiplication Factor MF 000 1 001 2 002 3 FFE 4095 FFF 4096 Stop Processing State Bit PSTP 0 PLL Disabled during Stop Processing State 1 PLL Enabled during Stop Processing State PLL Enable Bit PEN 0 Disable PLL 1 Enable PLL Chip Clock Source Bit CSRC 0 Output from Low Power Divider 1 Output from VCO Reserved wri...

Page 238: ...1 Data Register Buffer and Data Read Register Full ECSR EMI Busy EBSY Read Only Status Bit 0 No Transfers No Requests pending 1 Transfers and or Requests pending ECSR Read Trigger Select ERTS 0 Triggered by Write to EOR 1 Triggered by Read from EDRR ECSR EMI Enable EME 0 Individual Reset 1 Transfers Enabled ECSR Data Bus Width EBW 0 4 Bits 1 8 Bits ECSR Increment EBAR After Read EINR 0 EBAR unmodi...

Page 239: ...dress X FFEC Read Write Reset xxxxxx Register 1 EBAR1 19 18 17 16 23 22 21 20 Base Address Register 1 Contents 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EMI Read Offset X FFE9 EOR0 Reset 000000 Register Read Write 19 18 17 16 23 22 21 20 Read Offset Register Contents 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EMI Write Offset X FFE6 Read Write Reset 000000 Register EWOR 19 18 17 16 23 22 21 20 Write Offset...

Page 240: ...lication Date Programmer Sheet 3 of 4 E M I 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 23 22 21 20 Data Read Register Contents 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 23 22 21 20 Data Write Register Contents EMI Data Write Register Write Only EMI Data Read Register Read Only EMI Data Write X FFEA EDWR0 Reset xxxxxx Register Write Only X FFEE EDWR1 ...

Page 241: ...3 22 21 20 EPS0 EPS1 EOSR ERED Reserved write as 0 0 0 EREF ECD6 0 0 0 0 0 0 0 0 0 Refresh Rate Preset Value ERCR Refresh Clock Prescaler EPS0 EPS1 EPS1 EPS0 Interrupt Select 0 0 Divide By 64 0 1 Divide by 8 1 0 Prescaler bypassed 1 1 Reserved ERCR One Shot Refresh EOSR 0 No refresh 1 Refresh trigger ERCR Refresh Enable EREF 0 Refresh Cycle insertion disabled 1 CAS before RAS Refresh Cycle inserte...

Page 242: ... HA5 0 0 HA6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HA4 0 0 0 0 0 0 0 0 0 0 HDM5 HCKR Divider Modulus Select HSAR I 2 C Slave Address Slave address Bits HA6 HA3 HA1 and external pins HA2 HA0 Slave address after reset 1011_HA2_0_HA0 HFM1 HFM0 SHI Noise Reduction Filter Mode 0 0 Bypassed Filter disabled 0 1 Reserved 1 0 Narrow spike tolerance 1 1 Wide spike tolerance HFM0 HFM1 SHI Clock Control Register ...

Page 243: ...4 3 2 1 0 SHI Host Transmit X FFF3 Write Only Reset xxxxxx Data Register HTX 19 18 17 16 23 22 21 20 Host Transmit Data Register Contents 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SHI Host Receive X FFF3 Read Only Reset xxxxxx Data Register HRX 19 18 17 16 23 22 21 20 Host Receive Data Register Contents SHI Host Receive Data Register HRX SHI Host Transmit Data Register HTX ...

Page 244: ... C Asserted if IOSR ready to transmit or receive SPI Asserted if IOSR ready to transmit and receive HIDLE Description 0 Bus busy 1 Stop event HBIE Description 0 Bus Error Interrupt disabled 1 Bus Error Interrupt enabled HTIE Description 0 Transmit Interrupt disabled 1 Transmit Interrupt activated Host Transmit Underrun Error Read Only Status Bit Host Transfer Data Empty Read Only Status Bit Host R...

Page 245: ...irst 1 Data shifted in LSB first RLRS Description 0 WSR low identifies Left data word WSR high identifies Right data word 1 WSR high identifies Left data word WSR low identifies Right data word RCKP Description 0 Polarity is negative 1 Polarity is positive RREL Description 0 WSR occurs with 1st bit 1 WSR occurs 1 cycle earlier RDWT Description 0 First 24 bits transferred 1 Last 24 bits transferred...

Page 246: ...t MSB first 1 Data shifted out LSB first TLRS Description 0 WST low identifies Left data word WST high identifies Right data word 1 WST high identifies Left data word WST low identifies Right data word TCKP Description 0 Polarity is negative 1 Polarity is positive TREL Description 0 WSR occurs with 1st bit 1 WSR occurs 1 cycle earlier TDWE Description 0 Last bit transmitted 8 times 1 First bit tra...

Page 247: ...5 4 3 2 1 0 SAI Receive Data X FFE3 Read Only Reset xxxxxx Register 1 RX1 19 18 17 16 23 22 21 20 Receive Data Register 1 Contents SAI Receive Data Register 1 RX1 SAI Receive Data Register 0 RX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Baud Rate Control X FFE0 Reset 0000 Register BRC PM0 PM1 PM3 0 PM4 0 0 0 0 0 0 PM2 0 PM5 PM7 PSR PM6 PSR Description 0 Divide by 8 prescaler operational 1 Divide by 8 ...

Page 248: ...3 22 21 20 Transmit Data Register 2 Contents 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SAI Transmit Data X FFE5 Write Only Reset xxxxxx Register 0 TX0 19 18 17 16 23 22 21 20 Transmit Data Register 0 Contents 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SAI Transmit Data X FFE6 Write Only Reset xxxxxx Register 1 TX1 19 18 17 16 23 22 21 20 Transmit Data Register 1 Contents SAI Transmit Data Register 2 TX2 SA...

Page 249: ... of 1 GPIO Reserved write as 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GD3 GD2 GD1 GD0 GPIO Control Data X FFF7 Reset 000000 Register GPIOR 19 18 17 16 23 22 21 20 GC3 0 GDD3 GDD2 GDD1 GDD0 GC1 GCx GDDx GPIO Pin Definition 0 0 Disconnected 0 1 Standard output 1 0 Input 1 1 Open drain output 0 0 0 0 0 0 0 0 0 GC0 GC2 0 0 0 0 0 GPIO Data Bits ...

Page 250: ...B 30 DSP56009 User s Manual MOTOROLA Programming Reference ...

Page 251: ...MOTOROLA DSP56009 User s Manual C 1 APPENDIX C APPLICATION EXAMPLES ...

Page 252: ...cation Examples C 1 INTRODUCTION C 3 C 2 TYPICAL SYSTEM TOPOLOGY C 3 C 3 TYPICAL AUDIO APPLICATION C 4 C 4 PROGRAM OVERLAY C 5 C 5 SINGLE DELAY LINE C 5 C 6 EARLY REFLECTION FILTER C 6 C 7 TWO CHANNEL COMB FILTER C 7 C 8 3 TAP FIR FILTER C 10 ...

Page 253: ... bus 12 clock cycles per word transfer C 2 TYPICAL SYSTEM TOPOLOGY Figure C 1 shows the topology of a typical DSP audio application Figure C 1 Topology of DSP Typical Audio Application I2 S SONY I2 S SONY CONSUMER TR0 TR1 Stereo A D I2 S SONY REC0 SRAM DRAM EXTAL MD7 0 MA17 0 HOST SHI Stereo A D REC1 TR2 External Sinusoidal Clock Source I2 S SONY I2 S SONY GPIO AUDIO DSP PROCESSOR Stereo D A Stere...

Page 254: ...C3 Surround or DTS Figure C 2 Using the DSP56009 for Surround Sound Optional memory for soundfield effects DTS decoding buffering and booting DSP56009 SAI Tx SAI Tx ICE 958 Rx SAI Rx Host Microcontroller SHI EEPROM EMI SAI Tx Stereo DAC Stereo DAC Stereo DAC Right Left Center Subwoofer Surround L Surround R AA0444 not required for AC3 applications SRAM ...

Page 255: ... EDDR do N 2 end_OL loop to drive more N 2 triggers rep 1 nop movep x EDRR0 p r0 move previous read data to PMEM and trigger next read cycle end_OL bclr ERTS x ECSR turn off read triggers by EDRR read movep x EDRR0 p r0 move instruction N 1 to PMEM movep x EDRR0 p r0 move instruction N to PMEM bset GPIOR x GPIOR negate GPIO3 disable CS C 5 SINGLE DELAY LINE The following routine is an example of a...

Page 256: ...st read cycle clr a x r0 x0 y r4 y0 fetch 1st gain and 2nd delay do N 1 end_E movep x0 x EOR0 initiate next read trigger nop nop or other nop nop or other movep x EDRR0 x1 read current data mac x1 y0 a x r0 x0 y r4 y0 sum fetch next gain and offset nop nop or other end_E movep x SAMPLE x EDWR0 write current sample to delay line EWOR 0 nop nop or other movep x EDRR0 x1 read last data macr x1 y0 a c...

Page 257: ...fset zero dual_comb move Base_buff r0 pointer to base address values move Off_buff r1 pointer to offset delay values move Gain_buff r2 pointer to gains values move SAMPLE r4 pointer to left right samples move 0 x0 move 0 x1 x1 accumulates right comb outputs move 0 y1 x1 accumulates left comb outputs movep MODE x ECSR EINR 1 ERTS 0 do N end_comb move x1 b load right channel output movep x r0 x EBAR...

Page 258: ...y0 a b y1 compute input to delay buffer right and store left channel output movep a x EDWR1 insert input in delay buffer right point 3 insert nop or other instructions if required nop nop or other nop nop or other end comb move x1 b add x0 b y1 y out_left store left output move b x out_right store right output ...

Page 259: ...C 4 Two Channel Comb Filter Structure Delay T1 G1 Delay TN GN Comb Filters for One Channel Base Buffers Left Offset Buffers Left Gain Buffers Left Sample Left Base Buffers Right Offset Buffers Right Gain Buffers Right Sample Right r0 r0 r1 r2 r4 r1 r2 r4 X Y AA0448 ...

Page 260: ...pling rate 0 05 44100 2205 locations FIR Filter Assembler Code EMI mode increment EBAR on write operation movep x FIR_BASE x EBAR0 set FIR base address movep T1_OFF x EOR0 offset T1 and trigger mem read wait 3 DRAM or 1 SRAM inst cycles or do other tasks movep T2_OFF x EOR0 offset T2 and trigger mem read clr a x G1 x0 get G1 clear accumulator movep x EDRR0 y0 get x n T1 movep T3_OFF x EOR0 offset ...

Page 261: ...Application Examples MOTOROLA DSP56009 User s Manual C 11 Figure C 5 3 Tap FIR Filter Delay T1 Gain G1 y n G1 x n T1 G2 x n T2 G3 x n T3 x n Delay T2 Delay T3 Gain G2 Gain G3 x n T1 x n T2 x n T3 AA0449 ...

Page 262: ...C 12 DSP56009 User s Manual MOTOROLA Application Examples ...

Page 263: ... Filter Program C 6 EBARO and EBAR1 EMI Base Address Registers 4 7 EBDF EMI Data Register Buffer and Data Read Register Full 4 18 EBRB EMI Data Register Buffer 4 9 EBSY ECSR EMI Busy 4 19 EBW ECSR Data Bus Width 4 10 ECD0 ECD7 EMI Refresh Clock Divider 4 22 ECSR EMI Control Status Register 4 10 EDAR0 and EDRR1 EMI Data Read Registers 4 9 EDRF EMI Data Read Register Full 4 18 EDTM EMI DRAM Memory T...

Page 264: ...ebugging 4 22 ERED ERCR Refresh Enable When Debugging 4 22 EREF EMI Refresh Enable 4 23 ERTS EMI Read Trigger Select 4 19 ESTM0 ESTM3 EMI SRAM Memory Timing 4 20 EWL0 EWL2 EMI Word Length 4 11 EWOR EMI Write Offset Register 4 7 Examples C 1 External Memory Interface See Section 4 External Memory Interface EMI 1 10 External Memory Interface EMI Signals 2 7 F Fast Read or Write DRAM Access Timing 4 ...

Page 265: ... Transmit Data In Master Mode 5 30 Transmit Data In Slave Mode 5 27 I2C Bus Acknowledgment 5 22 I2C Mode 5 3 I2S Format 1 19 6 3 Input Output 1 16 Instruction Set Summary B 7 Inter Integrated Circuit Bus 1 18 5 3 Internal Exception Priorities SHI 5 7 Internal Interrupt Priorities SAI 6 9 Interrupt Sources 1 13 B 5 Starting Addresses 1 13 B 5 Interrupt and Mode Control Signals 2 10 Interrupt Priori...

Page 266: ...er Left Right Selection 6 12 RMST RCS Receiver Master 6 11 RRDF RCS Receiver Right Data Full 6 16 RWL0 RWL1 RCS Receiver Word Length Control 6 11 RX0 and RX1 Receive Data Registers 6 17 RXIE RCS Receiver Interrupt Enable 6 15 RXIL RCS Receiver Interrupt Location 6 15 S SAI 6 3 Baud Rate Control Register BRC 6 9 Baud Rate Generator 6 4 BRC Prescale Modulus Select 6 10 Prescaler Range 6 10 Reserved ...

Page 267: ... 5 Serial Peripheral Interface Bus 1 18 5 3 SHI 1 18 5 3 Block Diagram 5 4 Clock Control Register DSP Side 5 9 Clock Generator 5 5 Control Status Register DSP Side 5 13 Data Size 5 14 Exception Priorities 5 7 HCKR Clock Phase and Polarity Controls 5 10 Divider Modulus Select 5 12 Prescaler Rate Select 5 11 HCKR Filter Mode 5 12 HCSR Bus Error Interrupt Enable 5 16 FIFO Enable Control 5 14 Host Req...

Page 268: ...DIR TCS Transmitter Data Shift Direction 6 18 TDWE TCS Transmitter Data Word Expansion 6 20 Timing Diagrams for DRAM Addressing Modes 4 51 Timing Diagrams for SRAM Addressing Modes 4 64 Timing Skew 1 12 TLDE TCS Transmitter Left Data Empty 6 22 TMST TCS Transmitter Master 6 18 TRDE TCS Transmitter Right Data Empty 6 23 TREL TCS Transmitter Relative Timing 6 20 TWL0 TWL1 TCS Transmitter Word Length...

Page 269: ...MOTOROLA DSP56009 User s Manual C 1 APPENDIX C APPLICATION EXAMPLES ...

Page 270: ...cation Examples C 1 INTRODUCTION C 3 C 2 TYPICAL SYSTEM TOPOLOGY C 3 C 3 TYPICAL AUDIO APPLICATION C 4 C 4 PROGRAM OVERLAY C 5 C 5 SINGLE DELAY LINE C 5 C 6 EARLY REFLECTION FILTER C 6 C 7 TWO CHANNEL COMB FILTER C 7 C 8 3 TAP FIR FILTER C 10 ...

Page 271: ... bus 12 clock cycles per word transfer C 2 TYPICAL SYSTEM TOPOLOGY Figure C 1 shows the topology of a typical DSP audio application Figure C 1 Topology of DSP Typical Audio Application I2 S SONY I2 S SONY CONSUMER TR0 TR1 Stereo A D I2 S SONY REC0 SRAM DRAM EXTAL MD7 0 MA17 0 HOST SHI Stereo A D REC1 TR2 External Sinusoidal Clock Source I2 S SONY I2 S SONY GPIO AUDIO DSP PROCESSOR Stereo D A Stere...

Page 272: ...C3 Surround or DTS Figure C 2 Using the DSP56009 for Surround Sound Optional memory for soundfield effects DTS decoding buffering and booting DSP56009 SAI Tx SAI Tx ICE 958 Rx SAI Rx Host Microcontroller SHI EEPROM EMI SAI Tx Stereo DAC Stereo DAC Stereo DAC Right Left Center Subwoofer Surround L Surround R AA0444 not required for AC3 applications SRAM ...

Page 273: ... EDDR do N 2 end_OL loop to drive more N 2 triggers rep 1 nop movep x EDRR0 p r0 move previous read data to PMEM and trigger next read cycle end_OL bclr ERTS x ECSR turn off read triggers by EDRR read movep x EDRR0 p r0 move instruction N 1 to PMEM movep x EDRR0 p r0 move instruction N to PMEM bset GPIOR x GPIOR negate GPIO3 disable CS C 5 SINGLE DELAY LINE The following routine is an example of a...

Page 274: ...st read cycle clr a x r0 x0 y r4 y0 fetch 1st gain and 2nd delay do N 1 end_E movep x0 x EOR0 initiate next read trigger nop nop or other nop nop or other movep x EDRR0 x1 read current data mac x1 y0 a x r0 x0 y r4 y0 sum fetch next gain and offset nop nop or other end_E movep x SAMPLE x EDWR0 write current sample to delay line EWOR 0 nop nop or other movep x EDRR0 x1 read last data macr x1 y0 a c...

Page 275: ...fset zero dual_comb move Base_buff r0 pointer to base address values move Off_buff r1 pointer to offset delay values move Gain_buff r2 pointer to gains values move SAMPLE r4 pointer to left right samples move 0 x0 move 0 x1 x1 accumulates right comb outputs move 0 y1 x1 accumulates left comb outputs movep MODE x ECSR EINR 1 ERTS 0 do N end_comb move x1 b load right channel output movep x r0 x EBAR...

Page 276: ...y0 a b y1 compute input to delay buffer right and store left channel output movep a x EDWR1 insert input in delay buffer right point 3 insert nop or other instructions if required nop nop or other nop nop or other end comb move x1 b add x0 b y1 y out_left store left output move b x out_right store right output ...

Page 277: ...C 4 Two Channel Comb Filter Structure Delay T1 G1 Delay TN GN Comb Filters for One Channel Base Buffers Left Offset Buffers Left Gain Buffers Left Sample Left Base Buffers Right Offset Buffers Right Gain Buffers Right Sample Right r0 r0 r1 r2 r4 r1 r2 r4 X Y AA0448 ...

Page 278: ...pling rate 0 05 44100 2205 locations FIR Filter Assembler Code EMI mode increment EBAR on write operation movep x FIR_BASE x EBAR0 set FIR base address movep T1_OFF x EOR0 offset T1 and trigger mem read wait 3 DRAM or 1 SRAM inst cycles or do other tasks movep T2_OFF x EOR0 offset T2 and trigger mem read clr a x G1 x0 get G1 clear accumulator movep x EDRR0 y0 get x n T1 movep T3_OFF x EOR0 offset ...

Page 279: ...Application Examples MOTOROLA DSP56009 User s Manual C 11 Figure C 5 3 Tap FIR Filter Delay T1 Gain G1 y n G1 x n T1 G2 x n T2 G3 x n T3 x n Delay T2 Delay T3 Gain G2 Gain G3 x n T1 x n T2 x n T3 AA0449 ...

Page 280: ...C 12 DSP56009 User s Manual MOTOROLA Application Examples ...

Page 281: ... Filter Program C 6 EBARO and EBAR1 EMI Base Address Registers 4 7 EBDF EMI Data Register Buffer and Data Read Register Full 4 18 EBRB EMI Data Register Buffer 4 9 EBSY ECSR EMI Busy 4 19 EBW ECSR Data Bus Width 4 10 ECD0 ECD7 EMI Refresh Clock Divider 4 22 ECSR EMI Control Status Register 4 10 EDAR0 and EDRR1 EMI Data Read Registers 4 9 EDRF EMI Data Read Register Full 4 18 EDTM EMI DRAM Memory T...

Page 282: ...ebugging 4 22 ERED ERCR Refresh Enable When Debugging 4 22 EREF EMI Refresh Enable 4 23 ERTS EMI Read Trigger Select 4 19 ESTM0 ESTM3 EMI SRAM Memory Timing 4 20 EWL0 EWL2 EMI Word Length 4 11 EWOR EMI Write Offset Register 4 7 Examples C 1 External Memory Interface See Section 4 External Memory Interface EMI 1 10 External Memory Interface EMI Signals 2 7 F Fast Read or Write DRAM Access Timing 4 ...

Page 283: ... Transmit Data In Master Mode 5 30 Transmit Data In Slave Mode 5 27 I2C Bus Acknowledgment 5 22 I2C Mode 5 3 I2S Format 1 19 6 3 Input Output 1 16 Instruction Set Summary B 7 Inter Integrated Circuit Bus 1 18 5 3 Internal Exception Priorities SHI 5 7 Internal Interrupt Priorities SAI 6 9 Interrupt Sources 1 13 B 5 Starting Addresses 1 13 B 5 Interrupt and Mode Control Signals 2 10 Interrupt Priori...

Page 284: ...er Left Right Selection 6 12 RMST RCS Receiver Master 6 11 RRDF RCS Receiver Right Data Full 6 16 RWL0 RWL1 RCS Receiver Word Length Control 6 11 RX0 and RX1 Receive Data Registers 6 17 RXIE RCS Receiver Interrupt Enable 6 15 RXIL RCS Receiver Interrupt Location 6 15 S SAI 6 3 Baud Rate Control Register BRC 6 9 Baud Rate Generator 6 4 BRC Prescale Modulus Select 6 10 Prescaler Range 6 10 Reserved ...

Page 285: ... 5 Serial Peripheral Interface Bus 1 18 5 3 SHI 1 18 5 3 Block Diagram 5 4 Clock Control Register DSP Side 5 9 Clock Generator 5 5 Control Status Register DSP Side 5 13 Data Size 5 14 Exception Priorities 5 7 HCKR Clock Phase and Polarity Controls 5 10 Divider Modulus Select 5 12 Prescaler Rate Select 5 11 HCKR Filter Mode 5 12 HCSR Bus Error Interrupt Enable 5 16 FIFO Enable Control 5 14 Host Req...

Page 286: ...DIR TCS Transmitter Data Shift Direction 6 18 TDWE TCS Transmitter Data Word Expansion 6 20 Timing Diagrams for DRAM Addressing Modes 4 51 Timing Diagrams for SRAM Addressing Modes 4 64 Timing Skew 1 12 TLDE TCS Transmitter Left Data Empty 6 22 TMST TCS Transmitter Master 6 18 TRDE TCS Transmitter Right Data Empty 6 23 TREL TCS Transmitter Relative Timing 6 20 TWL0 TWL1 TCS Transmitter Word Length...

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