Motorola CPCI-9120, Reference Manual

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Daughter Card Details LA-1/QDR mezzanine
IXP/CPCI-9120 93
LA-1/QDR mezzanine
The IXP2400 has two independent SRAM controllers, each of which supports pipelined QDR
SSRAM and/or a coprocessor that adheres to QDR signaling.
One of the two QDR SRAM interfaces of the IXP2400 is used to provide 8 MB of on-board
QDR II SRAM, while the other is connected to an expansion slot through a 200-pin MEG-
Array® connector.
LA1-920/8M
LA1-920/8M is a QDR SRAM memory expansion mezzanine that is connected to Channel 1
of the IXP2400 memory controller. It contains 8 MB of QDR II SSRAM, and is expandable to
16 MB. This interface operates at 200 MHz.
I2C Interface
The IXP2400 detects the presence and type of the LA-1 module by interrogating the SPD
device on the LA-1 module. The information contained in the SPD on the LA-1 module may
be used to configure the IXP2400's QDR II Ch1 interface to meet the modules operating
requirements. The SPD device on the LA-1 module resides on the I2Cbus of the IXP2400. 2K
Serial EEPROMs, internally organized with 32 pages of 8 bytes each, shall be used to provide
board-specific information.