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Controls, Indicators and Connectors

Front Panel

IXP/CPCI-9120

Figure 16:

MSF Mezzanine Connector Pinout (rows D-E)

Summary of Contents for CPCI-9120

Page 1: ...lized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Ready to ship TAR certified secure asset solutions Expert team I Trust guarantee I 100 satisfaction All trademarks brand names and brands appearing herein are the property of their respective owners Fi...

Page 2: ...IXP CPCI 9120 Reference Guide 6806800A77B October 2006 ...

Page 3: ...ates of America Trademarks Motorola and the stylized M logo are trademarks of Motorola Inc registered in the U S Patent and Trademark Office All other names products or services mentioned in this document may be trademarks or registered trademarks of their respective holders ...

Page 4: ...ossible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Limited and Restricted Rights Legend If the documentation conta...

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Page 6: ...35 Ordering Information 36 Product Nomenclature 36 Order Numbers 36 2 Installation Action Plan 41 Preparing for Installation 42 Take Antistatic Precautions 42 Unpacking Kit Contents 42 Accessories 43 Requirements 44 Environmental Requirements 44 Power Requirements 46 Hardware Upgrades and Accessories 47 IO Daughtercard 47 IO 920 47 PMC Module 47 ...

Page 7: ...in Basic Hot Swap System 58 Installation in Full Hot Swap System 59 Removal from Full Hot Swap System 60 3 Controls Indicators and Connectors Front Panel 63 LEDs 65 Keys 66 Front Panel Reset 66 Connectors 66 D Type Subminiature Connector 66 On Board Connectors 67 CompactPCI Connectors 67 J1 and J2 67 J3 67 J4 68 J5 68 PrPMC Connectors 68 MSF Mezzanine Connector 69 LA 1 Mezzanine Connector 77 4 Dev...

Page 8: ... Programmable devices 86 BootROM Flash 86 User Flash 86 IBMU 86 ICMB 87 5 Daughter Card Details Media Switch Fabric mezzanine 91 IO 920 91 Quad Gigabit Ethernet MAC 91 Quad Gigabit Ethernet Transceiver 91 IO 920 Variants 92 Two 1000Base T PSB Single Slot Complex PSB Ethernet variant 92 LA 1 QDR mezzanine 93 LA1 920 8M 93 I2C Interface 93 6 Maps and Registers PCI memory map 97 SlowPort map 98 I2C m...

Page 9: ...er 108 Interrupt Mask Register 1 108 Interrupt Mask Register 2 109 Interrupt Mask Register 3 110 Interrupt Status Register 1 110 Interrupt Status Register 2 111 Interrupt Status Register 3 112 I2C MUX Reset Register 112 MAC EPLD IO 920 113 Variant ID 113 Version Number 113 Board Revision Number 113 PHY Reset Control Register 114 MUX Control Register 114 MAC PAUSE Address Register 115 MAC PAUSE Con...

Page 10: ...uments 132 Flash Image System FIS 133 Arguments 134 Arguments 135 Executing Programs from RedBoot 140 Arguments 140 8 Diagnostics Introduction 145 Requirements 145 Setup 145 Procedure 145 Configuring the Platform 146 Executing Diagnostics 146 Board Diagnostics Commands 146 A Troubleshooting Index ...

Page 11: ...10 IXP CPCI 9120 ...

Page 12: ...I Memory Map 97 Table 12 SlowPort Map 98 Table 13 NPU I2C Memory Map 101 Table 14 SENSE I2C Memory Map 102 Table 15 BIB I2C Memory Map 102 Table 16 Variant ID 103 Table 17 General Purpose EPLD Version Number 103 Table 18 General Purpose EPLD Board Revision Number 104 Table 19 User Flash Select 104 Table 20 CompactPCI Register 104 Table 21 PrPMC Register 105 Table 22 System Specific Register 106 Ta...

Page 13: ...egister 112 Table 35 MAC EPLD IO 920 Variant ID 113 Table 36 PHY Reset Control Register 114 Table 37 MAC PAUSE Address Register 115 Table 38 MAC PAUSE Control Register 115 Table 39 Interrupt Mask Register 116 Table 40 Interrupt Status Register 116 RedBoot Diagnostics Troubleshooting ...

Page 14: ...E 68 Figure 14 Jn4 Connector Pinout 69 Figure 15 MSF Mezzanine Connector Pinout rows A C 70 Figure 16 MSF Mezzanine Connector Pinout rows D E 71 Figure 17 MSF Mezzanine Connector Pinout rows F H 72 Figure 18 MSF Mezzanine Connector Pinout rows J K 73 Figure 19 MSF Mezzanine Connector Pinout MDI SlowPort I2C and JTAG rows A C 74 Figure 20 MSF Mezzanine Connector Pinout MDI SlowPort I2C and JTAG row...

Page 15: ...14 IXP CPCI 9120 Diagnostics Troubleshooting ...

Page 16: ...ides a basic overview of the features of the product and this manual Installation Outlines the installation requirements hardware accessories switch settings installation and removal procedures Controls Indicators and Connectors Describes the LEDs keys and connectors of the product Devices features and Data Paths Provides detailled information on the devices such as controllers CPU etc used on the...

Page 17: ...ld Used to emphasize a word Courier Used for on screen output Courier Bold Used to characterize user input and to separate it from system output Italics For references table and figure descriptions File Exit Notation for selecting a submenu text Notation for variables and keys text Notation for software buttons to click on the screen and parameter descriptions Repeated item e g node 1 node 2 node ...

Page 18: ...ct Peripheral Component Interconnect CPSB CompactPCI Packet Switching Backplane DDR Double Data Rate DRAM Dynamic Random Access Memory EEPROM E2 PROM Electrically Erasable Programmable Read Only Memory EPLD Erasable Programmable Logic Device ESD Electrostatic Discharge FRU Field Replaceable Unit GPIO General Purpose Input output I2C Inter IC Communication I O Input Output IBMU Intelligent Board Ma...

Page 19: ...C Network Interface Card NPU Network Processor Unit OC n Optical Carrier level n PCB Printed Circuit Board PCI Peripheral Component Interconnect PCISIG PCI Special Interest Group PHY Physical Layer Device PICMG PCI Industrial Computer Manufacturers Group PM Peripheral Management controller PMC PCI Mezzanine Card PPMC PrMC Processor PCI Mezzanine Card POS Packet Over Sonet POS PHY Packet Over Sonet...

Page 20: ...Random Access Memory SSTL_2 Stub Series Terminated logic for 2 5 Volts TBD To Be Decided UART Universal Asynchronous Receiver Transmitter VITA VMEbus International Trade Association Order No Revision Date Description 224535 420 000 AA September 2004 Initial Release 224535 420 000 AB December 2004 Updated Table of PCI Memory Map in Maps and Registers chapter Changes in Daughter Card Details chapter...

Page 21: ...ur correspondence please list your name position and company Be sure to include the title part number and revision of the manual and tell how you used it 6806800A77 A June 2006 Updated with Motorola logo formatted RedBoot commands change and update in Part Numbers in Ordering Information and Accessories name change to IXP CPCI 9120 RoHS compliance added to Standards table block diagrams updated Th...

Page 22: ...April 2003 Intel intel com Intel IXP2400 Network Processor Hardware Reference Manual April 2003 Linear Technology linear tech com LTC3728 Dual 550kHz 2 Phase Synchronous Step Down Switching Regulator Linear Technology linear tech com LTC3832 LTC3832 1 High Power Step Down synchronous DC DC controllers for low voltage operation Linear Technology linear tech com LTC1649 3 3V Input High Power Step Do...

Page 23: ...CPCI 9120 VITA Standards Organisation VSO vita com Processor PMC Standard VITA 32 Draft 1 0a Vitesse vitesse com VSC215 Baseboard Management Controller Data Manual Version 0 56 JAN 11 2001 Company www Document ...

Page 24: ... this manual is meant to complete the knowledge of a specialist and must not be taken as replacement for qualified personnel EMC The board has been tested in a standard Motorola ECC system and found to comply with the limits for a Class A digital device in this system pursuant to part 15 of the FCC Rules respectively EN 55022 Class A These limits are designed to provide reasonable protection again...

Page 25: ...swap full hot swap or high availability plat form is used and the system documentation explicitly includes appropriate guidelines For detailed information on hot swap support and the relevant safety notes see Installation in a Powered System Supporting Hot Swap page 57 Only install the board under hot swap conditions if the board is to be operated in slots for which hot swap is explicitly permitte...

Page 26: ...ral RJ 45 connectors which commonly serve as different inter faces RS 485 twisted pair Ethernet and telephone Connecting different interfaces e g Ethernet and RS 485 may damage the board Therefore make sure that you only con nect matching interfaces Furthermore take note of the following Clearly mark TPE Twisted Pair Ethernet connectors near your working area as network connectors TPE bushing of t...

Page 27: ...26 IXP CPCI 9120 ...

Page 28: ...ziertem Personal durchgeführt werden Die in diesem Handbuch enthaltenen Informationen dienen ausschließlich dazu das Wissen von Fachpersonal zu ergänzen können es aber in keinem Fall ersetzen EMV Das Board wurde entsprechend der PCI Spezifikation in einem Motorola ECC Standardsystem getestet Es erfüllt die für digitale Geräte der Klasse A gültigen Grenzwerte in einem solchen System gemäß den FCC R...

Page 29: ...enn die Basic Hot Swap Plattform die Full Hot Swap Plattform oder die High Availability Hot Swap Plattform verwendet wird und die Systembeschreibung dies ausdrücklich erlaubt Im Abschnitt Installation in a Powered System Supporting Hot Swap auf Seite 2 finden Sie ausführliche Informationen zur Unterstützung von Hot Swap und die entsprechenden Sicherheitshinweise Bauen Sie das Board nur dann unter ...

Page 30: ...nahme jedes Verbrauchers innerhalb der zulässigen Grenzwerte liegt siehe die technischen Daten des entsprechenden Verbrauchers RJ 45 Stecker Das CPU Board ist mit RJ 45 Steckern ausgestattet Dieser Stecker wird sowohl für Telefonanschlüsse als auch für Netzwerkkabel Twisted Pair Ethernet TPE verwendet Die Verwechslung dieser Anschlüsse kann sowohl das Telefon als auch das Board zerstören Beachten ...

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Page 32: ...1 Introduction ...

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Page 34: ...20 complies with the following industry standard specifications PICMG 2 0 R3 0 CompactPCI Core Specifications PICMG 2 1 R2 0 Hot Swap Specification PICMG 2 16 R1 0 Packet Switching Backplane Specification PICMG 2 9 R1 0 System Management Specification VITA 32 Processor PMC Figure 1 Single Slot Complex Functional Block Diagram change to Single NPU IXF1104 QUAD MAC µP INTERFACE EPLD 88E1145 QUAD PHY...

Page 35: ...t board complex comprises of the following features Single NPU Intel IXP2400 board at 600 MHz 256 MB SO DIMM DDRSDRAM with ECC 8 MB QDRSRAM with ECC onboard 8 MB QDRSRAM with ECC on accessory LA 1 mezzanine card 4 MB Boot Flash onboard 16 MB User Flash onboard 2 x PCI GbE MAC or 2 x SPI 3 GbE MAC on MSF mezzanine routed to PICMG 2 16 links ...

Page 36: ...esigned to meet the directive on the restriction of the use of certain hazardous substances in electrical and electronic equipment RoHS Directive 2002 95 EC Standard Description EN 60950 1 UL 60950 1 CSA 60950 1 IEC 60950 1 Legal safety requirements EN 55022 EN 55024 EN 300 386 FCC part 15 CISPR 22 EMC requirements on system level in a predefined Motorola sys tem ...

Page 37: ...ocal sales representative to check the possibility of combinations Table 1 Ordering Information Excerpt RoHS Part Number IXP CPCI 9120 xxx ccc Lyyy zz xxx SO DIMM DDRSDRAM size in Mbyte ccc QDRSRAM size in Mbyte Lyyy QDRSRAM size in Mbyte on LA 1 mezzanine card zz User Flash size in Mbyte Order No IXP CPCI 9120 Description 122754 IXP CPCI 9120 256 8 8 16 2GBE 2 16 6E Single NPU solution with 2x 10...

Page 38: ...rmation Excerpt Non RoHS Part Number Order No IXP CPCI 9120 Description Hardware Accessories IXP CPCI 9120 111013 ACC Serial Cable MD9 RD9 2 MD9 to DB9 Serial cable Note The Serial cable is used only for debug purpose 120460 ACC Serial Cable DTE 214451 CABLE 9 Rnd Shielded ...

Page 39: ...Ordering Information Introduction 38 IXP CPCI 9120 ...

Page 40: ...2 Installation ...

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Page 42: ...tallation Complete Begin Installation Unpack Kit Contents Check Kit Contents Check Physical Requirements Install PMC if required Check Power Requirements Take Anti Static Precautions Check Environmental Requirements Check Switch Settings Install in a Powered System Install IXP CPCI 9120 in a Non Powered System Install IXP CPCI 9120 in a Powered System No Power Up Yes ...

Page 43: ...g isolation gloves consider the following precautions Do not allow a circuit board or other components to make contact with nonconductors including your clothing Keep loose circuit boards inside or on top of conductive plastic bags Before touching a loose circuit board or component discharge static electricity Unpacking Kit Contents To unpack kit contents 1 Locate and put on an antistatic wristwra...

Page 44: ...table lists the accessories available for IXP CPCI 9120 Table 3 Accessories RoHS compliant Note The Serial cable is used only for debug purpose Table 4 Accessories Non RoHS compliant Note The Serial cable is used only for debug purpose ACC Serial Cable MD9 RD9 25E 122753 ACC Serial Port Y Adapter 5E 122734 ACC Serial Cable MD9 RD9 2 111013 ACC Serial Port Y Adapter 110973 ...

Page 45: ... the board and not to the component temperature Danger Do not operate the product outside the specified environmental limits High humidity and condensation may cause short circuits Make sure the product is completely dry and there is no moisture on any surface before applying power Do not operate the product below 0 C Table 5 Environmental Requirements Feature Operating Non Operating Temperature 0...

Page 46: ... of shocks 3 per direction 6 per axis total of 18 shocks Shape half sine Accelaration 15g Duration 11ms Number of shocks 3 per direction 6 per axis total of 18 shocks Free Fall 100 mm 3 axis 1 200 mm all edges and corners packed state Table 5 Environmental Requirements Feature Operating Non Operating ...

Page 47: ...alled If you want to install any accessories the load of the respective accessory has to be added to the load of the used board variant For information on the accessories power requirements refer to the documentation coming with the respective accessory or ask your local representative Table 6 Power Requirements IXP CPCI 9120 3 3V 5V 12V 12V Typical power requirements Min voltage 3 201V 4 85 11 4V...

Page 48: ...ers and Demulti plexers The IO 920 also houses an I O connector through which MDI lines from the Dual Gigabit Eth ernet controller are brought into the IO 920 Through multiplexers and demultiplexers Signals from two ports of the on board Quad PHY could be routed to the PSB Signals from the two ports of the baseboard Dual MAC 82546GB could be routed to the PSB PMC Module The CPCI 9120 provides one ...

Page 49: ...ails on how to install and remove PMC see Installing PMC and see Removing PMC page 53 LA1 920 8M LA1 920 8M is a QDR SRAM memory expansion mezzanine that is connected to Channel 1 of the IXP2400 memory controller It contains 8 MB of QDR II SSRAM and is expandable to 16 MB This interface operates at 200 MHz ...

Page 50: ...eset of the system from the Front panel Provide write protection to BootROM Flash and User Flash Figure 2 Location of Switches The board is delivered with the DIP switches set to ON position for SW2 and OFF for SW3 Table 7 Switch settings Switch Position Description SW2 1 OFF User Flash Write Disabled ON User Flash Write Enabled 2 OFF BootROM Flash Write Disabled ON BootROM Flash Write Enabled 3 R...

Page 51: ... PMC slot on IXP CPCI 9120 into which you are installing the PMC 4 Remove the PMC slot filler from front panel of IXP CPCI 9120 SW3 1 OFF Front Panel Reset enable ON Front Panel Reset disable 2 OFF PrPMC Monarch disable ON PrPMC Monarch enable 3 OFF Auto detect BMC or PM mode ON Force BMC mode 4 OFF Depends on Switch position 3 ON Force PM Table 7 Switch settings cont Switch Position Description T...

Page 52: ...re 3 Inserting the Bezel of the PMC into the Cutout on the Front Panel 6 Engage the connectors as shown in Figure 4 making sure they are seated com pletely Figure 4 Engaging the Connectors 7 Secure the PMC using screws provided Ensure that you screw the PMC from the rear side of using IXP CPCI 9120 through clearance holes as in Figure 5 ...

Page 53: ... using Screws provided Installation of the PMC on IXP CPCI 9120 is now complete A view of the IXP CPCI 9120 with the installed PMC is shown in Figure 6 Figure 6 IXP CPCI 9120 with the installed PMC Note Ensure that you cover the unused FrontPanel cutouts with filler panels ...

Page 54: ...ystem power 2 Remove IXP CPCI 9120 from the system as per the removal procedure detailed in section Installation in a Non Powered System 3 Carefully unscrew the PMC from the bottom of the IXP CPCI 9120 4 Carefully remove the PMC module from IXP CPCI 9120 by disengaging PMC connectors 5 Cover empty slot of IXP CPCI 9120 with PMC filler slot ...

Page 55: ... to install the board in a non powered system proceed as follows Caution Before touching integrated circuits make sure you are working in an ESD safe environ ment 1 Turn off system power 2 Check switch settings See Switch Settings 3 Insert board into the system by placing the top and bottom edges of the board in the card guides of the chassis as shown in Figure 7 Depending on the intended func tio...

Page 56: ...in the outward position 4 Check that the top and bottom injector ejector handles are in the outward position as shown by arrows in Figure 7 5 Slide the board into the chassis until you feel resistance approximately 1 4 inch short of full insertion The arrow in Figure 8 shows you the direction of required movement ...

Page 57: ...ctor handles to the inward position 7 Verify that the board is seated properly 8 Tighten the handle screws that secure the board to the chassis A zoomed view of the screw on the injector ejector handle is shown in Figure 9 Figure 9 Location of Screw on Injector Ejector Handle Plug in interface cables to the front panel connectors if applicable 9 Turn on system power ...

Page 58: ... defec tive boards can be repaired and systems can be reconfigured without disrupting system opera tion and with minimum operator intervention Caution Never hot swap the IXP CPCI 9120 unless a hot swap or high availability platform is used and the documentation of all installed boards and the system documentation explic itly include appropriate guidelines Live insertion extraction of the IXP CPCI ...

Page 59: ...nfigured 2 Ensure that IXP CPCI 9120 is inserted into a slot that does not have an RTB already installed 3 Insert board into powered system by placing the top and bottom edges of the board in the card guides of the chassis as shown in Figure 8 4 Check that the top and bottom injector ejector handles are in the outward position as shown by arrows in Figure 7 5 Slide the board into the chassis until...

Page 60: ...ct the IXP CPCI 9120 unless a hot swap or high availability platform is used and the documentation of all installed boards and the system documentation explicitly include appropriate guidelines Live insertion extraction of the IXP CPCI 9120 into from a System slot is not supported Before touching integrated circuits make sure that you are working in an ESD safe environment Removal from Basic Hot S...

Page 61: ...ll Hot Swap System To remove the board from a full hot swap system proceed as follows 1 Press red buttons on ejector injector handles to indicate board removal 2 Wait until blue hot swap LED is illuminated 3 Move ejector injector handles outwards Remove board from powered system ...

Page 62: ...3 Controls Indicators and Connectors ...

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Page 64: ...ront panel accommodates the following Hot swap status LED Blue LED placed above the lower ejector One bi color LED for power status Two bi color LEDs per gigabit ethernet port to indicate status and speed total eight Two general purpose user defined bi color LEDs Pinhole reset switch Serial port in a D type subminiature connector MD 9 Cutouts for one PMC Module The board is shipped with a filler p...

Page 65: ...of IXP CPCI 9120 For Description of IO Interfaces Switches and LEDs on Front Panel see following page Table 9 Description of IO Interfaces Switches and LEDs PMC Cut out for PMC module COM1 D type subminiature D type connector E1 Ethernet Port1 Bi color LED E2 Ethernet Port2 Bi color LED ...

Page 66: ...cription of IO Interfaces Switches and LEDs Table 10 Description of Front Panel LEDs LED Description Hot Swap Blue LED Hot Swap status LED When illuminated indicates that it is safe to extract the board from a live backplane Power Bi color LED Red Power unstable Yellow Power stable User LEDs Bi color LED1 User specific Bi color LED2 User specific Ethernet Speed LEDs LED off 10 Mbps link Blink Gree...

Page 67: ...reset switch is held in the active position Resets from the front panel can be disabled by means of switch settings see Description of Front Panel LEDs page 65 Connectors D Type Subminiature Connector A D type subminiature connector is used to facilitate debug and software development Modem controls are not supported on this connector Figure 11 D Subminiature Connector Pinout Green Link OK Yellow ...

Page 68: ...ezanine connector LA 1 mezzanine connector CompactPCI Connectors CompactPCI connectors J1 J2 J3 and J5 are present J1 and J2 The J1 and J2 CompactPCI connectors implement the CompactPCI 64 bit connector pinouts as specified by the CompactPCI specification These pinouts are hence not documented here J3 Figure 12 J3 Connector Pinout rows A E Note All pins of Row F are taken to GND ...

Page 69: ...PMC Connectors PMC slot connectors include the following Jn1 and Jn2 for the 32 bit PCI bus signals Jn3 for 64 bit PCI bus signals Jn4 for User I O signals Local bus signal pins on Jn1 Jn2 and Jn3 are assigned as specified by MMSC of IEEE in Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC P1386 1 Draft 2 4 Therefore these pinouts have not been documented ...

Page 70: ...inout MSF Mezzanine Connector Two 400 pin MEG Array connectors from FCI are used to connect the baseboard with the MSF mezzanine card One connector contains all MSF C bus LED signals and Power sig nals MDI signals I2C JTAG and SlowPort signals are routed through the second 400 pin connector ...

Page 71: ...Front Panel Controls Indicators and Connectors 70 IXP CPCI 9120 Figure 15 MSF Mezzanine Connector Pinout rows A C ...

Page 72: ...Controls Indicators and Connectors Front Panel IXP CPCI 9120 71 Figure 16 MSF Mezzanine Connector Pinout rows D E ...

Page 73: ...Front Panel Controls Indicators and Connectors 72 IXP CPCI 9120 Figure 17 MSF Mezzanine Connector Pinout rows F H ...

Page 74: ...Controls Indicators and Connectors Front Panel IXP CPCI 9120 73 Figure 18 MSF Mezzanine Connector Pinout rows J K ...

Page 75: ...Front Panel Controls Indicators and Connectors 74 IXP CPCI 9120 Figure 19 MSF Mezzanine Connector Pinout MDI SlowPort I2C and JTAG rows A C ...

Page 76: ...Controls Indicators and Connectors Front Panel IXP CPCI 9120 75 Figure 20 MSF Mezzanine Connector Pinout MDI SlowPort I2C and JTAG rows D E ...

Page 77: ...Front Panel Controls Indicators and Connectors 76 IXP CPCI 9120 Figure 21 MSF Mezzanine Connector Pinout MDI SlowPort I2C and JTAG rows F H ...

Page 78: ...igure 22 MSF Mezzanine Connector Pinout MDI SlowPort I2C and JTAG rows J K Note Rows B D F H and K are Ground LA 1 Mezzanine Connector A 200 pin MEG Array connector from FCI is used to connect the QDR II Channel 1 inter face of the IXP2400 to the LA 1 mezzanine card ...

Page 79: ...Front Panel Controls Indicators and Connectors 78 IXP CPCI 9120 Figure 23 LA 1 Pinout rows A C Figure 24 LA 1 Pinout rows D E ...

Page 80: ...Controls Indicators and Connectors Front Panel IXP CPCI 9120 79 Figure 25 LA 1 Pinout rows F H Figure 26 LA 1 Pinout rows J K ...

Page 81: ...Front Panel Controls Indicators and Connectors 80 IXP CPCI 9120 ...

Page 82: ...4 Devices features and Data Paths ...

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Page 84: ...y programmable multi threaded microengines for packet forwarding and traffic management on a single chip supporting 5 4 giga operations per second IXF1104 QUAD MAC µP INTERFACE EPLD 88E1145 QUAD PHY DMUX MSF MEZZANINE SITE IXP2400 82546GB LED EPLD RGMII RGMII RGMII RGMII MDI MDI MDI GP EPLD BOOT ROM Flash USER FLASH IBMU SO DIMM Up to 512 MB QDR II SSRAM Up to 16 MB LA 1 Mezzanine SITE LA1 920 8M ...

Page 85: ...CI 9120 QDR SRAM Interface The IXP2400 has two independent SRAM controllers each of which supports pipelined QDR and QDR II SSRAM and or a coprocessor that adheres to QDR signaling One of the two QDR SRAM interfaces of the IXP2400 is used to provide 8 MB of on board QDR II SSRAM while the other is connected to an expansion slot On IXP CPCI 9120 the QDR interfaces of IXP2400 operate at 200 MHz Medi...

Page 86: ...oller for Con trol plane processing The 82546GB provides two PICMG 2 16 links on a Packet Switching Backplane PSB Processor PMC The IXP CPCI 9120 provides one VITA 32 compliant Processor PMC site on to which addi tional I O or processing power may be added This site is connected to the IXP2400 via the local PCI bus Processor PMCs when mounted on this site may be configured in monarch or non monarc...

Page 87: ...tching backplane The Intel 82546GB Dual Port Gigabit Ethernet Controller described earlier provides the dual PICMG 2 16 links Programmable devices BootROM Flash The IXP CPCI 9120 provides 4 MB of BootROM Flash Support for up to 8 MB of BootROM Flash is provided on the IXP CPCI 9120 User Flash An Intel StrataFlash is used to provide 16 MB of User Flash Up to 32 MB of User Flash can be accommodated ...

Page 88: ...d IBMU is mapped on to IXP2400 s SlowPort area Communication between the IPMI control ler and the IXP2400 is achieved through the General Purpose EPLD which translates slow port signals into X bus and vice versa ICMB ICMB is an RS 485 based bus used to connect the BMCs of two or more chassis The ICMB port of IXP CPCI 9120 is located on the RTB Connections from the IPMI controller are routed throug...

Page 89: ...Block Diagram Devices features and Data Paths 88 IXP CPCI 9120 ...

Page 90: ...5 Daughter Card Details ...

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Page 92: ...System Packet Interface Phase 3 SPI3 media interface and the PHY interfaces are Serializer Deserializer SerDes with GBIC support Gigabit Media Inde pendent Interface GMII or Reduced GMII RGMII selected on a per port basis Signals from the SPI 3 interface of the IXF1104 are routed to the MSF interface of the IXP2400 on the baseboard through a 400 pin connector Quad Gigabit Ethernet Transceiver The ...

Page 93: ...ought into the IO 920 Through multiplexers and demultiplexers signals from the on board PHY and the baseboard Dual MAC 82546GB can either be routed to the PSB The muxes are controlled from slowport through EPLD Two 1000Base T PSB Single Slot Complex PSB Ethernet variant In this variant two of the MDI outputs are routed to the PSB ...

Page 94: ...pansion mezzanine that is connected to Channel 1 of the IXP2400 memory controller It contains 8 MB of QDR II SSRAM and is expandable to 16 MB This interface operates at 200 MHz I2C Interface The IXP2400 detects the presence and type of the LA 1 module by interrogating the SPD device on the LA 1 module The information contained in the SPD on the LA 1 module may be used to configure the IXP2400 s QD...

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Page 96: ...6 Maps and Registers ...

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Page 98: ...ap IXP CPCI 9120 97 PCI memory map Table 11 PCI Memory Map PCI device Description IDSEL Device number 82546GB Dual LAN controller 17 1 PrPMC First PCI agent of the PrPMC 18 2 PrPMC Second PCI agent of the PrPMC 19 3 IXP2400 NPU 22 6 ...

Page 99: ...rovides basic PrPMC information System specific register C600 0030 Contains information on mezzanine boards and RTB installed User LED control register C600 0050 KCS SMIC Data 0 Register KSD0 C600 0060 Register in the IPMI Controller VSC215 KCS SMIC Status 0 Register KSS0 C600 0061 Register in the IPMI Controller VSC215 KCS SMIC Data 1 Register KSD1 C600 0070 Register in the IPMI Controller VSC215...

Page 100: ...et Register C700 000F Resets the I2C MUX MAC EPLD Microprocessor interface1 C600 4000 C600 5FFF Microprocessor Interface of IXF1104 Variant ID C600 3010 MSF variant indicated here Version Number C600 3011 EPLD version number Board revision Number C600 3012 PHY reset Control register C600 3020 Provides ability to reset the PHY Reserved C600 3030 Reserved Reserved C600 3031 Reserved Reserved C600 30...

Page 101: ...SlowPort address for offset 50C is C600 5430 derived as C6004000 0x50C 4 C6004000 1430 C6005430 Interrupt Mask Register C700 000B Provides the ability to mask inter rupts generated by the PHY and MAC Interrupt Status Register C700 000F Provides status of interrupts issued by the PHY and MAC Table 12 SlowPort Map Device SlowPort Address Description ...

Page 102: ...ory map NPU I2C memory map Table 13 NPU I2C Memory Map Device Description I2C Address RTC Real Time Clock A0 SO DIMM SPD SO DIMM on IXP CPCI 9120 A2 MSF EEPROM EEPROM A4 I2C MUX Multiplexer for RTC E0 LA 1 site LA 1 on IXP CPCI 9120 A8 PrPMC site PrPMC site AC ...

Page 103: ...I2C Memory Map Table 14 SENSE I2C Memory Map Device Description I2C Address LM87 Voltage Temperature sensor on IXP CPCI 9120 5A Table 15 BIB I2C Memory Map Device Description I2C Address 24LC128 Board BIB A0 AT24C02 IBMU BIB AE ...

Page 104: ...dicates the amount of on board QDR II SSRAM installed Version Number Address C600 0001 Type Read only This register indicates the EPLD revision number Table 16 Variant ID Bit Description Access 3 2 00 8 MB on board QDR II SSRAM RO 01 16 MB on board QDR II SSRAM 1X RFU 1 0 00 IXP CPCI 9120 RO 01 RFU 10 RFU 11 RFU Table 17 General Purpose EPLD Version Number Bit Description Access 3 0 EPLD revision ...

Page 105: ...ess C600 0010 Type Read Write This register provides status of signals related to CompactPCI and hot swap It also provides control of the hot swap blue LED Table 18 General Purpose EPLD Board Revision Number Bit Description Access 3 0 Board revision number RO Table 19 User Flash Select Bit Description Access 0 0 Selects BootROM Flash R W 1 Selects User Flash Reset value 0 Table 20 CompactPCI Regis...

Page 106: ...LED Off R W 1 Blue LED On Reset value 1 Table 20 CompactPCI Register Bit Description Access Table 21 PrPMC Register Bit Description Access 1 EREADY control Note that the EREADY pin of the EPLD is configured as an output when the PrPMC is made Monarch Otherwise it is an input on the EPLD EREADY OUT If Processor PMC is a Monarch WO Reset value 0 EREADY IN If Processor PMC is a non Monarch RO 0 Non m...

Page 107: ...gister Bit Description Access 3 0 PrPMC Mezzanine Card Present RO 1 PrPMC Mezzanine Card Absent 2 0 Reserved RO 1 Reserved 1 0 MSF Mezzanine Card Present RO 1 MSF Mezzanine Card Absent 0 0 LA1 Mezzanine Card Present RO 1 LA1 Mezzanine Card Absent Table 23 User LED Control Register Bit Description Access 3 2 00 User LED2 does not glow R W 01 User LED2 glows green 10 User LED2 glows yellow 11 User L...

Page 108: ...le and Watchdog Reset Enable Register Address C600 00B0 Type Read Write This register provides a means to enable or disable the watchdog timer as well as to enable or disable the watchdog interrupt to reset the board Table 24 Watchdog Timer Register Bit Description Access 0 0 1 Access read or write to this register refreshes the Watch Dog Timer W Table 25 Watchdog Timer Interrupt Clear Register Bi...

Page 109: ... of 3 secs 101 Refresh Time of 4 secs 100 Refresh Time of 5 secs 011 Refresh Time of 6 secs 010 Refresh Time of 7 secs 001 Refresh Time of 8 secs 000 Refresh Time of 9 secs Reset Value 111 RW Table 28 Interrupt Mask Register 1 Bit Description Access 7 0 Reserved 1 Reserved Reset value 1 R W 6 0 MSF Interrupt is not masked 1 MSF Interrupt is masked Reset value 1 R W 5 0 LA1 Interrupt is not masked ...

Page 110: ...upt B is masked Reset value 1 R W 0 0 82546 Interrupt A is not masked 1 82546 Interrupt A is masked Reset value 1 R W Table 28 Interrupt Mask Register 1 Bit Description Access Table 29 Interrupt Mask Register 2 Bit Description Access 7 0 PMC Interrupt D is not masked 1 PMC Interrupt D is masked Reset value 1 R W 6 0 PMC Interrupt C is not masked 1 PMC Interrupt C is masked R W 5 0 PMC Interrupt B ...

Page 111: ...three In terrupt status registers to determine the interrupt source 1 0 RFU 1 RFU R W 0 0 RFU 1 RFU Reset value 1 R W Table 29 Interrupt Mask Register 2 Bit Description Access Table 30 Interrupt Mask Register 3 Bit Description Access 2 0 Voltage Monitor Interrupt is not masked 1 Voltage Monitor Interrupt is masked Reset value 1 R W 1 0 Watchdog Timer Interrupt is not masked 1 Watchdog Timer Interr...

Page 112: ...active RO 4 0 IPMI Interrupt 2 is active 1 IPMI Interrupt 2 is not active RO 3 0 IPMI Interrupt 1 is active 1 IPMI Interrupt 1 is not active RO 2 0 IPMI Interrupt 0 is active 1 IPMI Interrupt 0 is not active RO 1 0 82546 Interrupt B is active 1 82546 Interrupt B is not active RO 0 0 82546 Interrupt A is active 1 82546 Interrupt A is not active RO Table 32 Interrupt Status Register 2 Bit Descriptio...

Page 113: ...stuck in a LOW state Pulling the RESET pin LOW resets the I2C state machine and causes all the channels to be deselected as does the internal power on reset func tion 3 RFU 2 RFU 1 RFU 0 RFU Table 32 Interrupt Status Register 2 Bit Description Access Table 33 Interrupt Status Register 3 Bit Description Access 3 0 Ejector handles are open 1 Ejector handles are closed RO 2 0 Voltage Monitor Interrup...

Page 114: ...1 Type Read only This register indicates the EPLD revision number Board Revision Number Address C600 3012 Type Read only This register indicates the board revision number Table 35 MAC EPLD IO 920 Variant ID Bit Description Access 3 0 0000 IO 920 Front variant RO 0001 IO 920 Rear variant 0010 RFU 0011 RFU 0100 2 16 Variant 0101 to 1111 RFU Figure 28 MAC EPLD IO 920 Version Number Bit Description Ac...

Page 115: ...ddress C600 3040 Type Read Write This register controls the flow of Ethernet signals between the RTB and PSB Figure 29 Board revision Number Bit Description Access 3 0 Board Revision number for the current board RO Table 36 PHY Reset Control Register Bit Description Access 0 0 Quad PHY Reset is asserted 1 Quad PHY Reset is de asserted Reset value 0 R W Figure 30 Mux Control Register Bit Descriptio...

Page 116: ...errupt Mask Register Address C700 000B Type Read Write Interrupts generated from the PHY may be masked through this register Table 37 MAC PAUSE Address Register Bit Description Access 2 0 000 XON Packet on all IXF1104 Ports 001 XOFF Packet on Port 0 010 XOFF Packet on Port 1 011 XOFF Packet on Port 2 100 XOFF Packet on Port 3 110 101 Reserved 111 XOFF Packet on all Ports Reset value 000 RW Table 3...

Page 117: ...t masked 1 PHY Port 2 Interrupt is masked Reset value 1 R W 1 0 PHY Port 1 Interrupt is not masked 1 PHY Port 1 Interrupt is not active Reset value 1 R W 0 0 PHY Port 0 Interrupt is not masked 1 PHY Port 0 Interrupt is masked Reset value 1 R W Table 40 Interrupt Status Register Bit Description Access 3 0 PHY Port 3 Interrupt is active 1 PHY Port 3 Interrupt is not active RO 2 0 PHY Port 2 Interrup...

Page 118: ...7 RedBoot ...

Page 119: ......

Page 120: ...RedBoot Action Plan IXP CPCI 9120 119 Action Plan ...

Page 121: ...the firmware The main purpose of RedBoot for IXP CPCI 9120 is to boot VxWorks Diagnostics and Linux The RedBoot is also used to write an OS image to a determined location on the Flash Currently RedBoot runs at 600 MHz Certain parameters can be stored in Flash and are retained after reboot These parameters can be changed using the RedBoot commands The serial interface setting is 9600 bps with 8 N 1...

Page 122: ...l nl design intelxscale dev_tools 010413 The file to be downloaded is i686 pc linux gnulibc2 1 x xscale elf tar Z 4 Uncompress the file i686 pc linux gnulibc2 1 x xscale elf tar Z 5 Untar the file i686 pc linux gnulibc2 1 x xscale elf tar 6 Verify whether a directory named H i686 pc linux gnulibc2 1 has been created 7 Add the directory H i686 pc linux gnulibc2 1 bin to the PATH variable 8 In the S...

Page 123: ... image to the boot flash using fis create command at address 0xC4000000 RedBoot fis create RedBoot b 0x400000 f 0xc4000000 l 0x40000 Diagnostics 1 Execute boot_flash command to switch to boot flash RedBoot boot_flash 2 Load the diag bin image to SDRAM using load command RedBoot load diag bin b 0x400000 3 Program the diag image to the boot flash using fis create command at address 0xC4100000 RedBoo...

Page 124: ... is configured before using ping Arguments v Be verbose displaying information about each packet sent n count Controls the number of packets to be sent Default is 10 if n is not specified t timeout How long to wait for the round trip to complete specified in milliseconds Default is 1000ms 1 second r rate How fast to deliver packets i e time between successive sends Default is 1000ms 1 second Speci...

Page 125: ...s of memory in hexadecimal format It is most useful for examining a segment of RAM or flash Note that it could be detrimental if used on memory mapped hardware registers The memory is displayed at most sixteen bytes per line first as the raw hex value followed by an ASCII interpretation of the data RedBoot du b 0x100 l 0x80 0x00000100 3C60 0004 6063 2000 7C68 03A6 4E80 0020 c h N 0x00000110 0000 0...

Page 126: ...used to switch to user flash RedBoot user_flash help SYNTAX help topic DESCRIPTION This command is used for help Detect I2C devices SYNTAX i2cdetect DESCRIPTION This command detects and displays all I2C devices RedBoot i2cdetect Detecting I2C devices I2C MUX is present PrPMC is not present RTB is present LA 1 MEZZANINE is not present MSF MEZZANINE is present SO DIMM SPD is present RTC is present R...

Page 127: ...4 0 555555 RedBoot Read from I2C device SYNTAX i2c_read slave address offset count DESCRIPTION Read from I2C for the specified slave address and offset RedBoot i2c_read 0xa4 0 6 55 55 55 0 0 0 RedBoot Read byte SYNTAX inb address DESCRIPTION This command reads the value of the byte present at address RedBoot inb 0xc6000003 0x1 RedBoot Read dword SYNTAX inl address DESCRIPTION This command reads th...

Page 128: ...n Data field is optional and depends on IPMI command The following is an example of the GetDeviceID command RedBoot ipmi 6 1 0 LUN NetFn 0x0 0x7 Command 0x1 Completion Code 0x0 0x1 0x81 0x99 0x7 0x1 0x2b 0x48 0xe 0x0 0xc 0 x20 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0 x0 RedBoot Write Byte SYNTAX outb address value DESCRIPTION This command writes value to byte address RedBoot outb 0xc6000000 0x0 Write...

Page 129: ...Configuration Register for the specified values of the bus num ber device number function and the register number RedBoot pci_config_read b 0 d 2 f 0 r 2 0x12298086 RedBoot Write PCI config Registers SYNTAX pci_config_write b bus d device f func r reg v data DESCRIPTION This command writes data to the PCI Configuration Register for the specified values of the bus number device number function and ...

Page 130: ...I base address 1 0x00001081 0x18 PCI base address 2 0x04100000 0x1c PCI base address 3 0x00000000 0x20 PCI base address 4 0x00000000 0x24 PCI base address 5 0x00000000 0x28 PCI CardBus CIS pointer 0x00000000 0x2c PCI subsystem IDs 0x00000000 0x30 PCI expansion rom address 0x00000000 0x34 PCI Capabilities 0x000000dc 0x3c PCI interrupt line 0x00 0x3d PCI interrupt pin 0x01 0x3e PCI minimum grant 0x0...

Page 131: ... FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 0000 FFFF FFFF 0000 0800 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 0602 0120 4000 110F FFFF 0120 4000 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 8A22 RedBoot Read EEPROM SYNTAX read_eeprom DESCRIPTION This command reads 128 bytes of 82546 EEPROM RedBoot read_eeprom BEBA BEBA BEBA FFFF FFFF FFFF FFFF FFFF FFFF FFFF 4603 1004 124B 1079 8086 317...

Page 132: ...ev 2 IO 920 BOARD Rev 10 IO 920 EPLD Rev 2 82546_backplane SYNTAX 82546_backplane DESCRIPTION This command is used to have control plane connectivity to the back plane RedBoot 82546_backplane RedBoot ixf_backplane SYNTAX ixf_backplane DESCRIPTION This command is used to have data plane connectivity to the back plane RedBoot ixf_backplane RedBoot ...

Page 133: ...t would interfere with the protocol b Specify the location in memory to which the file should be loaded Executable images nor mally load at the location to which the file was linked This option allows the file to be loaded to a specific memory location possibly overriding any assumed location r Download raw data Normally the load command is used to load executable images into memory This option al...

Page 134: ...option is specified the image checksum is displayed instead of the Mem Addr field If the d option is specified the image datalength is displayed instead of the length amount of flash used The datalength is the length of data within the allocated flash image actually being used for data RedBoot fis list Name FLASH addr Mem addr Length Entry point RedBoot 0xC4000000 0x00300000 0x00040000 0x00000000 ...

Page 135: ...mmand to load an image into RAM and then the fis create command to write it to flash Arguments name The name of the file as shown in the FIS directory b The location in RAM used to obtain the image This is a required option l The length of the image If the image already exists then the length is inferred from when the image was previously created If specified and the image exists it must match the...

Page 136: ... about to program RedBoot at 0xc4000000 0xc403ffff from 0x00400000 are you sure y n y Your action requires changes to BootMonitor blocks Continue are you sure y n y Make sure flash is unlocked Erase from 0xc4000000 0xc4040000 Program from 0x00400000 0x00440000 at 0xc4000000 Lock from 0xc4000000 0xc4040000 Unlock from 0xc4fe0000 0xc5000000 Erase from 0xc4fe0000 0xc5000000 Program from 0x0ff5b000 0x...

Page 137: ...t lock a portion of flash memory to prevent accidental overwriting of images In order to make make any modifications to the flash a matching unlock command must be issued This command is optional and will only be provided on hardware which can support write protection of the flash space RedBoot fis lock f 0xC4040000 l 0x20000 Lock from 0xC4040000 0xC4060000 SYNTAX fis unlock f flash_addr l length ...

Page 138: ...n nickname value nickname value DESCRIPTION Manages configuration kept in FLASH memory A Reset has to be issued for the changed parameters to take effect Options i This option prompts the user whether to reset the configuration values to default state or not Example RedBoot fconfig i Initialize non volatile configuration are you sure y n n Run script at boot false Use BOOTP for network configurati...

Page 139: ...tion false Local IP address 10 208 32 99 Default server IP address 10 208 33 50 Network debug false Default network device i82546_gb0 RedBoot nickname value Nicknames provide a quick way to set a single entry using the format If no value is supplied the command will list and prompt for only that entry If a value is supplied then the entry will be set to that value You will be prompted to write the...

Page 140: ...on volatile configuration are you sure y n y Unlock from 0xc43c0000 0xc43e0000 Erase from 0xc43c0000 0xc43e0000 Program from 0x00059d80 0x0005ad80 at 0xc43df000 Lock from 0xc43c0000 0xc43e0000 RedBoot Note Provide IP address as per the available network configuration ...

Page 141: ...ecute a program The format of the go command is RedBoot go w time location Execution will begin at location if specified Otherwise the entry point of the last image loaded will be used The w option gives the user time seconds before execution begins The execution may be aborted by typing Ctrl C on the console This mode would typically be used in startup scripts 2 exec Execute a Linux kernel image ...

Page 142: ...RedBoot Executing Programs from RedBoot IXP CPCI 9120 141 ...

Page 143: ...Executing Programs from RedBoot RedBoot 142 IXP CPCI 9120 ...

Page 144: ...8 Diagnostics ...

Page 145: ......

Page 146: ...on progam such as HyperTerminal that runs on Windows The settings on the terminal emulation program are given below Bits per second bit rate 9600 bps Data bits 8 Parity None Stop bits 1 Flow control None Setup 1 Install IXP CPCI 9120 see IXP CPCI 9120 Board Installation page 54 2 Connect the cable ACC CABLE MD9 D9 2 see Ordering Information Excerpt Non RoHS Part Number page 37 to the PC or console...

Page 147: ...t addr and size it displays the contents of the last address when the command was issued Listed below are the different Board Diagnostics commands for IXP CPCI 9120 t test t test DESCRIPTION Displays a list of test commands within the diagnostics image SYNTAX test interface module PARAMETERS interface module is the interface or module that has to be tested Example The following command invokes the...

Page 148: ...igh val fill mem Arguments Hex Hex Hex banner DESCRIPTION Prints a banner containing basic hardware and software information SYNTAX Banner Example Banner exit reset DESCRIPTION reset command SYNTAX Exit Reset Example Exit Reset tf DESCRIPTION Enables test flags Causes given device to be included or excluded from tests in the test all command SYNTAX tf test_type_ID status PARAMETERS test_type_id te...

Page 149: ...splays the contents of memory that starts at address addr and is size bytes long SYNTAX p pb pw pd addr size PARAMETERS addr starting address of a memory block size length of a memory block Example p 800000 80 pb 500000 pw 300000 pd 000 c DESCRIPTION Interactively changes the contents of a specified memory address SYNTAX c addr PARAMETERS addr memory address that will change Example c 1000000 cb 2...

Page 150: ...est PARAMETERS low address in memory where the block begins high address in memory where the block ends dest address in memory where the block should be copied to Example blockcopy 800000 800100 400000 fill DESCRIPTION Fills a block of memory with the specified value SYNTAX fill low high val PARAMETERS low address in memory where the block begins high address in memory where the block ends val val...

Page 151: ...y information on the console 0 display information on the console 1 run in silent mode Example memrb 1 0 0 io DESCRIPTION Reads r or writes w a byte b word w or dword d from to a PCI IO SYNTAX io rw bwd iorb addr rept silent iowb addr data rept iorw addr rept silent ioww addr data rept iord addr rept silent iowd addr data rept PARAMETERS addr memory address that will be written to read from rept r...

Page 152: ... data cfgrd bus device function addr cfgwd bus device function addr data PARAMETERS bus PCI bus number of the device device device number of the device function function number of the device addr the nth byte word dword required data data to write to the memory address Example cfgrb 1 0 0 mac DESCRIPTION Read all read write the MAC registers Note MAC is IXF1104 in IO 920 SYNTAX mac r ra w Example ...

Page 153: ...nside the I2C device count number of bytes read decimal format Example i2cread A2 0 10 I2cwrite DESCRIPTION Writes string data into the memory of an I2C device The valid addresses are a0 a2 a4 a6 a8 ae and ac Caution Note The device is capable of a limited number of writes Use only as needed he SYNTAX i2cwrite slave_addr offset_addr data PARAMETERS slave_addr address of the I2C device on the bus o...

Page 154: ...sable instruction cache SYNTAX ion Enable instruction cache ioff Disable instruction cache Example ion ioff createscript DESCRIPTION Allows a test script to be written and stored in flash and run Note To finish the script just enter a null string SYNTAX createscript Example createscript viewscript DESCRIPTION Displays the test script stored in the flash SYNTAX viewscript Example viewScript ...

Page 155: ...e data loops verbose PARAMETERS option indicates the memory type to test Can be set as follows s SRAM memory test channel 0 and 1 default s0 SRAM memory test channel 0 s1 SRAM memory test channel 1 d DRAM memory test a all memory types h help test_option sets the test method to use Can be set as follows w1 walking one test w0 walking zero test w both walking tests c5 checker 0x5A5A5A5A test ca che...

Page 156: ...T tests The test cover all types of UART in the system User intervention is required to finish the test SYNTAX t uart command PARAMETERS command indicates a test method to perform Can be set as follows d dump all UART readable registers r UART register test q UART non FIFO polling test j UART non FIFO interrupt test p UART FIFO polling test i UART FIFO interrupt test a all UART tests h help Exampl...

Page 157: ...on indicates the test to perform Can be set as follows d GPIO detection test r GPIO register test e GPIO edge detection test l GPIO level detection test a all GPIO tests h help Example t gpio l t timers DESCRIPTION Performs timer tests The tests cover three timers and watchdog timers Note Watchdog Timer test causes the system to reset SYNTAX t timers option PARAMETERS option indicates a test optio...

Page 158: ... test a all tests h help offset offset in the I2C device serial eeprom IO 920 data data to write into I2C device 0 FF Example t i2c p 0 t ueng DESCRIPTION Performs a microengine uEngine test SYNTAX t ueng option microengine loop PARAMETERS option indicates a test method to perform Can be set as follows s context tests r register test c control store test t timers and counters test a all uEngine te...

Page 159: ...s present SYNTAX t pci Example t pci t sf DESCRIPTION Performs MSF Register test SYNTAX t sf Example tsf t flash DESCRIPTION Performs flash lock test SYNTAX t flash Example t flash t epld DESCRIPTION Performs epld Register tests SYNTAX t epld option PARAMETERS option indicates the test to perform Can be set as follows d slowport register default test r slowport register write read test a all slowp...

Page 160: ...erform Can be set as follows p Ethernet NIC 82546 Presence Test r Ethernet NIC 82546 Register Test l Ethernet NIC 82546 Link Test i Ethernet NIC 82546 Internal Loopback Test h help Example t nic p t dma DESCRIPTION Performs the PCI DMA tests on both the channels SYNTAX t dma Example t dma t ipmi DESCRIPTION Detects the presence of IPMI controller SYNTAX t ipmi Example t ipmi ...

Page 161: ...Introduction Diagnostics 160 IXP CPCI 9120 t spi3 DESCRIPTION Performs the spi3 interface test between IXDP2400 and IXF1104 SYNTAX t spi3 Example t spi3 ...

Page 162: ...A Troubleshooting ...

Page 163: ......

Page 164: ...low control Stop bits Start bits Check proper cables Problem Possible Reason Solution OS does not boot Boot device is not partitioned according to used operating system Wrong configuration of boot devices Check partition according to operating system s needs Configure boot devices correctly Front panel reset does not work Function is disabled Ensure that position 1 of SW3 is OFF PPMC installed doe...

Page 165: ...ard runs unstable Disregard of environmental requirements Drivers are missing faulty or do not match hardware Board defect Ensure that temperature inside the system stays within specified ranges Improve cooling inside the system if necessary Ensure that other envi ronmental requirements such as moisture or altitude are satisfied Reinstall appropriate drivers Replace board Problem Possible Reason S...

Page 166: ...3 ESD 54 F Front Panel 63 I I2C bus 86 IBMU 86 Injector ejector levers 55 58 Installation CPCI 9120 54 CPCI 9120 hot swap 58 non powered system 54 Unpack Kit 42 Installing PMC 50 IO 920 47 IO 920 Variants 92 K Keys 66 Front panel Reset 66 L LA 1 Mezzanine connector 77 LA 1 QDR mezzanine LA1 920 8M 93 LED hot swap 57 M Maps 95 I2C memory map 101 NPU I2C memory map 101 PCI memory map 97 SENSE I2C me...

Page 167: ...rupt Status Register 2 111 Interrupt Status Register 3 112 PrPMC register 105 System specific register 105 User Flash Select 104 User LED Control register 106 Variant ID 103 Version Number 103 Watchdog Timer Register 107 GeneralPurpose EPLD CompactPCI Register 104 MAC EPLD IO 920 Board Revision Number 113 Interrupt Mask Register 115 Interrupt Status Register 116 MAC PAUSE Address Register 115 MAC ...

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