5-8
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Connector Pin Assignments
5
EIDE (ATA-2),
Primary Channel
PDREQ-
Drive DMA request
PDACK-
Drive DMA acknowledge
PIOR-
Drive I/O read
PIOW-
Drive I/O write
PIORDY-
Indicates drive is ready for I/O cycle(s)
PD[15:0]
Drive data lines, bits 15 -- 0
DRSTDRV
Reset signal to drive
PCS1
Chip select drive 0, also command register block select
PCS3
Chip select drive 1, also command register block select
PA[2:0]
Drive register and data port address lines
PINTRQ
Drive interrupt request
PDASP
Drive active
PDIAG
Drive inter-communication
Video Signals
RED
Red signal
GRN
Green signal
BLU
Blue Signal
HSYNC
Horizontal synchronization
VSYNC
Vertical synchronization
DDCCLK
Display Data Channel clock signal for DDC2 support
DDCDAT
Display Data Channel data signal for DDC2 support
Table 5-7. CPN5365 Rear I/O Connector (J5)
Pin F
E
D
C
B
A
22
GND
SRSTDRV-
SINTRQ
KBDDAT
ERX0+
ETX0+
21
GND
SCS1-
SDACK-
KBDCLK
ERX0-
ETX0-
20
GND
SCS3-
SIORDY
RESET_IN
AUXVCC
GND
19
GND
SDREQ
SIOW-
MDAT
ERX1+
ETX1+
Table 5-6. Signal Descriptions for the Backplane Connector (J4)
Signal
Signal
Mnemonic
Signal Description