20
Pulse Accumulator Edge Triggered Interrupt:
Operation
This section describes how to set up the Pulse Accumulator for edge triggered
operation. The Pulse Accumulator is enabled by setting the Pulse Accumulator Enable
(PAEN) in _H12PACTL to one. There are two other control bits in _H12PACTL, PAMOD
and PEDGE.
When PAMOD equals zero the pulse accumulator is in event counter mode, when it is
one it is in gated time accumulation mode. PEDGE has different effects based on
the state of PAMOD.
When PAMOD equals zero:
If PEDGE equals 0, then falling edges on the pulse accumulator input pin (Port T
bit 7) causes the count to be incremented.
If PEDGE equals 1, then rising edges on the input cause the count to be
incremented.
When PAMOD equals one:
If PEDGE equals 0, when the pulse accumulator input pin goes high it enables an
internal clock which is connected to the pulse accumulator and the trailing falling
edge on the pulse accumulator input sets the PAIF flag. The internal clock used to
increment the pulse accumulator is 8MHz/64.
If PEDGE equals one, when the pulse accumulator input pin goes low it enables an
internal clock which is connected to the pulse accumulator and the trailing rising
edge on the pulse accumulator input sets the PAIF flag. The internal clock used to
increment the pulse accumulator is 8MHz/64.
The timer must be enable to use these since the clock generated is based on the
timer prescaler.
CLK1 and CLK0 are used to control the clock rate at which the pulse accumulator is
incremented. The different options are listed in Table 7.
Table 7: Pulse Accumulator Clock Rates
CLK1 CLK0
Selected clock__
0
0
timer prescaler
0
1
8MHz clock
1
0
8MHz/256 clock
1
1
8MHz/65536 clock
PAI is the Pulse Accumulator Edge triggered interrupt enable. This must be set to 1
to enable edge triggered interrupts.
_H12PACTL:
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
unused
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
After setting PACTL, the hardware will trigger an interrupt whenever the correct
edge is detected at Port T. The ISR must clear the flag by writing a one to the
Pulse Accumulator Interrupt Flag (PAIF) in _H12PAFLG.
Summary of Contents for 68HC12
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