17
Interrupt Priority:
Interrupts on the 68HC12 do not all occur simultaneously. Rather there is a
hierarchy of priority for the interrupts. The default priority order is:
1) Reset
2) COP Clock Monitor Fail Reset
3) COP Failure Reset
4) Trap
5) SWI
6) XIRQ
7) IRQ
8) RTI
9) Timer0
10) Timer1
11) Timer2
12) Timer3
13) Timer4
14) Timer5
15) Timer6
16) Timer7
17) TimerOvf
18) PAOvf
19) PAEdge
20) SPI
21) SCI0
22) SCI1
23) AtoD
24) PortJKey
25) PortHKey
The priority of these can be changed by using _H12HPRIO register. The first six
interrupts are unmaskable and can not have their priority changed. The other
interrupts are all maskable and may have their priority changed. An interrupt may
be made the highest priority interrupt by writing its address value to _H12HPRIO.
The address values are listed below in hex for each interrupt:
IRQ:
F2
RTI:
F0
Timer0:
EE
Timer1:
EC
Timer2:
EA
Timer3:
E8
Timer4:
E6
Timer5:
E4
Timer6:
E2
Timer7:
E0
TimerOvf:
DE
PAOvf:
DC
PAEdge:
DA
SPI:
D8
SCI0:
D6
SCI1:
D4
AtoD:
D2
PortJKey:
D0
PortHKey:
CE
Summary of Contents for 68HC12
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