B-1
Bus Interface FPGA
‘BlackPearl’
ALTERA Cyclone-III
(EP3C5F256C8N)
SH_W
E0
N_F/1/
2/3
SH_S
DCL
K
_F/S
DCKE
SH
_WE0N_
F
SH
_RDN
_F
S
H_FLCSN_F
DH/DK
[FFC-30pin/30pin]
SH_A
DDR
**_F[16
:1]
SH_D
ATA**
_F[
31:0]
Data Bus(SH_DATA[31:0])
Control Bus
2.5V
1.2V
TO PCB-DRIVE
Address Bus(SH_ADDR[21:1])
IC7202
256Mbit SDRAM1
(16Mx16)
IC7203
256Mbit SDRAM2
(16Mx16)
FPGA
Co
nfigu
rat
ion
IC7002
Reset IC
RSTN
S3.3V
IC7205
RFID Controller
IC7204
16Mbit
Flash Memory
X7200
13.56MHz
X’tal
S3.3V
S3.3V
5.0V
S3.3V
RSTN
TO HEAD
BH_
CLK1/C
LK2_F
BH_
LATN_F
BH_STRBN_F
RSTN
TO JTAG
de
bu
gger
TO JI
GU-Boar
d
3.3V
S3.3V
1.2V
X7002
16.67MHz
X’tal
X7001
48.0MHz
X’tal
IC7400
FPGA
Xilinx Spartan-3A
(XC3S400A-4FGG320C)
4
41
16
6
FPGACSN_F, WE[H/L], RD
INT
IC7000
CPU
SH7203
UBC
(debug
I/
F)
SS
U
(2c
h)
U
SB 2.0
I2C
(4
ch)
A
/D(8
ch)
D/
A
(2c
h)
SCIF
(4ch;
UAR
T
)
EXTAL
USB_X1
RSTN
AD
_B
H
T
H
E
R
M
IC7701
DC-DC
1.2V
U5.0V
S3.3V
5.
0V
3.
3V
S3.
3V
Ch.0
Moto
r C
urre
nt
B_
HUM
ID
/B_THERM
S3
.3V
5.0V
TO Antenna
19
15
3.3V
5.0V
TO PCB-P
OW
ER
4
41
19
BH_
D
ATA*
*_F
X7400
60MHz
SSG CLK
60MHz
FPGACLK_ENB
FPGA_RSTN
2
S3.3V
M
echa
Con
tro
l
BRF_ANT
TO PCB-INK
S
H_SD
A
1/S
C
L1
HEADV_ADJ
TO Head
Fan
(M
7)
HFAN_ON
AD_24V
S3.3V
24V
FANLOCK1
FANLOCK2
TO PCB-P
O
W
E
R
3.
3V
Ch.1
2SC2873-Y
24V
SFAN_ON
to
???
Fa
n
(M9)
A/
D
; D/
A
Ch.3
SH_TXD0/RXD0
24V
DS
[S-
10pin]
DN
[S-
2pin]
DP
[E-7pin]
DG
[S-2pin]
DRA/DRB
[FFC-30pin/30pin]
DA
[S-2pin]
DI
[S-5pin]
J7001
(US
B
)
J7002
[M
AC
8-14
pin
]
DF
[S-9pin
]
S
H
_SD
A
1/S
CL1
UPWR_ENB
U5.0V
S3.3V
IC7700
8ch D/A
IC7702
Dropper
24
V
2SA1213
TO Host
-PC
SH_DATA**_F
[15:0]
SH_ADDR**_F
[21:1]
SiTime
MPWR_ENB
SH_TXD
2/R
X
D2
2SC2873-Y
PCB-DIGITAL BLOCK DIAGRAM
Summary of Contents for CP-D70DW
Page 20: ... 1 EXPOSED ...
Page 24: ... 5 ...
Page 36: ... 17 ...
Page 51: ... 1 EXPLODED ...
Page 55: ... 5 ...
Page 59: ... 9 ...
Page 75: ... 1 PARTSLIST ...
Page 85: ... MEMO ...