8
M722 N/B MAINTENANCE
M722 N/B MAINTENANCE
Voltage reduction technology
Advanced Pentium III processor clock control
Quick Start for low power, low exit latency clock “throttling”
Deep Sleep mode for extremely low power dissipation
Thermal diode for measuring processor temperature
0.2.2 Intel 82440MX-100 Chipset Host Bridge
64-bit GTL+ based Host Bus Interface
32-bit Host address Support
64-bit Main Memory Interface with optimized support for SDRAM at 100 MHz
32-bit Primary PCI Bus Interface (PCI) with integrated PCI arbiter
Extensive Data Buffering between all interfaces for high throughput and concurrent operations.
Mobile and
“Deep Green”
Desktop power management support.
Host bridge for translation from CPU bus cycle to PCI bus cycle
Integrated IDE controller with Ultra DMA/33 support.
Processor/Host bus support
Optimized for mobile Celeron processors or Pentium III processors at 100MHz host bus frequency
Supports 32-bit mobile Celeron processor / Pentium III processor bus addressing.
4 or 1 deep in-order queue; 4 or 1 deep request queue
Supports uni-processor systems only
In-order transaction and dynamic deferred transaction support
GTL+ bus driver technology (gated GTL+ receivers for reduced power)
Integrated DRAM controller
8 to 512 Mbytes .
Supports up to 2 double-sided SO-DIMMs (4-row memory).
64-bit data interface without ECC support.
Unbuffered SDRAM Support (x-1-1-1 access @ 100 MHz).
Support only 3.3v DIMM DRAM configuration.
Enhanced SDRAM Open Page Architecture Support for 16- and 64-Mbit DRAM devices with 2k, 4k and 8k page sizes
Max address decode A0..A11, BA0, BA1
PCI bus interface
PCI Rev. 2.2, 3.3V, 33MHz interface compliant.
4 PCI bus masters support for combination of Graphic, LAN, Card Bus, and IEEE1394
PCI Parity Generation Support.
Data streaming support from PCI to DRAM.
Delayed Transaction supports for PCI-DRAM Reads.
Supports concurrent CPU, and PCI transactions to main memory.
Power Management Functions
