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M722 N/B MAINTENANCE
M722 N/B MAINTENANCE
3.2 Intel 82443MX Host Bridge Controller
Signal
Type Description
PLOCK# I/O
PCI Loc
k. Indicates an exclusive bus operation and may require multiple
transactions to complete. The 440MX asserts PLOCK# when it is doing non-exclusive
transactions on PCI. PLOCK# is ignored when PCI masters are
granted the bus.
PME# /
I / I/O
PCI Power Management Even
t. Driven by PCI peripherals to wake the system
GPIO(0)
from low-power states S1-S5. Now included in the PCI specification.
PREQ[3]# / I/O
PCI Request
s. 4 channels of bus master on the PCI bus.
GPIO(29)
PREQ[2:0]#
REQA# / I
PC/PCI DMA Reques
t. See Section 7.7 for a description.
GPIO(2) If the PC/PCI request is not needed, this signal can be used as a GPIO.
SERR# I/OD
System Erro
r. SERR# can be pulsed active by any PCI device that detects a
system error condition. Upon sampling SERR# active, the 440MX can be
programmed to generate an NMI, SMI#, or interrupt. Some internal conditions
can also cause the 440MX to drive SERR# active.
STOP# I/O
Sto
p. STOP# indicates that the 440MX, as a Target, is requesting an initiator to
stop the current transaction. As an Initiator, STOP# causes the 440MX to stop
the current transaction. STOP# is an output when the 440MX is a Target and an
input when the 440MX is an Initiator. STOP# is three-stated from the leading
edge of PCIRST#. STOP# remains three-stated until driven by the 440MX as a
slave.
TRDY# I/O
Target Read
y. TRDY# indicates the 440MX's ability to complete the current data
phase of the transaction. TRDY# is used in conjunction with IRDY#. A data
phase is completed when both TRDY# and IRDY# are sampled asserted. During
a read, TRDY# indicates that the 440MX, as a Target, has placed valid data on
AD[31:0]. During a write, it indicates the 440MX, as a Target is prepared to latch
data. TRDY# is an input to the 440MX when the 440MX is the Initiator and an
output when the 440MX is a Target. TRDY# is three-stated from the leading edge
of PCIRST#. TRDY# remains three-stated by the 440MX until driven as a target.
FRAME# I/O
Cycle Fram
e. FRAME# is driven by the current Initiator to indicate the beginning
and duration of an access. While FRAME# is asserted data transfers continue.
When FRAME# is negated the transaction is in the final data phase. FRAME# is
an input to the 440MX when it is the target. FRAME# is an output when the
440MX is the initiator and remains three-stated by the 440MX until driven as an
initiator.
GNTA# /
O / IO
PC/PCI DMA Acknowledg
e. See Section 7.7 for a description.
GPIO(3)
If the PC/PCI request is not needed, these can be used as general-purpose
inputs.
IRDY#
I/O
Initiator Read
y. IRDY# indicates the 440MX's ability, as an Initiator, to complete
the current data phase of the transaction. It is used in conjunction with TRDY#.
A data phase is completed on any clock when both IRDY# and TRDY# are
sampled asserted. During a write, IRDY# indicates the 440MX has valid data
present on AD[31:0]. During a read, it indicates the 440MX is prepared to latch
data. IRDY# is an input to the 440MX when the 440MX is the Target and an
output when the 440MX is an Initiator. IRDY# remains three-stated by the 440MX
until driven as an initiator.
PAR I/O
Calculated Parit
y. PAR is "even" parity and is calculated on 36 bits — AD[31:0]
plus C/BE[3:0]#. "Even" parity means that the number of "1"s within the 36 bits
plus PAR is counted and the sum is always even. PAR is always calculated on
36 bits regardless of the valid byte enables. PAR is generated for address and
data phases and is only guaranteed to be valid one PCI clock after the
corresponding address or data phase. PAR is driven and three-stated identically
to the AD[31:0] lines except that PAR is delayed by exactly one PCI clock. PAR
is an output during the address phase (delayed one clock) for all 440MX-initiated
transactions. It is also an output during the data phase (delayed one clock) when
the 440MX is the Initiator of a PCI write transaction, and when it is the Target of a
read transaction.
PCIRST# O
PCI Rese
t. The 440MX asserts PCIRST# to reset devices that reside on the PCI
bus. The 440MX asserts PCIRST# during power-up and when a hard Reset
sequence is initiated through the RC (CF9h) Register. PCIRST# is driven
inactive a minimum of 1 ms after PWROK is driven active. PCIRST# is driven for
a minimum of 1 ms when initiated through the RC Register. PCIRST# is asserted
after PWROK is de-asserted in the STR state.
PGNT[3]# / I/O
PCI Grant
s. 4 channels of bus master on the PCI bus.
GPIO(30)
PGNT[3]# is multiplexed with GPIO.
PGNT[2:0]#
PIRQ(A-B)#, I/OD
PCI Interrupt Request
s. The PIRQx# signals can be routed to interrupts 3, 4, 5,
PIRQ(C-D)# / 6, 7, 9, 10, 11, 12, 14 or 15 as described in Section 7.10.1.8. Each PIRQx# line
GPIO(22:23) has a separate Route Control Register.
PIRQC# and PIRQD# are multiplexed with GPIO.
AC’97 Signal Description (1 of 2)
Signal Type
Description
AC_BIT_CLK I
AC’97 Bit Cloc
k. 12.288 MHz serial data clock
AC_RST# O
AC’97 Rese
t. Master H/W Reset
AC_SDATA_ I
AC’97 Serial Data I
n. Serial TDM data input
IN(0)
PCI I/F Signal Description (2 of 3)
PCI I/F Signal Description (3 of 3)
Signal Type
Description
