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M722 N/B MAINTENANCE
M722 N/B MAINTENANCE
3.2 Intel 82443MX Host Bridge Controller
GPIO Signal Description
Signal
Default
Description
Type*
GPIO[0,1,2,4,5,
Input
General Purpose I/
O. Handled by system processor. Some of the 31 GPIO
6,7,8,9,10,11,
signals are muxed with other functions. (See Section 4.1.2 for the GPIO
12,13,15,17,18, definition.)
20,21,22,23,24,
27,29,30] 3.3V only or 3.3/5V (3.3V drive with 5V tolerant). See Table 24 for details.
GPIO[3,14,16, Output
General Purpose I/
O. Handled by system processor. Some of the 31 GPIO
19,25,26,28] signals are muxed with other functions. (See Section 4.1.2 for the GPIO
definition.)
3.3V only or 3.3/5V (3.3V drive with 5V tolerant). See Table 24 for details.
Note:
*This table specifies the default direction of the pins selected as GPIOs
(GPIO_DIR Register Dev #7, Function 3, Power Management I/O Space).
SUSB# O
Power plane contro
l. Shuts off power to all non-critical systems when in the S3
(Suspend-to-RAM) state. This signal goes low to turn off the power.
SUSC#
O
Power plane contro
l. Shuts power to all non-critical systems when in the S4
(Suspend-to-Disk) or S5 (Soft Off) states. This signal goes low to turn off the
power.
SUSCLK O
Suspend Cloc
k. 32.768 KHz. This output signal from the Real Time Clock
generator circuit is used as the Refresh clock for the 440MX. This signal is
always running, except in the Suspend-to-Disk or Soft-Off states.
During Reset: Running
After Reset: Running
During POS, STR: Running
THRM# / I / I/O
Thermal Alar
m. Active low signal generated by external hardware to start the
GPIO(8) Hardware clock throttling mode. This signal can also generate an SMI# or an
SCI. This signal is muxed with GPIO(8).
EXSMI# /
I / I/O
External System Management Interrup
t. EXSMI# is a falling edge-triggered
GPIO(24)
input to the 440MX indicating that an external device is requesting the system to
enter SMM mode. When enabled, a falling edge on EXSMI# results in the
assertion of SMI# to the processor. EXSMI# is an asynchronous input to the
440MX. However, when the setup and hold times are met it is only required to be
asserted for one PCICLK. Once de-asserted it must remain de-asserted for at
least four PCICLKs to allow the edge detect logic to PCIRST#. An external pullup
should be placed on this signal if it is not used; otherwise it is not always
guaranteed to be driven.
EXSMI# can cause an SERR# (if enabled).
This signal resides on the RESUME plane.
If EXSMI# is not used, this signal can be used as a GPIO.
LID / GPIO(10) I / I/O
Li
d. Input from the lid button/switch. This signal can be used to generate wake
events or interrupts. This signal is muxed with GPIO(10).
PCISTP# O
Stop PCI Cloc
k. This signal is an output to the external clock generator to turn
off the PCI clock.
PWRBTN# I
Power Butto
n. This signal causes the SMI# or SCI to request that the system
enter a Sleep state. If already in a Sleep state, it causes a wake event. If
PWRBTN# is pressed for four seconds, it causes an unconditional transition
(power button override) to the S5 state with only the PWRBTN# available as a
wake event. An override occurs even if the system is in the S1-S4 states.
PWROK I
Power O
K. When asserted, PWROK is an indication to the 440MX that STR
(Suspend-to-RAM) power plane and PCICLK has been stable for at least 1 ms.
PWROK can be driven asynchronously. When PWROK is negated, the 440MX
asserts PCIRST# and RSTDRV. It also resets the processor.
RI# / GPIO(12) I / I/O
Ring Indicat
e. When asserted, this signal indicates that a telephone ringing
signal has been received by the modem and that the 440MX should wake up the
system to accept data from the call. This signal is muxed with GPIO(12).
RSMRST# I
Resume Well Rese
t. Used for resetting the Resume well. If using a PS’98
power supply, then no external RC circuit is required. Otherwise, a 1 ms delay is
needed.
SUS_STAT# O
Suspend Statu
s. This signal is asserted by the 440MX to indicate that the
system will be entering a low-power state soon. It can be used by peripherals as
an indication that they should isolate their outputs that may be going to powered-
off planes.
SUSA# O
Power plane control.
Shuts off power to all non-critical systems when in the S1
(Power-On Suspend) or S2 (Power-On Suspend w/ full Reset) state. This signal
goes low to turn off the power.
Signal Type
Description
Signal Type
Description
Power Management Signal Description (2 of 3 )
Power Management Signal Description (3 of 3 )