113
8175 N/B MAINTENANCE
8175 N/B MAINTENANCE
Name Type
Description
BPM[5:0]#
Input/
Output
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor which indicate
the status of breakpoints and programmable counters used for
monitoring processor performance. BPM[5:0]# should connect the
appropriate pins of all Pentium 4 processor in the 478-pin package
system bus agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP
port. PRDY# is a processor output used by debug tools to determine
processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP
port. PREQ# is used by debug tools to request debug operation of
the processor. Please refer to the
Intel® Pentium® 4 Processor in
the 478-pin Package and Intel® 850 Chipset Platform Design
Guide
for more detailed information.
These signals do not have on-die termination. the Intel®
Pentium® 4 Processor in the 478-pin Package and Intel® 850
Chipset Platform Design Guide for termination requirements.
BPRI#
Input
BPRI# (Bus Priority Request) is used to arbitrate for ownership of
the processor system bus. It must connect the appropriate pins of all
processor system bus agents. Observing BPRI# active (as asserted
by the priority agent) causes all other agents to stop issuing new
requests, unless such requests are part of an ongoing locked
operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by deasserting BPRI#.
BR0#
Input/
Output
BR0# drives the BREQ0# signal in the system and is used by the
processor to request the bus. During power-on configuration this pin
is sampled to determine the agent ID = 0.
This signal does not have on-die termination and must be
terminated.
BSEL[1:0]
Output
The BCLK[1:0] frequency select signals BSEL[1:0] are used to
select the processor input clock frequency. The required frequency
is determined by the processor, chipset and clock synthesizer. All
agents must operate at the same frequency. The Pentium 4
processor in the 478-pin package operates currently at a 400 MHz
system bus frequency (100 MHz BCLK[1:0] frequency). For more
information about these pins, including termination
recommendations.
COMP[1:0]
Analog COMP[1:0] must be terminated on the system board using precision
resistors. Refer to the
Intel® Pentium® 4 Processor in the 478-pin
Package and Intel® 850 Chipset Platform Design Guide
for details
on implementation.
Name Type
Description
D[63:0]#
Input/
Output
D[63:0]# (Data) are the data signals. These signals provide a 64-bit
data path between the processor system bus agents, and must
connect the appropriate pins on all such agents. The data driver
asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four
times in a common clock period. D[63:0]# are latched off the falling
edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16
data signals correspond to a pair of one DSTBP# and one DSTBN#.
The following table shows the grouping of data signals to data
strobes and DBI#.
Quad-Pumped Signal Groups
Data Group
DSTBN#/
DSTBP#
DBI#
D[15:0]# 0
0
D[31:16]# 1
1
D[47:32]# 2
2
D[63:48]# 3
3
Furthermore, the DBI# pins determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DBI#
signal. When the DBI# signal is active, the corresponding data
group is inverted and therefore sampled active high.
DBI[3:0]#
Input/
Output
DBI[3:0]# are source synchronous and indicate the polarity of the
D[63:0]# signals. The DBI[3:0]# signals are activated when the data
on the data bus is inverted. The bus agent will invert the data bus
signals if more than half the bits, within the covered group, would
change level in the next cycle.
DBI[3:0] Assignment To Data Bus
Bus Signal
Data Bus Signals
DBI3# D[63:48]#
DBI2# D[47:32]#
DBI1# D[31:16]#
DBI0# D[15:0]#
DBR#
Output
DBR# is used only in processor systems where no debug port is
implemented on the system board. DBR# is used by a debug port
interposer so that an in-target probe can drive system reset. If a
debug port is implemented in the system, DBR# is a no connect in
the system. DBR# is not a processor signal.
5.1 Pentium 4(Willamette/Northwood) mFC-PGA2 478 pin
