miriac MPX-S32G274A User Manual
V2.1
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© MicroSys Electronics GmbH 2020
4.12.15
SerDes
The S32G274A of fers two SerDes channels with f our lanes in total which can be
conf igured as PCIe or SGMII. In order to be co nsistent with the NXP
documentation they are referred to as “PCIE0” and “PCIE1”.
Each SerDes channel requires a clock which can be conf igured as 100MHz or
125MHz clock depending on PCIe or SGMII use. More inf ormation on SerDes
clocks can be obtained f rom chapter 4.4.
SerDes 0 (“PCIE0”):
Lane 0
Lane 1
Clock
PCIe x2
100 MHz
PCIe x1
SGMII 1.25 Gbps
100 MHz
SGMII 1.25 Gbps
SGMII 1.25 Gbps
125 MHz (100 MHz)
Table 34 SerDes 0: working modes
SerDes 1 (“PCIE1”):
Lane 0
Lane 1
Clock
PCIe x2
100 MHz
PCIe x1
SGMII 1.25 Gbps
100 MHz
SGMII 1.25 Gbps
SGMII 1.25 Gbps
125 MHz (100 MHz)
SGMII 3.125 Gbps
N/A
125 MHz
Table 35 SerDes 1: working modes
The MPX-S32G274A generates f our clock pairs. Two of them are routed to the
carrier (“CLKC”) and the other two to the SerDes PLLs of the SoC (“CLKM”). For
each SerDes “CLKC” and “CLKM” have the same frequency and can be controlled
via an electronic DIP switch.
The S32G274A can also be used as a PCIe endpoint. In this case, SerDes 0
(“PCIE0”) receives its clock pair from the carrier. In order to control the multiplexer
on the module, “SEL_CLK_RC/EP#” needs to be driven low.
However, root complex (RC) or endpoint (EP) mode is determined via sof tware.
Pin
Signal
Signal Conditioning
Function
T130
SEL_CLK_RC/EP#
PU: 10k
0
S32G274A is endpoint
(clock from carrier)
1
S32G274A is root complex
(clock from module)
Table 36 SerDes: root complex / endpoint
