miriac MPX-S32G274A User Manual
V2.1
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© MicroSys Electronics GmbH 2020
4.4
Clock Structure
The S32G274A of fers two SerDes channels with f our lanes in total which can be
conf igured as PCIe or SGMII. In order to be compliant with the NXP documentation
they are referred to as “PCIE0” and “PCIE1”.
Each SerDes channel requires a clock which can be conf igured as 100MHz or
125MHz clock depending on PCIe or SGMII use.
J12 (PI6C557)
S32G274A
“PCIE0” channel
Pin
Signal
Pin
Signal
I/O Range
Signal
conditioning
Frequency
15
CLK0+
→
AB15
PCIE0_CLK_P
HCSL
SR: 33R
PD: 49R9
100/125 MHz
14
CLK0-
→
AC15
PCIE0_CLK_N
HCSL
SR: 33R
PD: 49R9
100/125 MHz
Figure 4-3 Clock Structure