Microsemi UG0557 User Manual Download Page 50

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Board Components Placement

UG0557 User Guide Revision 4.0

The following figure shows the bottom view of the SmartFusion2 Advanced Development Kit silkscreen.

Figure 21 • Silkscreen Bottom View

R36

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A32

3P3V

PLL_S2

2P5V

3P3V

2P5V

3P3V

2P5V

3P3V

S3_PLL_L01

Summary of Contents for UG0557

Page 1: ...UG0557 User Guide SmartFusion2 SoC FPGA Advanced Development Kit ...

Page 2: ...e suitability of any products and to test and verify the same The information provided by Microsemi hereunder is provided as is where is and with all faults and the entire risk associated with such information is entirely with the Buyer Microsemi does not grant explicitly or implicitly to any party any patent rights licenses or any other IP rights whether with regard to such information itself or ...

Page 3: ...Board 11 4 2 Current Measurement 11 4 2 1 1 0 V or 1 2 V Current Sensing for Normal Operation 11 4 2 2 1 2 V Current Sensing for Flash Freeze Mode 12 4 3 Memory Interface 12 4 3 1 DDR3 SDRAM 12 4 4 SerDes Interface 14 4 4 1 SERDES0 Interface 14 4 4 2 SERDES1 Interface 15 4 4 3 SERDES2 Interface 16 4 4 4 SERDES3 Interface 17 4 5 USB Interface 18 4 6 Marvell PHY 88E1340S 18 4 7 Programming 19 4 8 FT...

Page 4: ...ign 45 8 Manufacturing Test 46 8 1 Programming M2S150 ADV DEV KIT 46 8 1 1 Validating Power Supply 46 8 1 2 Programming the FPGA Using Embedded FlashPro5 46 8 2 Running the Manufacturing Test 48 8 2 1 Setting Up Tera Term 48 8 2 2 Setting Up Jumpers 50 8 2 3 Running the Test 51 ...

Page 5: ... 23 Figure 19 SPST Interface 24 Figure 20 Silkscreen Top View 43 Figure 21 Silkscreen Bottom View 44 Figure 22 PCIe Demo Design Window 45 Figure 23 FlashPro Window 47 Figure 24 New Project Window 47 Figure 25 Configuring the Device 48 Figure 26 Tera Term New Connection Window 48 Figure 27 Tera Term New Connection Window 49 Figure 28 Tera Term Serial Port Setup Window 49 Figure 29 Test Menu 51 Figu...

Page 6: ...e 4 LEDs 8 Table 5 Test Points 9 Table 6 I O Voltage Rails 9 Table 7 Programming Jumper Selection 20 Table 8 50 MHz Clock 21 Table 9 100 MHz Clock 22 Table 10 LEDs 22 Table 11 Push Button Switches 23 Table 12 DIP Switches 24 Table 13 FMC HPC Connector J30 Pinout 25 Table 14 FMC LPC Connector J60 Pinout 36 Table 15 Jumper Settings for Manufacturing Test 50 ...

Page 7: ...ion 2 0 The following is a summary of the changes made in revision 2 0 of this document Throughout the document the part number was updated from M2S150 ADV DEV KIT ES to M2S150 ADV DEV KIT SAR 66855 Throughout the document the device number was updated from M2S150T 1FCG1152ES to M2S150TS 1FCG1152 SAR 66855 The MTD files link was updated For more information see Manufacturing Test page 46 SAR 60671...

Page 8: ...gram of the SmartFusion2 Advanced Development Kit Figure 1 SmartFusion2 Advanced Development Kit Block Diagram Table 1 Kit Contents Item Quantity SmartFusion2 Advanced Development Board with 150K LE M2S150TS 1FCG1152 device 1 USB A to Micro B cable 1 USB Micro A to A cable 1 USB A to Mini B cable 1 12 V 5 A power adapter 1 6PDUW XVLRQ 0 6 76 3 H GJH RQQHFWRU 21 86 3 86 DQH DQH DQH DQH 86 B 86 0LFU...

Page 9: ... x4 serializer and deserializer SerDes DDR3 memory JTAG Inter integrated circuit I2C Serial peripheral interface SPI Universal asynchronous receiver transmitter UART Dual gigabit Ethernet The SmartFusion2 memory management system supports 1 GB 4 256 MB on board DDR3 memory for data storage 256 MB DDR3 memory for error detection and correction ECC SECDED and 2 GB 2 1 GB memory for SPI flash devices...

Page 10: ...ected to SPI port 0 of the SmartFusion2 microcontroller subsystem MSS and another 1 gigabit SPI flash Micron N25Q00AA13GSF40G connected to the SmartFusion2 fabric Ethernet Two RJ45 connectors Ethernet jacks with built in magnetics interfacing with a Marvell 10 100 1000 BASE T physical layer PHY chip 88E1304S in Serial Gigabit Media Independent Interface SGMII mode The Marvell PHY device in turn in...

Page 11: ...he SmartFusion2 device to the J60 connector USB interface USB Micro AB connector interfacing with the high speed USB2 0 ULPI transceiver chip USB3320 which in turn interfaces with USB D port of the SmartFusion2 MSS DS1818 3 3V EconoReset A simple three pin voltage monitor and power on reset that holds reset for 150 ms for stabilization after power returns to tolerance OSC 100 100 MHz clock oscilla...

Page 12: ...e latest Keil MDK ARM Microcontroller Advanced Development Kit 3 2 Hardware Settings This section provides information about default jumper settings switches LEDs and DIP switches for the SmartFusion2 Advanced Development Kit 3 2 1 Jumper Settings Connect the jumpers with the default settings specified in the following table to evaluate the pre programmed demo design Table 3 Jumper Settings Jumper...

Page 13: ...ll PHY J14 Jumper to select either PHY_CONFIG1 or M2S_PHY_CONFIG1 for global hardware configuration CONFIG 1 Pin 1 2 CONFIG 1 connects to P2_LED 2 pin of 88E1340S Open Pin 2 3 CONFIG 1 connects to SmartFusion2 J8 pin MSIO80NB3 Open J15 Jumper to short AC test points for debugging It is recommended not to connect this jumper refer to the Marvell PHY Datasheet Two pin header Open J23 Jumper to provi...

Page 14: ...REG supply DS19 Indicates 1P5V_REG supply DS20 Indicates VDD_REG supply DS21 Indicates 2P5V_LDO supply DS22 Indicates VCCIO_LPC_VADJ supply DS23 Indicates VCCIO_HPC_VADJ supply DS24 Indicates 1P0V_PHY supply DS25 Indicates 1P8V supply DS28 Indicates 3P3V_LDO supply DS17 Indicates 5P0V supply DS29 Indicates 3P3V supply DS16 Indicates 12P0V supply DS27 Indicates VSS_BUS supply DS8 Indicates that DS8...

Page 15: ...LDO TP9 1 5 V TP10 0 75 V TP14 1 8 V TP27 VDDIO for the USB device TP24 PHY 1 0 V Table 6 I O Voltage Rails SmartFusion2 Bank I O Rail Voltage Bank0 VCCIO_HPC_VIO_B_M2S 3 3 V 2 5 V 1 8 V 1 5 V or 1 2 V Bank1 2P5V_LDO 2 5 V Bank2 1P5V_REG 1 5 V Bank3 3P3V 3 3 V Bank4 3P3V 3 3 V Bank5 VCCIO_HPC_VIO_B_M2S 3 3 V 2 5 V 1 8 V 1 5 V or 1 2 V Bank6 VCCIO_LPC_VADJ 2 5 V 1 8 V 1 5 V or 1 2 V Bank7 3P3V 3 3 ...

Page 16: ... 1 2 V Bank16 VCCIO_LPC_VADJ 2 5 V 1 8 V 1 5 V or 1 2 V Bank17 VCCIO_HPC_VADJ 3 3 V 2 5 V 1 8 V 1 5 V 1 2 V Bank18 VCCIO_HPC_VADJ 3 3 V 2 5 V 1 8 V 1 5 V or1 2 V VDD VDD_REG 1 2 V or 1 0 V VPP 3P3V_VPP 3 3 V VREF1 VREF1 0 75 V VREF2 0P75V_VTT_REF 0 75 V SERDES_x_PLL_VDDA PLL_SERDESx_VDDA 3 3 V SERDES_x_L01_VDDAPLL SERDESx_VDDPLL 2 5 V SERDES_x_VDD VDD_REG 1 2 V or 1 0 V Table 6 I O Voltage Rails c...

Page 17: ...pply brick to the J42 jumper to supply power to the board 2 Switch ON the SW7 power supply switch Figure 4 Powering Up the Board 4 2 Current Measurement This section provides information about current sensing in various modes 4 2 1 1 0 V or 1 2 V Current Sensing for Normal Operation For applications that require current measurement high precision operational amplifier circuitry U59 with gain 100 i...

Page 18: ... voltage measured across a sense resistor to power use the following equation Note Accuracy is 10 4 3 Memory Interface Dedicated I Os for MSS DDR and fabric DDR are available in the SmartFusion2 device 4 3 1 DDR3 SDRAM Four chips with 256 MB DDR3 memory are provided in the SmartFusion2 device as flexible volatile memory for user applications Additionally one chip with 256 MB DDR3 memory is provide...

Page 19: ... see the Board Level Schematics document provided separately 6PDUW XVLRQ 5 6 5 0 0 0 8 DWD 4 GGUHVV RQWURO OLQHV 5 6 5 0 0 0 8 6LQJOH ELW HUURU FRUUHFWLRQ DQG GXDO ELW HUURU GHWHFWLRQ 6 0 5 DQN 0 5 DQN 0 5 DQN 46 46 DWD 4 GGUHVV RQWURO OLQHV 46 46 5 6 5 0 0 0 8 0 5 GGUHVV RQWURO OLQHV 6 6 5 6 5 0 0 0 8 DWD 4 GGUHVV RQWURO OLQHV 46 46 5 6 5 0 0 0 8 DWD 4 GGUHVV RQWURO OLQHV 46 46 0 5 DQN 0 5 DQN ...

Page 20: ...hematics document provided separately 4 4 1 SERDES0 Interface The SERDES0 interface Lane 0 1 2 or 3 is directly routed to the PCIe connector The SerDes reference clocks are routed as follows SERDES0 reference clock 0 is directly routed from the PCIe connector to the SmartFusion2 device SERDES0 reference clock 1 is routed from the 100 MHz differential clock source LVDS clock oscillator through resi...

Page 21: ...r SERDES1 reference clock 1 is routed from the FMC connector through the clock buffer The output of the clock buffer is additionally routed to SmartFusion2 Advanced Development Kit board pins AF18 and AG18 The following figure shows the SERDES1 interface of the SmartFusion2 Advanced Development Board Figure 8 SERDES1 Interface 6PDUW XVLRQ 6 5 6 DQH 5 6 5 6 DQH 5 6 5 6 DQH 5 6 5 6 DQH 5 6 5 6 DQH 7...

Page 22: ...r SERDES2 reference clock 1 is routed from the FMC connector through the clock buffer The output of the clock buffer is additionally routed to SmartFusion2 Advanced Development Kit board pins AE17 and AF17 The following figure shows the SERDES2 interface of the SmartFusion2 Advanced Development Board Figure 9 SERDES2 Interface 6PDUW XVLRQ 6 5 6 DQH 5 6 5 6 DQH 5 6 5 6 DQH 5 6 5 6 DQH 5 6 5 6 DQH 7...

Page 23: ...connected from FMC connector or SMA connector through MUX SERDES3 reference clock 1 is connected from 125 MHz or 100 MHz through MUX The following figure shows the SERDES3 interface of the SmartFusion2 Advanced Development Board Figure 10 SERDES3 Interface 6PDUW XVLRQ 0 RQQHFWRU 3 6 5 6 DQH 5 6 5 6 DQH 7 6 5 6 DQH 7 6 5 6 DQH 5 6 5 6 DQH 5 6 5 6 DQH 7 6 5 6 DQH 5 6 5 6 DQH 7 0DUYHOO 3 0DJQHWLFV DF...

Page 24: ...two of these transceivers Each transceiver performs all the PHY functions for 100BASE TX and 1000BASE T full duplex or half duplex Ethernet on a CAT5 twisted pair cable The PHY device is connected to a user provided Ethernet cable through an RJ45 connector with built in magnetics Device 88E1340S supports Quad SGMII for direct connection to a SmartFusion2 chip It is configured through the CONFIG 3 ...

Page 25: ...programming SPI port can operate in SPI slave or SPI master modes For more information see SmartFusion2 and IGLOO2 Programming User Guide The following figure shows the programming interface of the SmartFusion2 Advanced Development Board Figure 13 Programming Interface KDQQOH 6PDUW XVLRQ 0DUYHOO 3 6 HDGHU 0 7 6 7 B 1 7 B287 6 5 6 DQH 5 6 5 6 DQH 7 6 5 6 DQH 5 6 5 6 DQH 7 DQN 5 5 1 0DJQHWLFV DFN 5 ...

Page 26: ...l Schematics document provided separately 4 8 FTDI Interface The FT4232H chip is a USB 2 0 high speed 480 Mbps to UART MPSSE interface with the following key features Single chip USB to quad serial ports in various configurations Entire USB protocol handled on the chip without requiring USB specific firmware programming USB 2 0 high speed 480 Mbps and full speed 12 Mbps compatibility Two MPSSEs on...

Page 27: ...r is connected to the FPGA fabric to provide a system reference clock An on chip SmartFusion2 PLL can be configured to generate a wide range of high precision clock frequencies The following table provides package and pin details of the 50 MHz oscillator The following figure shows the 50 MHz clock oscillator interface Figure 15 50 MHz Clock Oscillator Interface For more information see the Board L...

Page 28: ...as well as push button switches 4 11 1 User LEDs The board has eight active high LEDs connected to the SmartFusion2 device that can be used to debug applications The following table lists the on board user LEDs Table 9 100 MHz Clock SmartFusion2 Advanced Development Kit Pin Name SmartFusion2 Package Pin Number SmartFusion2 Device Pin Name 100MHZ_DIFFCLK_P N1 MSIO40PB4 CCC_NE1_CLKI1 100MHZ_DIFFCLK_...

Page 29: ...rtFusion2 device The following table lists the on board push button switches The following figure shows the switches interface of the SmartFusion2 Advanced Development Board Figure 18 Switches Interface For more information see the Board Level Schematics document provided separately Table 11 Push Button Switches SmartFusion2 Advanced Development Board Pin SmartFusion2 Package Pin Number SmartFusio...

Page 30: ...e of the SmartFusion2 Advanced Development Board Figure 19 SPST Interface For more information see the Board Level Schematics document provided separately Table 12 DIP Switches SmartFusion2 Advanced Development Board Pin SmartFusion2 Package Pin Number SmartFusion2 Device Pin Name DIP0 F25 DDRIO152PB1 FDDR_DQ14 DIP1 G25 DDRIO152NB1 FDDR_DQ15 DIP2 J23 DDRIO153PB1 FDDR_DQ12 DIP3 J22 DDRIO153NB1 FDDR...

Page 31: ...ng table provides the FMC HPC header pinout details Table 13 FMC HPC Connector J30 Pinout FMC Pin Number J30 FMC Net Name SmartFusion2 Pin Number SmartFusion2 Pin name A1 GND A2 FMC_HPC_SERDES2_RXD2_P AM13 SERDES_2_RXD2_P A3 FMC_HPC_SERDES2_RXD2_N AL13 SERDES_2_RXD2_N A4 GND A5 GND A6 FMC_HPC_SERDES2_RXD1_P AM15 SERDES_2_RXD1_P A7 FMC_HPC_SERDES2_RXD1_N AL15 SERDES_2_RXD1_N A8 GND A9 GND A10 FMC_H...

Page 32: ...FMC_HPC_SERDES1_TXD2_N AN20 SERDES_1_TXD2_N A40 GND B1 NC B2 GND B3 GND B4 NC B5 NC B6 GND B7 GND B8 NC B9 NC B10 GND B11 GND B12 FMC_HPC_SERDES1_RXD0_P AL25 SERDES_1_RXD0_P B13 FMC_HPC_SERDES1_RXD0_N AM25 SERDES_1_RXD0_N B14 GND B15 GND B16 FMC_HPC_SERDES1_RXD1_P AL23 SERDES_1_RXD1_P B17 FMC_HPC_SERDES1_RXD1_N AM23 SERDES_1_RXD1_N B18 GND B19 GND B20 FMC_HPC_SERDES1_REFCLK0_P AJ22 MSIOD271PB12 SE...

Page 33: ..._TXD3_N AP10 SERDES_2_TXD3_N C4 GND C5 GND C6 FMC_HPC_SERDES2_RXD3_P AM11 SERDES_2_RXD3_P C7 FMC_HPC_SERDES2_RXD3_N AL11 SERDES_2_RXD3_N C8 GND C9 GND C10 HPC_LA06_M32_191P_B18 M32 MSIO191PB18 C11 HPC_LA06_M31_191N_B18 M31 MSIO191NB18 C12 GND C13 GND C14 HPC_LA10_T23_206P_B17 T23 MSIO206PB17 C15 HPC_LA10_T24_206N_B17 T24 MSIO206NB17 C16 GND C17 GND C18 HPC_LA14_P29_198P_B17 P29 MSIO198PB17 C19 HPC...

Page 34: ...0 SERDES_2_REFCLK0_P D5 FMC_HPC_SERDES2_REFCLK0_N AJ14 MSIOD277NB10 SERDES_2_REFCLK0_N D6 GND D7 GND D8 HPC_LA01_CC_U27_216P_B17 U27 MSIO216PB17 CCC_NW0_CLKI0 D9 HPC_LA01_CC_U26_216N_B17 U26 MSIO216NB17 D10 GND D11 HPC_LA05_N23_186P_B18 N23 MSIO186PB18 D12 HPC_LA05_N24_186N_B18 N24 MSIO186NB18 D13 GND D14 HPC_LA09_R23_200P_B17 R23 MSIO200PB17 D15 HPC_LA09_R24_200N_B17 R24 MSIO200NB17 D16 GND D17 H...

Page 35: ...CLKI E3 HPC_HA01_CC_AG16_276N_B11 AG16 MSIO276NB11 E4 GND E5 GND E6 HPC_HA05_AA3_17P_B6 AA3 MSIO17PB6 E7 HPC_HA05_AA2_17N_B6 AA2 MSIO17NB6 E8 GND E9 HPC_HA09_AJ2_285P_B8 AJ2 MSIO285PB8 E10 HPC_HA09_AH3_285N_B8 AH3 MSIO285NB8 E11 GND E12 HPC_HA13_AH6_283P_B8 AH6 MSIO283PB8 E13 HPC_HA13_AH5_283N_B8 AH5 MSIO283NB8 E14 GND E15 HPC_HA16_AG7_284P_B8 AG7 MSIO284PB8 E16 HPC_HA16_AF7_284N_B8 AF7 MSIO284NB8...

Page 36: ...B21_L26_174N_B0 L26 MSIO174NB0 E38 GND E39 VCCIO_HPC_VADJ E40 GND F1 HPC_PG_M2C_J6_78P_B3 J6 MSIO78PB3 MMUART_0_RI GPIO_21_B F2 GND F3 GND F4 HPC_HA00_CC_AJ4_282P_B8 AJ4 MSIO282PB8 VCCC_SE1_CLKI F5 HPC_HA00_CC_AJ3_282N_B8 AJ3 MSIO282NB8 F6 GND F7 HPC_HA04_AG3_287P_B8 AG3 MSIO287PB8 F8 HPC_HA04_AG4_287N_B8 AG4 MSIO287NB8 F9 GND F10 HPC_HA08_AD1_9P_B6 AD1 MSIO9PB6 F11 HPC_HA08_AC1_9N_B6 AC1 MSIO9NB6...

Page 37: ...PB5 USB_XCLK_B F38 HPC_HB20_W11_28N_B5 W11 MSIO28NB5 USB_DIR_B F39 GND F40 VCCIO_HPC_VADJ G1 GND G2 HPC_CLK1_M2C_AH28_267P_B14 AH28 MSIO267PB14 CCC_SW0_CLKI2 G3 HPC_CLK1_M2C_AG27_267N_B14 AG27 MSIO267NB14 G4 GND G5 GND G6 HPC_LA00_CC_U23_214P_B17 U23 MSIO214PB17 GB2 CCC_NW0_CLKI1 G7 HPC_LA00_CC_U24_214N_B17 U24 MSIO214NB17 G8 GND G9 HPC_LA03_N32_201P_B17 N32 MSIO201PB17 G10 HPC_LA03_N31_201N_B17 N...

Page 38: ..._176P_B18 E33 MSIO176PB18 G37 HPC_LA33_D33_176N_B18 D33 MSIO176NB18 G38 GND G39 VCCIO_HPC_VADJ G40 GND H1 N36608719 H2 HPC_PRSNT_M2CL_J7_78N_B3 J7 MSIO78NB3 MMUART_0_DCD GPIO_22_B H3 GND H4 HPC_CLK0_M2C_AJ6_281P_B8 AJ6 MSIO281PB8 GB15 VCCC_SE1_CLKI H5 HPC_CLK0_M2C_AJ5_281N_B8 AJ5 MSIO281NB8 H6 GND H7 HPC_LA02_K31_179P_B18 K31 MSIO179PB18 H8 HPC_LA02_K30_179N_B18 K30 MSIO179NB18 H9 GND H10 HPC_LA04...

Page 39: ...PC_LA30_F33_185N_B18 F33 MSIO185NB18 H36 GND H37 HPC_LA32_D34_180P_B18 D34 MSIO180PB18 H38 HPC_LA32_C34_180N_B18 C34 MSIO180NB18 H39 GND H40 VCCIO_HPC_VADJ J1 GND J2 HPC_CLK3_M2C_P AK12 MSIOD278PB10 SERDES_2_REFCLK1_P J2 HPC_CLK3_M2C_P AE17 MSIO275PB11 VCCC_SE0_CLKI J3 HPC_CLK3_M2C_N AJ12 MSIOD278NB10 SERDES_2_REFCLK1_N J3 HPC_CLK3_M2C_N AF17 MSIO275NB11 J4 GND J5 GND J6 HPC_HA03_AA4_12P_B6 AA4 MS...

Page 40: ...J33 HPC_HB15_V9_34P_B5 V9 MSIO34PB5 J34 HPC_HB15_V10_34N_B5 V10 MSIO34NB5 J35 GND J36 HPC_HB18_T2_31P_B5 T2 MSIO31PB5 USB_DATA2_B J37 HPC_HB18_T3_31N_B5 T3 MSIO31NB5 USB_DATA3_B J38 GND J39 VCCIO_HPC_VIO_B_M2C_FMC J40 GND K1 N36626276 K2 GND K3 GND K4 HPC_CLK2_M2C_P AJ20 MSIOD272PB12 SERDES_1_REFCLK1_P K4 HPC_CLK2_M2C_P AF18 MSIO274PB11 CCC_SW1_CLKI2 K5 HPC_CLK2_M2C_N AK20 MSIOD272NB12 SERDES_1_RE...

Page 41: ...B6 MSIO7NB6 K24 GND K25 HPC_HB00_CC_F32_172P_B0 F32 MSIO172PB0 GB0 CCC_NW0_CLKI3 K26 HPC_HB00_CC_E32_172N_B0 E32 MSIO172NB0 K27 GND K28 HPC_HB06_CC_J29_170P_B0 J29 MSIO170PB0 CCC_NW1_CLKI3 K29 HPC_HB06_CC_J28_170N_B0 J28 MSIO170NB0 K30 GND K31 HPC_HB10_Y10_22P_B5 Y10 MSIO22PB5 K32 HPC_HB10_Y9_22N_B5 Y9 MSIO22NB5 K33 GND K34 HPC_HB14_V6_33P_B5 V6 MSIO33PB5 USB_DATA6_B K35 HPC_HB14_U6_33N_B5 U6 MSIO...

Page 42: ...6 FMC_LPC_SERDES3_RXD0_P AM9 SERDES_3_RXD0_P C7 FMC_LPC_SERDES3_RXD0_N AL9 SERDES_3_RXD0_N C8 GND C9 GND C10 LPC_LA06_AF33_248P_B15 AF33 MSIOD248PB15 C11 LPC_LA06_AE33_248N_B15 AE33 MSIOD248NB15 C12 GND C13 GND C14 LPC_LA10_AE30_250P_B15 AE30 MSIOD250PB15 C15 LPC_LA10_AD30_250N_B15 AD30 MSIOD250NB15 C16 GND C17 GND C18 LPC_LA14_W23_227P_B16 W23 MSIOD227PB16 C19 LPC_LA14_W24_227N_B16 W24 MSIOD227NB...

Page 43: ...34 MSIOD219NB16 D10 GND D11 LPC_LA05_W29_226P_B16 W29 MSIOD226PB16 D12 LPC_LA05_W30_226N_B16 W30 MSIOD226NB16 D13 GND D14 LPC_LA09_Y28_231P_B16 Y28 MSIOD231PB16 D15 LPC_LA09_W28_231N_B16 W28 MSIOD231NB16 D16 GND D17 LPC_LA13_AC24_258P_B15 AC24 MSIOD258PB15 D18 LPC_LA13_AC23_258N_B15 AC23 MSIOD258NB15 D19 GND D20 LPC_LA17_CC_V23_220P_B16 V23 MSIOD220PB16 CCC_SW0_CLKI0 D21 LPC_LA17_CC_V24_220N_B16 V...

Page 44: ... G9 LPC_LA03_AC34_232P_B16 AC34 MSIOD232PB16 G10 LPC_LA03_AB34_232N_B16 AB34 MSIOD232NB16 G11 GND G12 LPC_LA08_AC32_233P_B16 AC32 MSIOD233PB16 G13 LPC_LA08_AC33_233N_B16 AC33 MSIOD233NB16 G14 GND G15 LPC_LA12_W26_229P_B16 W26 MSIOD229PB16 G16 LPC_LA12_W25_229N_B16 W25 MSIOD229NB16 G17 GND G18 LPC_LA16_Y23_234P_B16 Y23 MSIOD234PB16 G19 LPC_LA16_Y24_234N_B16 Y24 MSIOD234NB16 G20 GND G21 LPC_LA20_AF2...

Page 45: ...IO_ 12_B H3 GND H4 LPC_CLK0_M2C_V32_218P_B16 V32 MSIOD218PB16 GB1 CCC_SW0_CLK I1 H5 LPC_CLK0_M2C_V33_218N_B16 V33 MSIOD218NB16 H6 GND H7 LPC_LA02_AA33_225P_B16 AA33 MSIOD225PB16 H8 LPC_LA02_AA34_225N_B16 AA34 MSIOD225NB16 H9 GND H10 LPC_LA04_AD33_239P_B16 AD33 MSIOD239PB16 H11 LPC_LA04_AD34_239N_B16 AD34 MSIOD239NB16 H12 GND H13 LPC_LA07_AE31_247P_B15 AE31 MSIOD247PB15 H14 LPC_LA07_AE32_247N_B15 A...

Page 46: ... H29 LPC_LA24_AD29_249N_B15 AD29 MSIOD249NB15 H30 GND H31 LPC_LA28_AB25_246P_B15 AB25 MSIOD246PB15 H32 LPC_LA28_AB26_246N_B15 AB26 MSIOD246NB15 H33 GND H34 LPC_LA30_AC25_253P_B15 AC25 MSIOD253PB15 H35 LPC_LA30_AC26_253N_B15 AC26 MSIOD253NB15 H36 GND H37 LPC_LA32_AE26_259P_B15 AE26 MSIOD259PB15 H38 LPC_LA32_AD26_259N_B15 AD26 MSIOD259NB15 H39 GND H40 VCCIO_LPC_VADJ Table 14 FMC LPC Connector J60 Pi...

Page 47: ...n List UG0557 User Guide Revision 4 0 41 5 Pin List The SmartFusion2 Advanced Development Kit uses an M2S150TS 1FCG1152 device For a list of all package pins in this device see SmartFusion2 FC1152 Pinouts ...

Page 48: ...rd Components Placement UG0557 User Guide Revision 4 0 42 6 Board Components Placement The following figure shows the placement of various components on the SmartFusion2 Advanced Development Kit silkscreen ...

Page 49: ...C140 C139 C137 C183 C173 C172 C141 U2 R210 C174 C175 C179 C176 C177 U1 C178 C216 C215 U3 C94 C93 C91 C92 J4 J30 R266 R1212 R1210 R1208 R1207 R375 Y3 C359 C361 C360 Y4 C362 C220 C95 C96 J7 U5 U4 Y20 R1209 R1215 R1214 R378 R1211 R211C371 R69 R213 C599 C463 C422 C153 R70 C109 C150 U32 C645 TP10 C467 C519 C468 R209 R1213 C518 C119 C156 C236 C235 C199 R353 C648 R309 R311 C646 C644 C642 C641 TP22 R363 C...

Page 50: ...R982 R980 R981 C607 R1521 R82 U15 R77 R287 C1580 R979 U161 R1520 R832 CON1 R360 R357 R833 C121 C290 R296 C708 C1567 C1576 C1568 C1569 C1570 C1571 R23 R9 R32 R31 R358 R359 R85 R83 C1577 R5477 R5478 C42 R11 R13 C57 R21 C29 R20 C85 R22 R19 R18 R26 R6 R8 R15 R16 R28 R27 R29 C28 C36 C513 C417 C506 R204 C533 C509 C400 C453 C423 C510 C291 C261 C266 C267 C280 D15 R12 R14 C70 R24 R10 C63 R7 C15 R5 R37 C80 ...

Page 51: ...aded PCIe control plane design to demonstrate the PCIe interface of the SmartFusion2 device The following figure shows the PCIe demo design window Figure 22 PCIe Demo Design Window For more information about running the demo design see SmartFusion2 SoC FPGA PCIe Control Plane Demo Guide for Advanced Development Kit ...

Page 52: ...ment Board Short the J116 jumper to position 1 2 Short the J123 jumper to position 2 3 Short the J353 jumper to position 1 2 Short the J354 jumper to position 1 2 Short the J54 jumper to position 1 2 Note Before making the jumper connections switch OFF the SW7 power supply switch 2 Connect the 12 V 5 A power supply brick to the J42 jumper 3 Switch ON the SW7 power supply switch 8 1 2 Programming t...

Page 53: ... 47 Figure 23 FlashPro Window 4 Click New Project to create a new project 5 In the New Project window do the following and click OK Enter a project name Select Single device as the programming mode Figure 24 New Project Window 6 Click Configure Device ...

Page 54: ...rogrammed successfully 8 2 Running the Manufacturing Test This section describes how to run the manufacturing test for the SmartFusion2 Advanced Development Board 8 2 1 Setting Up Tera Term To set up Tera Term for the manufacturing test 1 Connect one end of the mini USB to Type A USB cable to J33 and other end to the USB port of the host PC 2 Launch Tera Term from the Start menu Figure 26 Tera Ter...

Page 55: ...ablish the connection with the host PC If FlashPro5 drivers are not installed properly the drop down list does not list FlashPro5 COM ports Figure 27 Tera Term New Connection Window 5 On the Tera Term Serial port setup window select the COM port to establish connection with the host PC and enter the following Tera Term settings Baud rate 57600 Data 8 bit Parity none Stop 1 bit Flow control none Fi...

Page 56: ...ry test Short J118 pin 1 2 SPI1 memory test Short J119 pin 1 2 USB device test Connect Micro B to P1 and connect the other end of the cable to the host PC type A This cable is required for testing on board USB device interface Short J23 pin 1 2 SGMII test Connect an Ethernet cable to J19 and connect other end of the cable to the 1 Gbps Ethernet switch or network Short J11 pin 1 2 Short J8 pin 1 2 ...

Page 57: ...150 ADV DEV KIT board to reset the board and begin the tests When the setup is completed all tests are listed in the HyperTerminal window as shown in the fol lowing figure Figure 29 Test Menu If the list of tests does not appear press the SW6 reset switch again If the list still does not appear then check all the jumpers and Tera Term settings 2 Press 1 to run the RTC test The following message ap...

Page 58: ... 3 Press 2 to run the I2C loopback test Wait for five seconds for the test to be run When the test is passed the following message appears Figure 32 I2C Test Passed 4 Press 3 to run the DDR3 memory test Wait for 30 seconds for the test to be run When the test is passed the following message appears Figure 33 DDR3 Memory Test Passed ...

Page 59: ...d the following message appears Figure 34 SPI0 Memory Test Passed 6 Press 5 to run the SPI1 memory test When the test is passed the following message is appears Figure 35 SPI1 Memory Test Passed 7 Press 6 to run the USB device test When the test begins the following message appears Figure 36 USB Device Test Passed ...

Page 60: ...g message appears Figure 37 SGMII Test Note If this message is not displayed or if DS10 and DS8 LEDs do not blink switch ON and OFF the SW7 power supply switch on the board and run the DDR3 test by pressing 3 11 Press 7 to repeat the SGMII test A confirmation message is displayed 12 Press n twice When the test is passed the IP address of the host PC is displayed as shown in the following figure Fi...

Page 61: ...d perform the following steps to get the IP address i Press 7 to run the SGMII test Figure 39 SGMII Debug Test ii Press 1 to restart auto negotiation and press y to continue Figure 40 SGMII Debug Test iii Press 2 to disable auto negotiation and press y to continue Figure 41 SGMII Debug Test ...

Page 62: ...g figure Figure 42 SGMII Debug Test Passed 15 Press SW6 to go back to the main menu 16 Press 8 to run the SerDes loopback test Note Ensure that the loopback cable is connected See Setting Up Jumpers page 50 Figure 43 SerDes Loopback Test 17 Press 1 to enable PRBS pattern for Lane 1 Figure 44 SerDes Loopback Test Enabling PRBS Pattern for Lane 1 ...

Page 63: ...57 User Guide Revision 4 0 57 18 Press 2 to read the status register for Lane 1 When the test is passed the following message appears Figure 45 SerDes Loopback Passed 19 Press the SW6 reset switch to go back to the main menu ...

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