Key Components Description and Operation
UG0557 User Guide Revision 4.0
18
4.5
USB Interface
The following figure shows the USB interface of the SmartFusion2 Advanced Development Board. The
SMSC USB3320 shown in the following figure is a high-speed USB 2.0 ULPI transceiver that provides
the industry standard UTMI+ low pin interface to connect the USB transceiver to the link. CPEN (shown
in the figure) is the external 5 V supply enable pin that controls the external VBUS power switch.
In the SmartFusion2 Advanced Development Kit, the USB interface can operate in host, device, and
OTG modes. To use device mode, J23 can either be in open or shorted. To use host or OTG mode, pins
1 and 2 of the
J23
jumper must be closed.
Figure 11 • USB Interface
For more information, see the Board Level Schematics document (provided separately).
4.6
Marvell PHY (88E1340S)
The SmartFusion2 Advanced Development Kit uses the on-board Marvell Alaska PHY device 88E1340S
for Ethernet communications at 10 or 1000 Mbps. The device has four independent gigabit Ethernet
transceivers; however, the board uses only two of these transceivers. Each transceiver performs all the
PHY functions for 100BASE-TX and 1000BASE-T full-duplex or half-duplex Ethernet on a CAT5
twisted-pair cable. The PHY device is connected to a user-provided Ethernet cable through an RJ45
connector with built-in magnetics.
Device 88E1340S supports Quad SGMII for direct connection to a SmartFusion2 chip. It is configured
through the CONFIG [3:0] and CLK_SEL [1:0] pins.
The CLK_SEL [1:0] pin is used to select the reference clock input. On the board, the status of the
CLK_SEL0 pin is
high
and the status of the CLK_SEL1 pin is
low
. REF_CLK is a 125 MHz reference
differential clock input (Y11). It consists of LVDS differential inputs with a 100
Ω
differential internal
termination resistor.
Key features of Marvell PHY 88E1340S are as follows.
•
RCLK: Gigabit recovered clock
•
SCLK: 25 MHz synchronous input reference clock
•
Expected reference clock (REF_CLK) specifications:
•
Voltage level: 3.3 (± 0.3) V
•
Differential LVDS
•Symmetry: 50% (± 10%)
•Rise/fall time: Maximum 1 ns @ 20% to 80% of supply (3.3 V)
•Output voltage levels: 0 = 0.90 minimum, 1.10 typical; 1 = 1.43 typical, 1.60 maximum
•Differential output voltage: 247 mV minimum, 454 mV maximum
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